1 /*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34 #include <asm/page.h>
35 #include <linux/mlx4/cq.h>
36 #include <linux/slab.h>
37 #include <linux/mlx4/qp.h>
38 #include <linux/skbuff.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/vmalloc.h>
42 #include <linux/tcp.h>
43 #include <linux/ip.h>
44 #include <linux/moduleparam.h>
45
46 #include "mlx4_en.h"
47
mlx4_en_create_tx_ring(struct mlx4_en_priv * priv,struct mlx4_en_tx_ring ** pring,int qpn,u32 size,u16 stride,int node,int queue_index)48 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
49 struct mlx4_en_tx_ring **pring, int qpn, u32 size,
50 u16 stride, int node, int queue_index)
51 {
52 struct mlx4_en_dev *mdev = priv->mdev;
53 struct mlx4_en_tx_ring *ring;
54 int tmp;
55 int err;
56
57 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
58 if (!ring) {
59 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
60 if (!ring) {
61 en_err(priv, "Failed allocating TX ring\n");
62 return -ENOMEM;
63 }
64 }
65
66 ring->size = size;
67 ring->size_mask = size - 1;
68 ring->stride = stride;
69 ring->full_size = ring->size - HEADROOM - MAX_DESC_TXBBS;
70
71 tmp = size * sizeof(struct mlx4_en_tx_info);
72 ring->tx_info = kmalloc_node(tmp, GFP_KERNEL | __GFP_NOWARN, node);
73 if (!ring->tx_info) {
74 ring->tx_info = vmalloc(tmp);
75 if (!ring->tx_info) {
76 err = -ENOMEM;
77 goto err_ring;
78 }
79 }
80
81 en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n",
82 ring->tx_info, tmp);
83
84 ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node);
85 if (!ring->bounce_buf) {
86 ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL);
87 if (!ring->bounce_buf) {
88 err = -ENOMEM;
89 goto err_info;
90 }
91 }
92 ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE);
93
94 /* Allocate HW buffers on provided NUMA node */
95 set_dev_node(&mdev->dev->pdev->dev, node);
96 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size,
97 2 * PAGE_SIZE);
98 set_dev_node(&mdev->dev->pdev->dev, mdev->dev->numa_node);
99 if (err) {
100 en_err(priv, "Failed allocating hwq resources\n");
101 goto err_bounce;
102 }
103
104 err = mlx4_en_map_buffer(&ring->wqres.buf);
105 if (err) {
106 en_err(priv, "Failed to map TX buffer\n");
107 goto err_hwq_res;
108 }
109
110 ring->buf = ring->wqres.buf.direct.buf;
111
112 en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n",
113 ring, ring->buf, ring->size, ring->buf_size,
114 (unsigned long long) ring->wqres.buf.direct.map);
115
116 ring->qpn = qpn;
117 err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp, GFP_KERNEL);
118 if (err) {
119 en_err(priv, "Failed allocating qp %d\n", ring->qpn);
120 goto err_map;
121 }
122 ring->qp.event = mlx4_en_sqp_event;
123
124 err = mlx4_bf_alloc(mdev->dev, &ring->bf, node);
125 if (err) {
126 en_dbg(DRV, priv, "working without blueflame (%d)\n", err);
127 ring->bf.uar = &mdev->priv_uar;
128 ring->bf.uar->map = mdev->uar_map;
129 ring->bf_enabled = false;
130 ring->bf_alloced = false;
131 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME;
132 } else {
133 ring->bf_alloced = true;
134 ring->bf_enabled = !!(priv->pflags &
135 MLX4_EN_PRIV_FLAGS_BLUEFLAME);
136 }
137
138 ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type;
139 ring->queue_index = queue_index;
140
141 if (queue_index < priv->num_tx_rings_p_up)
142 cpumask_set_cpu(cpumask_local_spread(queue_index,
143 priv->mdev->dev->numa_node),
144 &ring->affinity_mask);
145
146 *pring = ring;
147 return 0;
148
149 err_map:
150 mlx4_en_unmap_buffer(&ring->wqres.buf);
151 err_hwq_res:
152 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
153 err_bounce:
154 kfree(ring->bounce_buf);
155 ring->bounce_buf = NULL;
156 err_info:
157 kvfree(ring->tx_info);
158 ring->tx_info = NULL;
159 err_ring:
160 kfree(ring);
161 *pring = NULL;
162 return err;
163 }
164
mlx4_en_destroy_tx_ring(struct mlx4_en_priv * priv,struct mlx4_en_tx_ring ** pring)165 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
166 struct mlx4_en_tx_ring **pring)
167 {
168 struct mlx4_en_dev *mdev = priv->mdev;
169 struct mlx4_en_tx_ring *ring = *pring;
170 en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn);
171
172 if (ring->bf_alloced)
173 mlx4_bf_free(mdev->dev, &ring->bf);
174 mlx4_qp_remove(mdev->dev, &ring->qp);
175 mlx4_qp_free(mdev->dev, &ring->qp);
176 mlx4_en_unmap_buffer(&ring->wqres.buf);
177 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
178 kfree(ring->bounce_buf);
179 ring->bounce_buf = NULL;
180 kvfree(ring->tx_info);
181 ring->tx_info = NULL;
182 kfree(ring);
183 *pring = NULL;
184 }
185
mlx4_en_activate_tx_ring(struct mlx4_en_priv * priv,struct mlx4_en_tx_ring * ring,int cq,int user_prio)186 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
187 struct mlx4_en_tx_ring *ring,
188 int cq, int user_prio)
189 {
190 struct mlx4_en_dev *mdev = priv->mdev;
191 int err;
192
193 ring->cqn = cq;
194 ring->prod = 0;
195 ring->cons = 0xffffffff;
196 ring->last_nr_txbb = 1;
197 memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info));
198 memset(ring->buf, 0, ring->buf_size);
199
200 ring->qp_state = MLX4_QP_STATE_RST;
201 ring->doorbell_qpn = cpu_to_be32(ring->qp.qpn << 8);
202 ring->mr_key = cpu_to_be32(mdev->mr.key);
203
204 mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn,
205 ring->cqn, user_prio, &ring->context);
206 if (ring->bf_alloced)
207 ring->context.usr_page = cpu_to_be32(ring->bf.uar->index);
208
209 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context,
210 &ring->qp, &ring->qp_state);
211 if (!cpumask_empty(&ring->affinity_mask))
212 netif_set_xps_queue(priv->dev, &ring->affinity_mask,
213 ring->queue_index);
214
215 return err;
216 }
217
mlx4_en_deactivate_tx_ring(struct mlx4_en_priv * priv,struct mlx4_en_tx_ring * ring)218 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
219 struct mlx4_en_tx_ring *ring)
220 {
221 struct mlx4_en_dev *mdev = priv->mdev;
222
223 mlx4_qp_modify(mdev->dev, NULL, ring->qp_state,
224 MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp);
225 }
226
mlx4_en_is_tx_ring_full(struct mlx4_en_tx_ring * ring)227 static inline bool mlx4_en_is_tx_ring_full(struct mlx4_en_tx_ring *ring)
228 {
229 return ring->prod - ring->cons > ring->full_size;
230 }
231
mlx4_en_stamp_wqe(struct mlx4_en_priv * priv,struct mlx4_en_tx_ring * ring,int index,u8 owner)232 static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv,
233 struct mlx4_en_tx_ring *ring, int index,
234 u8 owner)
235 {
236 __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT));
237 struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE;
238 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
239 void *end = ring->buf + ring->buf_size;
240 __be32 *ptr = (__be32 *)tx_desc;
241 int i;
242
243 /* Optimize the common case when there are no wraparounds */
244 if (likely((void *)tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) {
245 /* Stamp the freed descriptor */
246 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE;
247 i += STAMP_STRIDE) {
248 *ptr = stamp;
249 ptr += STAMP_DWORDS;
250 }
251 } else {
252 /* Stamp the freed descriptor */
253 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE;
254 i += STAMP_STRIDE) {
255 *ptr = stamp;
256 ptr += STAMP_DWORDS;
257 if ((void *)ptr >= end) {
258 ptr = ring->buf;
259 stamp ^= cpu_to_be32(0x80000000);
260 }
261 }
262 }
263 }
264
265
mlx4_en_free_tx_desc(struct mlx4_en_priv * priv,struct mlx4_en_tx_ring * ring,int index,u8 owner,u64 timestamp)266 static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
267 struct mlx4_en_tx_ring *ring,
268 int index, u8 owner, u64 timestamp)
269 {
270 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
271 struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE;
272 struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset;
273 void *end = ring->buf + ring->buf_size;
274 struct sk_buff *skb = tx_info->skb;
275 int nr_maps = tx_info->nr_maps;
276 int i;
277
278 /* We do not touch skb here, so prefetch skb->users location
279 * to speedup consume_skb()
280 */
281 prefetchw(&skb->users);
282
283 if (unlikely(timestamp)) {
284 struct skb_shared_hwtstamps hwts;
285
286 mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp);
287 skb_tstamp_tx(skb, &hwts);
288 }
289
290 /* Optimize the common case when there are no wraparounds */
291 if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) {
292 if (!tx_info->inl) {
293 if (tx_info->linear)
294 dma_unmap_single(priv->ddev,
295 tx_info->map0_dma,
296 tx_info->map0_byte_count,
297 PCI_DMA_TODEVICE);
298 else
299 dma_unmap_page(priv->ddev,
300 tx_info->map0_dma,
301 tx_info->map0_byte_count,
302 PCI_DMA_TODEVICE);
303 for (i = 1; i < nr_maps; i++) {
304 data++;
305 dma_unmap_page(priv->ddev,
306 (dma_addr_t)be64_to_cpu(data->addr),
307 be32_to_cpu(data->byte_count),
308 PCI_DMA_TODEVICE);
309 }
310 }
311 } else {
312 if (!tx_info->inl) {
313 if ((void *) data >= end) {
314 data = ring->buf + ((void *)data - end);
315 }
316
317 if (tx_info->linear)
318 dma_unmap_single(priv->ddev,
319 tx_info->map0_dma,
320 tx_info->map0_byte_count,
321 PCI_DMA_TODEVICE);
322 else
323 dma_unmap_page(priv->ddev,
324 tx_info->map0_dma,
325 tx_info->map0_byte_count,
326 PCI_DMA_TODEVICE);
327 for (i = 1; i < nr_maps; i++) {
328 data++;
329 /* Check for wraparound before unmapping */
330 if ((void *) data >= end)
331 data = ring->buf;
332 dma_unmap_page(priv->ddev,
333 (dma_addr_t)be64_to_cpu(data->addr),
334 be32_to_cpu(data->byte_count),
335 PCI_DMA_TODEVICE);
336 }
337 }
338 }
339 dev_consume_skb_any(skb);
340 return tx_info->nr_txbb;
341 }
342
343
mlx4_en_free_tx_buf(struct net_device * dev,struct mlx4_en_tx_ring * ring)344 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring)
345 {
346 struct mlx4_en_priv *priv = netdev_priv(dev);
347 int cnt = 0;
348
349 /* Skip last polled descriptor */
350 ring->cons += ring->last_nr_txbb;
351 en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n",
352 ring->cons, ring->prod);
353
354 if ((u32) (ring->prod - ring->cons) > ring->size) {
355 if (netif_msg_tx_err(priv))
356 en_warn(priv, "Tx consumer passed producer!\n");
357 return 0;
358 }
359
360 while (ring->cons != ring->prod) {
361 ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring,
362 ring->cons & ring->size_mask,
363 !!(ring->cons & ring->size), 0);
364 ring->cons += ring->last_nr_txbb;
365 cnt++;
366 }
367
368 netdev_tx_reset_queue(ring->tx_queue);
369
370 if (cnt)
371 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt);
372
373 return cnt;
374 }
375
mlx4_en_process_tx_cq(struct net_device * dev,struct mlx4_en_cq * cq)376 static bool mlx4_en_process_tx_cq(struct net_device *dev,
377 struct mlx4_en_cq *cq)
378 {
379 struct mlx4_en_priv *priv = netdev_priv(dev);
380 struct mlx4_cq *mcq = &cq->mcq;
381 struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring];
382 struct mlx4_cqe *cqe;
383 u16 index;
384 u16 new_index, ring_index, stamp_index;
385 u32 txbbs_skipped = 0;
386 u32 txbbs_stamp = 0;
387 u32 cons_index = mcq->cons_index;
388 int size = cq->size;
389 u32 size_mask = ring->size_mask;
390 struct mlx4_cqe *buf = cq->buf;
391 u32 packets = 0;
392 u32 bytes = 0;
393 int factor = priv->cqe_factor;
394 int done = 0;
395 int budget = priv->tx_work_limit;
396 u32 last_nr_txbb;
397 u32 ring_cons;
398
399 if (!priv->port_up)
400 return true;
401
402 netdev_txq_bql_complete_prefetchw(ring->tx_queue);
403
404 index = cons_index & size_mask;
405 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor;
406 last_nr_txbb = ACCESS_ONCE(ring->last_nr_txbb);
407 ring_cons = ACCESS_ONCE(ring->cons);
408 ring_index = ring_cons & size_mask;
409 stamp_index = ring_index;
410
411 /* Process all completed CQEs */
412 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
413 cons_index & size) && (done < budget)) {
414 /*
415 * make sure we read the CQE after we read the
416 * ownership bit
417 */
418 rmb();
419
420 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
421 MLX4_CQE_OPCODE_ERROR)) {
422 struct mlx4_err_cqe *cqe_err = (struct mlx4_err_cqe *)cqe;
423
424 en_err(priv, "CQE error - vendor syndrome: 0x%x syndrome: 0x%x\n",
425 cqe_err->vendor_err_syndrome,
426 cqe_err->syndrome);
427 }
428
429 /* Skip over last polled CQE */
430 new_index = be16_to_cpu(cqe->wqe_index) & size_mask;
431
432 do {
433 u64 timestamp = 0;
434
435 txbbs_skipped += last_nr_txbb;
436 ring_index = (ring_index + last_nr_txbb) & size_mask;
437
438 if (unlikely(ring->tx_info[ring_index].ts_requested))
439 timestamp = mlx4_en_get_cqe_ts(cqe);
440
441 /* free next descriptor */
442 last_nr_txbb = mlx4_en_free_tx_desc(
443 priv, ring, ring_index,
444 !!((ring_cons + txbbs_skipped) &
445 ring->size), timestamp);
446
447 mlx4_en_stamp_wqe(priv, ring, stamp_index,
448 !!((ring_cons + txbbs_stamp) &
449 ring->size));
450 stamp_index = ring_index;
451 txbbs_stamp = txbbs_skipped;
452 packets++;
453 bytes += ring->tx_info[ring_index].nr_bytes;
454 } while ((++done < budget) && (ring_index != new_index));
455
456 ++cons_index;
457 index = cons_index & size_mask;
458 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor;
459 }
460
461
462 /*
463 * To prevent CQ overflow we first update CQ consumer and only then
464 * the ring consumer.
465 */
466 mcq->cons_index = cons_index;
467 mlx4_cq_set_ci(mcq);
468 wmb();
469
470 /* we want to dirty this cache line once */
471 ACCESS_ONCE(ring->last_nr_txbb) = last_nr_txbb;
472 ACCESS_ONCE(ring->cons) = ring_cons + txbbs_skipped;
473
474 netdev_tx_completed_queue(ring->tx_queue, packets, bytes);
475
476 /* Wakeup Tx queue if this stopped, and ring is not full.
477 */
478 if (netif_tx_queue_stopped(ring->tx_queue) &&
479 !mlx4_en_is_tx_ring_full(ring)) {
480 netif_tx_wake_queue(ring->tx_queue);
481 ring->wake_queue++;
482 }
483 return done < budget;
484 }
485
mlx4_en_tx_irq(struct mlx4_cq * mcq)486 void mlx4_en_tx_irq(struct mlx4_cq *mcq)
487 {
488 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
489 struct mlx4_en_priv *priv = netdev_priv(cq->dev);
490
491 if (priv->port_up)
492 napi_schedule(&cq->napi);
493 else
494 mlx4_en_arm_cq(priv, cq);
495 }
496
497 /* TX CQ polling - called by NAPI */
mlx4_en_poll_tx_cq(struct napi_struct * napi,int budget)498 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget)
499 {
500 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
501 struct net_device *dev = cq->dev;
502 struct mlx4_en_priv *priv = netdev_priv(dev);
503 int clean_complete;
504
505 clean_complete = mlx4_en_process_tx_cq(dev, cq);
506 if (!clean_complete)
507 return budget;
508
509 napi_complete(napi);
510 mlx4_en_arm_cq(priv, cq);
511
512 return 0;
513 }
514
mlx4_en_bounce_to_desc(struct mlx4_en_priv * priv,struct mlx4_en_tx_ring * ring,u32 index,unsigned int desc_size)515 static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv,
516 struct mlx4_en_tx_ring *ring,
517 u32 index,
518 unsigned int desc_size)
519 {
520 u32 copy = (ring->size - index) * TXBB_SIZE;
521 int i;
522
523 for (i = desc_size - copy - 4; i >= 0; i -= 4) {
524 if ((i & (TXBB_SIZE - 1)) == 0)
525 wmb();
526
527 *((u32 *) (ring->buf + i)) =
528 *((u32 *) (ring->bounce_buf + copy + i));
529 }
530
531 for (i = copy - 4; i >= 4 ; i -= 4) {
532 if ((i & (TXBB_SIZE - 1)) == 0)
533 wmb();
534
535 *((u32 *) (ring->buf + index * TXBB_SIZE + i)) =
536 *((u32 *) (ring->bounce_buf + i));
537 }
538
539 /* Return real descriptor location */
540 return ring->buf + index * TXBB_SIZE;
541 }
542
543 /* Decide if skb can be inlined in tx descriptor to avoid dma mapping
544 *
545 * It seems strange we do not simply use skb_copy_bits().
546 * This would allow to inline all skbs iff skb->len <= inline_thold
547 *
548 * Note that caller already checked skb was not a gso packet
549 */
is_inline(int inline_thold,const struct sk_buff * skb,const struct skb_shared_info * shinfo,void ** pfrag)550 static bool is_inline(int inline_thold, const struct sk_buff *skb,
551 const struct skb_shared_info *shinfo,
552 void **pfrag)
553 {
554 void *ptr;
555
556 if (skb->len > inline_thold || !inline_thold)
557 return false;
558
559 if (shinfo->nr_frags == 1) {
560 ptr = skb_frag_address_safe(&shinfo->frags[0]);
561 if (unlikely(!ptr))
562 return false;
563 *pfrag = ptr;
564 return true;
565 }
566 if (shinfo->nr_frags)
567 return false;
568 return true;
569 }
570
inline_size(const struct sk_buff * skb)571 static int inline_size(const struct sk_buff *skb)
572 {
573 if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg)
574 <= MLX4_INLINE_ALIGN)
575 return ALIGN(skb->len + CTRL_SIZE +
576 sizeof(struct mlx4_wqe_inline_seg), 16);
577 else
578 return ALIGN(skb->len + CTRL_SIZE + 2 *
579 sizeof(struct mlx4_wqe_inline_seg), 16);
580 }
581
get_real_size(const struct sk_buff * skb,const struct skb_shared_info * shinfo,struct net_device * dev,int * lso_header_size,bool * inline_ok,void ** pfrag)582 static int get_real_size(const struct sk_buff *skb,
583 const struct skb_shared_info *shinfo,
584 struct net_device *dev,
585 int *lso_header_size,
586 bool *inline_ok,
587 void **pfrag)
588 {
589 struct mlx4_en_priv *priv = netdev_priv(dev);
590 int real_size;
591
592 if (shinfo->gso_size) {
593 *inline_ok = false;
594 if (skb->encapsulation)
595 *lso_header_size = (skb_inner_transport_header(skb) - skb->data) + inner_tcp_hdrlen(skb);
596 else
597 *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb);
598 real_size = CTRL_SIZE + shinfo->nr_frags * DS_SIZE +
599 ALIGN(*lso_header_size + 4, DS_SIZE);
600 if (unlikely(*lso_header_size != skb_headlen(skb))) {
601 /* We add a segment for the skb linear buffer only if
602 * it contains data */
603 if (*lso_header_size < skb_headlen(skb))
604 real_size += DS_SIZE;
605 else {
606 if (netif_msg_tx_err(priv))
607 en_warn(priv, "Non-linear headers\n");
608 return 0;
609 }
610 }
611 } else {
612 *lso_header_size = 0;
613 *inline_ok = is_inline(priv->prof->inline_thold, skb,
614 shinfo, pfrag);
615
616 if (*inline_ok)
617 real_size = inline_size(skb);
618 else
619 real_size = CTRL_SIZE +
620 (shinfo->nr_frags + 1) * DS_SIZE;
621 }
622
623 return real_size;
624 }
625
build_inline_wqe(struct mlx4_en_tx_desc * tx_desc,const struct sk_buff * skb,const struct skb_shared_info * shinfo,int real_size,u16 * vlan_tag,int tx_ind,void * fragptr)626 static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc,
627 const struct sk_buff *skb,
628 const struct skb_shared_info *shinfo,
629 int real_size, u16 *vlan_tag,
630 int tx_ind, void *fragptr)
631 {
632 struct mlx4_wqe_inline_seg *inl = &tx_desc->inl;
633 int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl;
634 unsigned int hlen = skb_headlen(skb);
635
636 if (skb->len <= spc) {
637 if (likely(skb->len >= MIN_PKT_LEN)) {
638 inl->byte_count = cpu_to_be32(1 << 31 | skb->len);
639 } else {
640 inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN);
641 memset(((void *)(inl + 1)) + skb->len, 0,
642 MIN_PKT_LEN - skb->len);
643 }
644 skb_copy_from_linear_data(skb, inl + 1, hlen);
645 if (shinfo->nr_frags)
646 memcpy(((void *)(inl + 1)) + hlen, fragptr,
647 skb_frag_size(&shinfo->frags[0]));
648
649 } else {
650 inl->byte_count = cpu_to_be32(1 << 31 | spc);
651 if (hlen <= spc) {
652 skb_copy_from_linear_data(skb, inl + 1, hlen);
653 if (hlen < spc) {
654 memcpy(((void *)(inl + 1)) + hlen,
655 fragptr, spc - hlen);
656 fragptr += spc - hlen;
657 }
658 inl = (void *) (inl + 1) + spc;
659 memcpy(((void *)(inl + 1)), fragptr, skb->len - spc);
660 } else {
661 skb_copy_from_linear_data(skb, inl + 1, spc);
662 inl = (void *) (inl + 1) + spc;
663 skb_copy_from_linear_data_offset(skb, spc, inl + 1,
664 hlen - spc);
665 if (shinfo->nr_frags)
666 memcpy(((void *)(inl + 1)) + hlen - spc,
667 fragptr,
668 skb_frag_size(&shinfo->frags[0]));
669 }
670
671 wmb();
672 inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc));
673 }
674 }
675
mlx4_en_select_queue(struct net_device * dev,struct sk_buff * skb,void * accel_priv,select_queue_fallback_t fallback)676 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
677 void *accel_priv, select_queue_fallback_t fallback)
678 {
679 struct mlx4_en_priv *priv = netdev_priv(dev);
680 u16 rings_p_up = priv->num_tx_rings_p_up;
681 u8 up = 0;
682
683 if (dev->num_tc)
684 return skb_tx_hash(dev, skb);
685
686 if (vlan_tx_tag_present(skb))
687 up = vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT;
688
689 return fallback(dev, skb) % rings_p_up + up * rings_p_up;
690 }
691
mlx4_bf_copy(void __iomem * dst,const void * src,unsigned int bytecnt)692 static void mlx4_bf_copy(void __iomem *dst, const void *src,
693 unsigned int bytecnt)
694 {
695 __iowrite64_copy(dst, src, bytecnt / 8);
696 }
697
mlx4_en_xmit(struct sk_buff * skb,struct net_device * dev)698 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev)
699 {
700 struct skb_shared_info *shinfo = skb_shinfo(skb);
701 struct mlx4_en_priv *priv = netdev_priv(dev);
702 struct device *ddev = priv->ddev;
703 struct mlx4_en_tx_ring *ring;
704 struct mlx4_en_tx_desc *tx_desc;
705 struct mlx4_wqe_data_seg *data;
706 struct mlx4_en_tx_info *tx_info;
707 int tx_ind = 0;
708 int nr_txbb;
709 int desc_size;
710 int real_size;
711 u32 index, bf_index;
712 __be32 op_own;
713 u16 vlan_tag = 0;
714 int i_frag;
715 int lso_header_size;
716 void *fragptr = NULL;
717 bool bounce = false;
718 bool send_doorbell;
719 bool stop_queue;
720 bool inline_ok;
721 u32 ring_cons;
722
723 if (!priv->port_up)
724 goto tx_drop;
725
726 tx_ind = skb_get_queue_mapping(skb);
727 ring = priv->tx_ring[tx_ind];
728
729 /* fetch ring->cons far ahead before needing it to avoid stall */
730 ring_cons = ACCESS_ONCE(ring->cons);
731
732 real_size = get_real_size(skb, shinfo, dev, &lso_header_size,
733 &inline_ok, &fragptr);
734 if (unlikely(!real_size))
735 goto tx_drop;
736
737 /* Align descriptor to TXBB size */
738 desc_size = ALIGN(real_size, TXBB_SIZE);
739 nr_txbb = desc_size / TXBB_SIZE;
740 if (unlikely(nr_txbb > MAX_DESC_TXBBS)) {
741 if (netif_msg_tx_err(priv))
742 en_warn(priv, "Oversized header or SG list\n");
743 goto tx_drop;
744 }
745
746 if (vlan_tx_tag_present(skb))
747 vlan_tag = vlan_tx_tag_get(skb);
748
749
750 netdev_txq_bql_enqueue_prefetchw(ring->tx_queue);
751
752 /* Track current inflight packets for performance analysis */
753 AVG_PERF_COUNTER(priv->pstats.inflight_avg,
754 (u32)(ring->prod - ring_cons - 1));
755
756 /* Packet is good - grab an index and transmit it */
757 index = ring->prod & ring->size_mask;
758 bf_index = ring->prod;
759
760 /* See if we have enough space for whole descriptor TXBB for setting
761 * SW ownership on next descriptor; if not, use a bounce buffer. */
762 if (likely(index + nr_txbb <= ring->size))
763 tx_desc = ring->buf + index * TXBB_SIZE;
764 else {
765 tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf;
766 bounce = true;
767 }
768
769 /* Save skb in tx_info ring */
770 tx_info = &ring->tx_info[index];
771 tx_info->skb = skb;
772 tx_info->nr_txbb = nr_txbb;
773
774 data = &tx_desc->data;
775 if (lso_header_size)
776 data = ((void *)&tx_desc->lso + ALIGN(lso_header_size + 4,
777 DS_SIZE));
778
779 /* valid only for none inline segments */
780 tx_info->data_offset = (void *)data - (void *)tx_desc;
781
782 tx_info->inl = inline_ok;
783
784 tx_info->linear = (lso_header_size < skb_headlen(skb) &&
785 !inline_ok) ? 1 : 0;
786
787 tx_info->nr_maps = shinfo->nr_frags + tx_info->linear;
788 data += tx_info->nr_maps - 1;
789
790 if (!tx_info->inl) {
791 dma_addr_t dma = 0;
792 u32 byte_count = 0;
793
794 /* Map fragments if any */
795 for (i_frag = shinfo->nr_frags - 1; i_frag >= 0; i_frag--) {
796 const struct skb_frag_struct *frag;
797
798 frag = &shinfo->frags[i_frag];
799 byte_count = skb_frag_size(frag);
800 dma = skb_frag_dma_map(ddev, frag,
801 0, byte_count,
802 DMA_TO_DEVICE);
803 if (dma_mapping_error(ddev, dma))
804 goto tx_drop_unmap;
805
806 data->addr = cpu_to_be64(dma);
807 data->lkey = ring->mr_key;
808 wmb();
809 data->byte_count = cpu_to_be32(byte_count);
810 --data;
811 }
812
813 /* Map linear part if needed */
814 if (tx_info->linear) {
815 byte_count = skb_headlen(skb) - lso_header_size;
816
817 dma = dma_map_single(ddev, skb->data +
818 lso_header_size, byte_count,
819 PCI_DMA_TODEVICE);
820 if (dma_mapping_error(ddev, dma))
821 goto tx_drop_unmap;
822
823 data->addr = cpu_to_be64(dma);
824 data->lkey = ring->mr_key;
825 wmb();
826 data->byte_count = cpu_to_be32(byte_count);
827 }
828 /* tx completion can avoid cache line miss for common cases */
829 tx_info->map0_dma = dma;
830 tx_info->map0_byte_count = byte_count;
831 }
832
833 /*
834 * For timestamping add flag to skb_shinfo and
835 * set flag for further reference
836 */
837 tx_info->ts_requested = 0;
838 if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON &&
839 shinfo->tx_flags & SKBTX_HW_TSTAMP)) {
840 shinfo->tx_flags |= SKBTX_IN_PROGRESS;
841 tx_info->ts_requested = 1;
842 }
843
844 /* Prepare ctrl segement apart opcode+ownership, which depends on
845 * whether LSO is used */
846 tx_desc->ctrl.srcrb_flags = priv->ctrl_flags;
847 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
848 if (!skb->encapsulation)
849 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
850 MLX4_WQE_CTRL_TCP_UDP_CSUM);
851 else
852 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM);
853 ring->tx_csum++;
854 }
855
856 if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) {
857 struct ethhdr *ethh;
858
859 /* Copy dst mac address to wqe. This allows loopback in eSwitch,
860 * so that VFs and PF can communicate with each other
861 */
862 ethh = (struct ethhdr *)skb->data;
863 tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest);
864 tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2));
865 }
866
867 /* Handle LSO (TSO) packets */
868 if (lso_header_size) {
869 int i;
870
871 /* Mark opcode as LSO */
872 op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) |
873 ((ring->prod & ring->size) ?
874 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
875
876 /* Fill in the LSO prefix */
877 tx_desc->lso.mss_hdr_size = cpu_to_be32(
878 shinfo->gso_size << 16 | lso_header_size);
879
880 /* Copy headers;
881 * note that we already verified that it is linear */
882 memcpy(tx_desc->lso.header, skb->data, lso_header_size);
883
884 ring->tso_packets++;
885
886 i = ((skb->len - lso_header_size) / shinfo->gso_size) +
887 !!((skb->len - lso_header_size) % shinfo->gso_size);
888 tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size;
889 ring->packets += i;
890 } else {
891 /* Normal (Non LSO) packet */
892 op_own = cpu_to_be32(MLX4_OPCODE_SEND) |
893 ((ring->prod & ring->size) ?
894 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
895 tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
896 ring->packets++;
897 }
898 ring->bytes += tx_info->nr_bytes;
899 netdev_tx_sent_queue(ring->tx_queue, tx_info->nr_bytes);
900 AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len);
901
902 if (tx_info->inl)
903 build_inline_wqe(tx_desc, skb, shinfo, real_size, &vlan_tag,
904 tx_ind, fragptr);
905
906 if (skb->encapsulation) {
907 struct iphdr *ipv4 = (struct iphdr *)skb_inner_network_header(skb);
908 if (ipv4->protocol == IPPROTO_TCP || ipv4->protocol == IPPROTO_UDP)
909 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP);
910 else
911 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP);
912 }
913
914 ring->prod += nr_txbb;
915
916 /* If we used a bounce buffer then copy descriptor back into place */
917 if (unlikely(bounce))
918 tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size);
919
920 skb_tx_timestamp(skb);
921
922 /* Check available TXBBs And 2K spare for prefetch */
923 stop_queue = mlx4_en_is_tx_ring_full(ring);
924 if (unlikely(stop_queue)) {
925 netif_tx_stop_queue(ring->tx_queue);
926 ring->queue_stopped++;
927 }
928 send_doorbell = !skb->xmit_more || netif_xmit_stopped(ring->tx_queue);
929
930 real_size = (real_size / 16) & 0x3f;
931
932 if (ring->bf_enabled && desc_size <= MAX_BF && !bounce &&
933 !vlan_tx_tag_present(skb) && send_doorbell) {
934 tx_desc->ctrl.bf_qpn = ring->doorbell_qpn |
935 cpu_to_be32(real_size);
936
937 op_own |= htonl((bf_index & 0xffff) << 8);
938 /* Ensure new descriptor hits memory
939 * before setting ownership of this descriptor to HW
940 */
941 wmb();
942 tx_desc->ctrl.owner_opcode = op_own;
943
944 wmb();
945
946 mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl,
947 desc_size);
948
949 wmb();
950
951 ring->bf.offset ^= ring->bf.buf_size;
952 } else {
953 tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag);
954 tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN *
955 !!vlan_tx_tag_present(skb);
956 tx_desc->ctrl.fence_size = real_size;
957
958 /* Ensure new descriptor hits memory
959 * before setting ownership of this descriptor to HW
960 */
961 wmb();
962 tx_desc->ctrl.owner_opcode = op_own;
963 if (send_doorbell) {
964 wmb();
965 /* Since there is no iowrite*_native() that writes the
966 * value as is, without byteswapping - using the one
967 * the doesn't do byteswapping in the relevant arch
968 * endianness.
969 */
970 #if defined(__LITTLE_ENDIAN)
971 iowrite32(
972 #else
973 iowrite32be(
974 #endif
975 ring->doorbell_qpn,
976 ring->bf.uar->map + MLX4_SEND_DOORBELL);
977 } else {
978 ring->xmit_more++;
979 }
980 }
981
982 if (unlikely(stop_queue)) {
983 /* If queue was emptied after the if (stop_queue) , and before
984 * the netif_tx_stop_queue() - need to wake the queue,
985 * or else it will remain stopped forever.
986 * Need a memory barrier to make sure ring->cons was not
987 * updated before queue was stopped.
988 */
989 smp_rmb();
990
991 ring_cons = ACCESS_ONCE(ring->cons);
992 if (unlikely(!mlx4_en_is_tx_ring_full(ring))) {
993 netif_tx_wake_queue(ring->tx_queue);
994 ring->wake_queue++;
995 }
996 }
997 return NETDEV_TX_OK;
998
999 tx_drop_unmap:
1000 en_err(priv, "DMA mapping error\n");
1001
1002 while (++i_frag < shinfo->nr_frags) {
1003 ++data;
1004 dma_unmap_page(ddev, (dma_addr_t) be64_to_cpu(data->addr),
1005 be32_to_cpu(data->byte_count),
1006 PCI_DMA_TODEVICE);
1007 }
1008
1009 tx_drop:
1010 dev_kfree_skb_any(skb);
1011 priv->stats.tx_dropped++;
1012 return NETDEV_TX_OK;
1013 }
1014
1015