1 /*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
8 #include "qlcnic.h"
9 #include "qlcnic_hdr.h"
10
11 #include <linux/slab.h>
12 #include <net/ip.h>
13 #include <linux/bitops.h>
14
15 #define MASK(n) ((1ULL<<(n))-1)
16 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
17
18 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
19
20 #define CRB_BLK(off) ((off >> 20) & 0x3f)
21 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
22 #define CRB_WINDOW_2M (0x130060)
23 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
24 #define CRB_INDIRECT_2M (0x1e0000UL)
25
26 struct qlcnic_ms_reg_ctrl {
27 u32 ocm_window;
28 u32 control;
29 u32 hi;
30 u32 low;
31 u32 rd[4];
32 u32 wd[4];
33 u64 off;
34 };
35
36 #ifndef readq
readq(void __iomem * addr)37 static inline u64 readq(void __iomem *addr)
38 {
39 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
40 }
41 #endif
42
43 #ifndef writeq
writeq(u64 val,void __iomem * addr)44 static inline void writeq(u64 val, void __iomem *addr)
45 {
46 writel(((u32) (val)), (addr));
47 writel(((u32) (val >> 32)), (addr + 4));
48 }
49 #endif
50
51 static struct crb_128M_2M_block_map
52 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
53 {{{0, 0, 0, 0} } }, /* 0: PCI */
54 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
55 {1, 0x0110000, 0x0120000, 0x130000},
56 {1, 0x0120000, 0x0122000, 0x124000},
57 {1, 0x0130000, 0x0132000, 0x126000},
58 {1, 0x0140000, 0x0142000, 0x128000},
59 {1, 0x0150000, 0x0152000, 0x12a000},
60 {1, 0x0160000, 0x0170000, 0x110000},
61 {1, 0x0170000, 0x0172000, 0x12e000},
62 {0, 0x0000000, 0x0000000, 0x000000},
63 {0, 0x0000000, 0x0000000, 0x000000},
64 {0, 0x0000000, 0x0000000, 0x000000},
65 {0, 0x0000000, 0x0000000, 0x000000},
66 {0, 0x0000000, 0x0000000, 0x000000},
67 {0, 0x0000000, 0x0000000, 0x000000},
68 {1, 0x01e0000, 0x01e0800, 0x122000},
69 {0, 0x0000000, 0x0000000, 0x000000} } },
70 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
71 {{{0, 0, 0, 0} } }, /* 3: */
72 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
73 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
74 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
75 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
76 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
77 {0, 0x0000000, 0x0000000, 0x000000},
78 {0, 0x0000000, 0x0000000, 0x000000},
79 {0, 0x0000000, 0x0000000, 0x000000},
80 {0, 0x0000000, 0x0000000, 0x000000},
81 {0, 0x0000000, 0x0000000, 0x000000},
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {0, 0x0000000, 0x0000000, 0x000000},
91 {1, 0x08f0000, 0x08f2000, 0x172000} } },
92 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {0, 0x0000000, 0x0000000, 0x000000},
95 {0, 0x0000000, 0x0000000, 0x000000},
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {1, 0x09f0000, 0x09f2000, 0x176000} } },
108 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {0, 0x0000000, 0x0000000, 0x000000},
111 {0, 0x0000000, 0x0000000, 0x000000},
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
124 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
140 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
141 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
142 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
143 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
144 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
145 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
146 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
147 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
148 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
149 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
150 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
151 {{{0, 0, 0, 0} } }, /* 23: */
152 {{{0, 0, 0, 0} } }, /* 24: */
153 {{{0, 0, 0, 0} } }, /* 25: */
154 {{{0, 0, 0, 0} } }, /* 26: */
155 {{{0, 0, 0, 0} } }, /* 27: */
156 {{{0, 0, 0, 0} } }, /* 28: */
157 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
158 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
159 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
160 {{{0} } }, /* 32: PCI */
161 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
162 {1, 0x2110000, 0x2120000, 0x130000},
163 {1, 0x2120000, 0x2122000, 0x124000},
164 {1, 0x2130000, 0x2132000, 0x126000},
165 {1, 0x2140000, 0x2142000, 0x128000},
166 {1, 0x2150000, 0x2152000, 0x12a000},
167 {1, 0x2160000, 0x2170000, 0x110000},
168 {1, 0x2170000, 0x2172000, 0x12e000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000} } },
177 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
178 {{{0} } }, /* 35: */
179 {{{0} } }, /* 36: */
180 {{{0} } }, /* 37: */
181 {{{0} } }, /* 38: */
182 {{{0} } }, /* 39: */
183 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
184 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
185 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
186 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
187 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
188 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
189 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
190 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
191 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
192 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
193 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
194 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
195 {{{0} } }, /* 52: */
196 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
197 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
198 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
199 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
200 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
201 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
202 {{{0} } }, /* 59: I2C0 */
203 {{{0} } }, /* 60: I2C1 */
204 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
205 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
206 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
207 };
208
209 /*
210 * top 12 bits of crb internal address (hub, agent)
211 */
212 static const unsigned crb_hub_agt[64] = {
213 0,
214 QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
215 QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
216 QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
217 0,
218 QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
219 QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
220 QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
221 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
222 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
223 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
224 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
225 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
226 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
227 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
228 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
229 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
230 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
231 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
232 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
233 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
234 QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
235 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
236 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
237 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
238 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
239 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
240 0,
241 QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
242 QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
243 0,
244 QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
245 0,
246 QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
247 QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
248 0,
249 0,
250 0,
251 0,
252 0,
253 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
254 0,
255 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
256 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
257 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
258 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
259 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
260 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
261 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
262 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
263 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
264 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
265 0,
266 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
267 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
268 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
269 QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
270 0,
271 QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
272 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
273 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
274 0,
275 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
276 0,
277 };
278
279 static const u32 msi_tgt_status[8] = {
280 ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1,
281 ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3,
282 ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5,
283 ISR_INT_TARGET_STATUS_F6, ISR_INT_TARGET_STATUS_F7
284 };
285
286 /* PCI Windowing for DDR regions. */
287
288 #define QLCNIC_PCIE_SEM_TIMEOUT 10000
289
qlcnic_read_window_reg(u32 addr,void __iomem * bar0,u32 * data)290 static void qlcnic_read_window_reg(u32 addr, void __iomem *bar0, u32 *data)
291 {
292 u32 dest;
293 void __iomem *val;
294
295 dest = addr & 0xFFFF0000;
296 val = bar0 + QLCNIC_FW_DUMP_REG1;
297 writel(dest, val);
298 readl(val);
299 val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
300 *data = readl(val);
301 }
302
qlcnic_write_window_reg(u32 addr,void __iomem * bar0,u32 data)303 static void qlcnic_write_window_reg(u32 addr, void __iomem *bar0, u32 data)
304 {
305 u32 dest;
306 void __iomem *val;
307
308 dest = addr & 0xFFFF0000;
309 val = bar0 + QLCNIC_FW_DUMP_REG1;
310 writel(dest, val);
311 readl(val);
312 val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
313 writel(data, val);
314 readl(val);
315 }
316
317 int
qlcnic_pcie_sem_lock(struct qlcnic_adapter * adapter,int sem,u32 id_reg)318 qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
319 {
320 int timeout = 0, err = 0, done = 0;
321
322 while (!done) {
323 done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)),
324 &err);
325 if (done == 1)
326 break;
327 if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT) {
328 if (id_reg) {
329 done = QLCRD32(adapter, id_reg, &err);
330 if (done != -1)
331 dev_err(&adapter->pdev->dev,
332 "Failed to acquire sem=%d lock held by=%d\n",
333 sem, done);
334 else
335 dev_err(&adapter->pdev->dev,
336 "Failed to acquire sem=%d lock",
337 sem);
338 } else {
339 dev_err(&adapter->pdev->dev,
340 "Failed to acquire sem=%d lock", sem);
341 }
342 return -EIO;
343 }
344 usleep_range(1000, 1500);
345 }
346
347 if (id_reg)
348 QLCWR32(adapter, id_reg, adapter->portnum);
349
350 return 0;
351 }
352
353 void
qlcnic_pcie_sem_unlock(struct qlcnic_adapter * adapter,int sem)354 qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
355 {
356 int err = 0;
357
358 QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)), &err);
359 }
360
qlcnic_ind_rd(struct qlcnic_adapter * adapter,u32 addr)361 int qlcnic_ind_rd(struct qlcnic_adapter *adapter, u32 addr)
362 {
363 int err = 0;
364 u32 data;
365
366 if (qlcnic_82xx_check(adapter))
367 qlcnic_read_window_reg(addr, adapter->ahw->pci_base0, &data);
368 else {
369 data = QLCRD32(adapter, addr, &err);
370 if (err == -EIO)
371 return err;
372 }
373 return data;
374 }
375
qlcnic_ind_wr(struct qlcnic_adapter * adapter,u32 addr,u32 data)376 int qlcnic_ind_wr(struct qlcnic_adapter *adapter, u32 addr, u32 data)
377 {
378 int ret = 0;
379
380 if (qlcnic_82xx_check(adapter))
381 qlcnic_write_window_reg(addr, adapter->ahw->pci_base0, data);
382 else
383 ret = qlcnic_83xx_wrt_reg_indirect(adapter, addr, data);
384
385 return ret;
386 }
387
388 static int
qlcnic_send_cmd_descs(struct qlcnic_adapter * adapter,struct cmd_desc_type0 * cmd_desc_arr,int nr_desc)389 qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
390 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
391 {
392 u32 i, producer;
393 struct qlcnic_cmd_buffer *pbuf;
394 struct cmd_desc_type0 *cmd_desc;
395 struct qlcnic_host_tx_ring *tx_ring;
396
397 i = 0;
398
399 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
400 return -EIO;
401
402 tx_ring = &adapter->tx_ring[0];
403 __netif_tx_lock_bh(tx_ring->txq);
404
405 producer = tx_ring->producer;
406
407 if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
408 netif_tx_stop_queue(tx_ring->txq);
409 smp_mb();
410 if (qlcnic_tx_avail(tx_ring) > nr_desc) {
411 if (qlcnic_tx_avail(tx_ring) > TX_STOP_THRESH)
412 netif_tx_wake_queue(tx_ring->txq);
413 } else {
414 adapter->stats.xmit_off++;
415 __netif_tx_unlock_bh(tx_ring->txq);
416 return -EBUSY;
417 }
418 }
419
420 do {
421 cmd_desc = &cmd_desc_arr[i];
422
423 pbuf = &tx_ring->cmd_buf_arr[producer];
424 pbuf->skb = NULL;
425 pbuf->frag_count = 0;
426
427 memcpy(&tx_ring->desc_head[producer],
428 cmd_desc, sizeof(struct cmd_desc_type0));
429
430 producer = get_next_index(producer, tx_ring->num_desc);
431 i++;
432
433 } while (i != nr_desc);
434
435 tx_ring->producer = producer;
436
437 qlcnic_update_cmd_producer(tx_ring);
438
439 __netif_tx_unlock_bh(tx_ring->txq);
440
441 return 0;
442 }
443
qlcnic_82xx_sre_macaddr_change(struct qlcnic_adapter * adapter,u8 * addr,u16 vlan_id,u8 op)444 int qlcnic_82xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
445 u16 vlan_id, u8 op)
446 {
447 struct qlcnic_nic_req req;
448 struct qlcnic_mac_req *mac_req;
449 struct qlcnic_vlan_req *vlan_req;
450 u64 word;
451
452 memset(&req, 0, sizeof(struct qlcnic_nic_req));
453 req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
454
455 word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
456 req.req_hdr = cpu_to_le64(word);
457
458 mac_req = (struct qlcnic_mac_req *)&req.words[0];
459 mac_req->op = op;
460 memcpy(mac_req->mac_addr, addr, ETH_ALEN);
461
462 vlan_req = (struct qlcnic_vlan_req *)&req.words[1];
463 vlan_req->vlan_id = cpu_to_le16(vlan_id);
464
465 return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
466 }
467
qlcnic_nic_del_mac(struct qlcnic_adapter * adapter,const u8 * addr)468 int qlcnic_nic_del_mac(struct qlcnic_adapter *adapter, const u8 *addr)
469 {
470 struct qlcnic_mac_vlan_list *cur;
471 struct list_head *head;
472 int err = -EINVAL;
473
474 /* Delete MAC from the existing list */
475 list_for_each(head, &adapter->mac_list) {
476 cur = list_entry(head, struct qlcnic_mac_vlan_list, list);
477 if (ether_addr_equal(addr, cur->mac_addr)) {
478 err = qlcnic_sre_macaddr_change(adapter, cur->mac_addr,
479 0, QLCNIC_MAC_DEL);
480 if (err)
481 return err;
482 list_del(&cur->list);
483 kfree(cur);
484 return err;
485 }
486 }
487 return err;
488 }
489
qlcnic_nic_add_mac(struct qlcnic_adapter * adapter,const u8 * addr,u16 vlan)490 int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, const u8 *addr, u16 vlan)
491 {
492 struct qlcnic_mac_vlan_list *cur;
493 struct list_head *head;
494
495 /* look up if already exists */
496 list_for_each(head, &adapter->mac_list) {
497 cur = list_entry(head, struct qlcnic_mac_vlan_list, list);
498 if (ether_addr_equal(addr, cur->mac_addr) &&
499 cur->vlan_id == vlan)
500 return 0;
501 }
502
503 cur = kzalloc(sizeof(*cur), GFP_ATOMIC);
504 if (cur == NULL)
505 return -ENOMEM;
506
507 memcpy(cur->mac_addr, addr, ETH_ALEN);
508
509 if (qlcnic_sre_macaddr_change(adapter,
510 cur->mac_addr, vlan, QLCNIC_MAC_ADD)) {
511 kfree(cur);
512 return -EIO;
513 }
514
515 cur->vlan_id = vlan;
516 list_add_tail(&cur->list, &adapter->mac_list);
517 return 0;
518 }
519
__qlcnic_set_multi(struct net_device * netdev,u16 vlan)520 static void __qlcnic_set_multi(struct net_device *netdev, u16 vlan)
521 {
522 struct qlcnic_adapter *adapter = netdev_priv(netdev);
523 struct qlcnic_hardware_context *ahw = adapter->ahw;
524 struct netdev_hw_addr *ha;
525 static const u8 bcast_addr[ETH_ALEN] = {
526 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
527 };
528 u32 mode = VPORT_MISS_MODE_DROP;
529
530 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
531 return;
532
533 qlcnic_nic_add_mac(adapter, adapter->mac_addr, vlan);
534 qlcnic_nic_add_mac(adapter, bcast_addr, vlan);
535
536 if (netdev->flags & IFF_PROMISC) {
537 if (!(adapter->flags & QLCNIC_PROMISC_DISABLED))
538 mode = VPORT_MISS_MODE_ACCEPT_ALL;
539 } else if ((netdev->flags & IFF_ALLMULTI) ||
540 (netdev_mc_count(netdev) > ahw->max_mc_count)) {
541 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
542 } else if (!netdev_mc_empty(netdev)) {
543 netdev_for_each_mc_addr(ha, netdev)
544 qlcnic_nic_add_mac(adapter, ha->addr, vlan);
545 }
546
547 /* configure unicast MAC address, if there is not sufficient space
548 * to store all the unicast addresses then enable promiscuous mode
549 */
550 if (netdev_uc_count(netdev) > ahw->max_uc_count) {
551 mode = VPORT_MISS_MODE_ACCEPT_ALL;
552 } else if (!netdev_uc_empty(netdev)) {
553 netdev_for_each_uc_addr(ha, netdev)
554 qlcnic_nic_add_mac(adapter, ha->addr, vlan);
555 }
556
557 if (mode == VPORT_MISS_MODE_ACCEPT_ALL &&
558 !adapter->fdb_mac_learn) {
559 qlcnic_alloc_lb_filters_mem(adapter);
560 adapter->drv_mac_learn = 1;
561 if (adapter->flags & QLCNIC_ESWITCH_ENABLED)
562 adapter->rx_mac_learn = true;
563 } else {
564 adapter->drv_mac_learn = 0;
565 adapter->rx_mac_learn = false;
566 }
567
568 qlcnic_nic_set_promisc(adapter, mode);
569 }
570
qlcnic_set_multi(struct net_device * netdev)571 void qlcnic_set_multi(struct net_device *netdev)
572 {
573 struct qlcnic_adapter *adapter = netdev_priv(netdev);
574
575 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
576 return;
577
578 if (qlcnic_sriov_vf_check(adapter))
579 qlcnic_sriov_vf_set_multi(netdev);
580 else
581 __qlcnic_set_multi(netdev, 0);
582 }
583
qlcnic_82xx_nic_set_promisc(struct qlcnic_adapter * adapter,u32 mode)584 int qlcnic_82xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
585 {
586 struct qlcnic_nic_req req;
587 u64 word;
588
589 memset(&req, 0, sizeof(struct qlcnic_nic_req));
590
591 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
592
593 word = QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE |
594 ((u64)adapter->portnum << 16);
595 req.req_hdr = cpu_to_le64(word);
596
597 req.words[0] = cpu_to_le64(mode);
598
599 return qlcnic_send_cmd_descs(adapter,
600 (struct cmd_desc_type0 *)&req, 1);
601 }
602
qlcnic_82xx_free_mac_list(struct qlcnic_adapter * adapter)603 void qlcnic_82xx_free_mac_list(struct qlcnic_adapter *adapter)
604 {
605 struct list_head *head = &adapter->mac_list;
606 struct qlcnic_mac_vlan_list *cur;
607
608 while (!list_empty(head)) {
609 cur = list_entry(head->next, struct qlcnic_mac_vlan_list, list);
610 qlcnic_sre_macaddr_change(adapter,
611 cur->mac_addr, 0, QLCNIC_MAC_DEL);
612 list_del(&cur->list);
613 kfree(cur);
614 }
615 }
616
qlcnic_prune_lb_filters(struct qlcnic_adapter * adapter)617 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter)
618 {
619 struct qlcnic_filter *tmp_fil;
620 struct hlist_node *n;
621 struct hlist_head *head;
622 int i;
623 unsigned long expires;
624 u8 cmd;
625
626 for (i = 0; i < adapter->fhash.fbucket_size; i++) {
627 head = &(adapter->fhash.fhead[i]);
628 hlist_for_each_entry_safe(tmp_fil, n, head, fnode) {
629 cmd = tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
630 QLCNIC_MAC_DEL;
631 expires = tmp_fil->ftime + QLCNIC_FILTER_AGE * HZ;
632 if (time_before(expires, jiffies)) {
633 qlcnic_sre_macaddr_change(adapter,
634 tmp_fil->faddr,
635 tmp_fil->vlan_id,
636 cmd);
637 spin_lock_bh(&adapter->mac_learn_lock);
638 adapter->fhash.fnum--;
639 hlist_del(&tmp_fil->fnode);
640 spin_unlock_bh(&adapter->mac_learn_lock);
641 kfree(tmp_fil);
642 }
643 }
644 }
645 for (i = 0; i < adapter->rx_fhash.fbucket_size; i++) {
646 head = &(adapter->rx_fhash.fhead[i]);
647
648 hlist_for_each_entry_safe(tmp_fil, n, head, fnode)
649 {
650 expires = tmp_fil->ftime + QLCNIC_FILTER_AGE * HZ;
651 if (time_before(expires, jiffies)) {
652 spin_lock_bh(&adapter->rx_mac_learn_lock);
653 adapter->rx_fhash.fnum--;
654 hlist_del(&tmp_fil->fnode);
655 spin_unlock_bh(&adapter->rx_mac_learn_lock);
656 kfree(tmp_fil);
657 }
658 }
659 }
660 }
661
qlcnic_delete_lb_filters(struct qlcnic_adapter * adapter)662 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter)
663 {
664 struct qlcnic_filter *tmp_fil;
665 struct hlist_node *n;
666 struct hlist_head *head;
667 int i;
668 u8 cmd;
669
670 for (i = 0; i < adapter->fhash.fbucket_size; i++) {
671 head = &(adapter->fhash.fhead[i]);
672 hlist_for_each_entry_safe(tmp_fil, n, head, fnode) {
673 cmd = tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
674 QLCNIC_MAC_DEL;
675 qlcnic_sre_macaddr_change(adapter,
676 tmp_fil->faddr,
677 tmp_fil->vlan_id,
678 cmd);
679 spin_lock_bh(&adapter->mac_learn_lock);
680 adapter->fhash.fnum--;
681 hlist_del(&tmp_fil->fnode);
682 spin_unlock_bh(&adapter->mac_learn_lock);
683 kfree(tmp_fil);
684 }
685 }
686 }
687
qlcnic_set_fw_loopback(struct qlcnic_adapter * adapter,u8 flag)688 static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u8 flag)
689 {
690 struct qlcnic_nic_req req;
691 int rv;
692
693 memset(&req, 0, sizeof(struct qlcnic_nic_req));
694
695 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
696 req.req_hdr = cpu_to_le64(QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK |
697 ((u64) adapter->portnum << 16) | ((u64) 0x1 << 32));
698
699 req.words[0] = cpu_to_le64(flag);
700
701 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
702 if (rv != 0)
703 dev_err(&adapter->pdev->dev, "%sting loopback mode failed\n",
704 flag ? "Set" : "Reset");
705 return rv;
706 }
707
qlcnic_82xx_set_lb_mode(struct qlcnic_adapter * adapter,u8 mode)708 int qlcnic_82xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
709 {
710 if (qlcnic_set_fw_loopback(adapter, mode))
711 return -EIO;
712
713 if (qlcnic_nic_set_promisc(adapter,
714 VPORT_MISS_MODE_ACCEPT_ALL)) {
715 qlcnic_set_fw_loopback(adapter, 0);
716 return -EIO;
717 }
718
719 msleep(1000);
720 return 0;
721 }
722
qlcnic_82xx_clear_lb_mode(struct qlcnic_adapter * adapter,u8 mode)723 int qlcnic_82xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
724 {
725 struct net_device *netdev = adapter->netdev;
726
727 mode = VPORT_MISS_MODE_DROP;
728 qlcnic_set_fw_loopback(adapter, 0);
729
730 if (netdev->flags & IFF_PROMISC)
731 mode = VPORT_MISS_MODE_ACCEPT_ALL;
732 else if (netdev->flags & IFF_ALLMULTI)
733 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
734
735 qlcnic_nic_set_promisc(adapter, mode);
736 msleep(1000);
737 return 0;
738 }
739
qlcnic_82xx_read_phys_port_id(struct qlcnic_adapter * adapter)740 int qlcnic_82xx_read_phys_port_id(struct qlcnic_adapter *adapter)
741 {
742 u8 mac[ETH_ALEN];
743 int ret;
744
745 ret = qlcnic_get_mac_address(adapter, mac,
746 adapter->ahw->physical_port);
747 if (ret)
748 return ret;
749
750 memcpy(adapter->ahw->phys_port_id, mac, ETH_ALEN);
751 adapter->flags |= QLCNIC_HAS_PHYS_PORT_ID;
752
753 return 0;
754 }
755
qlcnic_82xx_set_rx_coalesce(struct qlcnic_adapter * adapter)756 int qlcnic_82xx_set_rx_coalesce(struct qlcnic_adapter *adapter)
757 {
758 struct qlcnic_nic_req req;
759 int rv;
760
761 memset(&req, 0, sizeof(struct qlcnic_nic_req));
762
763 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
764
765 req.req_hdr = cpu_to_le64(QLCNIC_CONFIG_INTR_COALESCE |
766 ((u64) adapter->portnum << 16));
767
768 req.words[0] = cpu_to_le64(((u64) adapter->ahw->coal.flag) << 32);
769 req.words[2] = cpu_to_le64(adapter->ahw->coal.rx_packets |
770 ((u64) adapter->ahw->coal.rx_time_us) << 16);
771 req.words[5] = cpu_to_le64(adapter->ahw->coal.timer_out |
772 ((u64) adapter->ahw->coal.type) << 32 |
773 ((u64) adapter->ahw->coal.sts_ring_mask) << 40);
774 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
775 if (rv != 0)
776 dev_err(&adapter->netdev->dev,
777 "Could not send interrupt coalescing parameters\n");
778
779 return rv;
780 }
781
782 /* Send the interrupt coalescing parameter set by ethtool to the card. */
qlcnic_82xx_config_intr_coalesce(struct qlcnic_adapter * adapter,struct ethtool_coalesce * ethcoal)783 int qlcnic_82xx_config_intr_coalesce(struct qlcnic_adapter *adapter,
784 struct ethtool_coalesce *ethcoal)
785 {
786 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
787 int rv;
788
789 coal->flag = QLCNIC_INTR_DEFAULT;
790 coal->rx_time_us = ethcoal->rx_coalesce_usecs;
791 coal->rx_packets = ethcoal->rx_max_coalesced_frames;
792
793 rv = qlcnic_82xx_set_rx_coalesce(adapter);
794
795 if (rv)
796 netdev_err(adapter->netdev,
797 "Failed to set Rx coalescing parametrs\n");
798
799 return rv;
800 }
801
802 #define QLCNIC_ENABLE_IPV4_LRO BIT_0
803 #define QLCNIC_ENABLE_IPV6_LRO (BIT_1 | BIT_9)
804
qlcnic_82xx_config_hw_lro(struct qlcnic_adapter * adapter,int enable)805 int qlcnic_82xx_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
806 {
807 struct qlcnic_nic_req req;
808 u64 word;
809 int rv;
810
811 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
812 return 0;
813
814 memset(&req, 0, sizeof(struct qlcnic_nic_req));
815
816 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
817
818 word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
819 req.req_hdr = cpu_to_le64(word);
820
821 word = 0;
822 if (enable) {
823 word = QLCNIC_ENABLE_IPV4_LRO;
824 if (adapter->ahw->extra_capability[0] &
825 QLCNIC_FW_CAP2_HW_LRO_IPV6)
826 word |= QLCNIC_ENABLE_IPV6_LRO;
827 }
828
829 req.words[0] = cpu_to_le64(word);
830
831 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
832 if (rv != 0)
833 dev_err(&adapter->netdev->dev,
834 "Could not send configure hw lro request\n");
835
836 return rv;
837 }
838
qlcnic_config_bridged_mode(struct qlcnic_adapter * adapter,u32 enable)839 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable)
840 {
841 struct qlcnic_nic_req req;
842 u64 word;
843 int rv;
844
845 if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
846 return 0;
847
848 memset(&req, 0, sizeof(struct qlcnic_nic_req));
849
850 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
851
852 word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
853 ((u64)adapter->portnum << 16);
854 req.req_hdr = cpu_to_le64(word);
855
856 req.words[0] = cpu_to_le64(enable);
857
858 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
859 if (rv != 0)
860 dev_err(&adapter->netdev->dev,
861 "Could not send configure bridge mode request\n");
862
863 adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
864
865 return rv;
866 }
867
868
869 #define QLCNIC_RSS_HASHTYPE_IP_TCP 0x3
870 #define QLCNIC_ENABLE_TYPE_C_RSS BIT_10
871 #define QLCNIC_RSS_FEATURE_FLAG (1ULL << 63)
872 #define QLCNIC_RSS_IND_TABLE_MASK 0x7ULL
873
qlcnic_82xx_config_rss(struct qlcnic_adapter * adapter,int enable)874 int qlcnic_82xx_config_rss(struct qlcnic_adapter *adapter, int enable)
875 {
876 struct qlcnic_nic_req req;
877 u64 word;
878 int i, rv;
879
880 static const u64 key[] = {
881 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
882 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
883 0x255b0ec26d5a56daULL
884 };
885
886 memset(&req, 0, sizeof(struct qlcnic_nic_req));
887 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
888
889 word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
890 req.req_hdr = cpu_to_le64(word);
891
892 /*
893 * RSS request:
894 * bits 3-0: hash_method
895 * 5-4: hash_type_ipv4
896 * 7-6: hash_type_ipv6
897 * 8: enable
898 * 9: use indirection table
899 * 10: type-c rss
900 * 11: udp rss
901 * 47-12: reserved
902 * 62-48: indirection table mask
903 * 63: feature flag
904 */
905 word = ((u64)(QLCNIC_RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
906 ((u64)(QLCNIC_RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
907 ((u64)(enable & 0x1) << 8) |
908 ((u64)QLCNIC_RSS_IND_TABLE_MASK << 48) |
909 (u64)QLCNIC_ENABLE_TYPE_C_RSS |
910 (u64)QLCNIC_RSS_FEATURE_FLAG;
911
912 req.words[0] = cpu_to_le64(word);
913 for (i = 0; i < 5; i++)
914 req.words[i+1] = cpu_to_le64(key[i]);
915
916 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
917 if (rv != 0)
918 dev_err(&adapter->netdev->dev, "could not configure RSS\n");
919
920 return rv;
921 }
922
qlcnic_82xx_config_ipaddr(struct qlcnic_adapter * adapter,__be32 ip,int cmd)923 void qlcnic_82xx_config_ipaddr(struct qlcnic_adapter *adapter,
924 __be32 ip, int cmd)
925 {
926 struct qlcnic_nic_req req;
927 struct qlcnic_ipaddr *ipa;
928 u64 word;
929 int rv;
930
931 memset(&req, 0, sizeof(struct qlcnic_nic_req));
932 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
933
934 word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
935 req.req_hdr = cpu_to_le64(word);
936
937 req.words[0] = cpu_to_le64(cmd);
938 ipa = (struct qlcnic_ipaddr *)&req.words[1];
939 ipa->ipv4 = ip;
940
941 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
942 if (rv != 0)
943 dev_err(&adapter->netdev->dev,
944 "could not notify %s IP 0x%x request\n",
945 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
946 }
947
qlcnic_82xx_linkevent_request(struct qlcnic_adapter * adapter,int enable)948 int qlcnic_82xx_linkevent_request(struct qlcnic_adapter *adapter, int enable)
949 {
950 struct qlcnic_nic_req req;
951 u64 word;
952 int rv;
953 memset(&req, 0, sizeof(struct qlcnic_nic_req));
954 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
955
956 word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
957 req.req_hdr = cpu_to_le64(word);
958 req.words[0] = cpu_to_le64(enable | (enable << 8));
959 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
960 if (rv != 0)
961 dev_err(&adapter->netdev->dev,
962 "could not configure link notification\n");
963
964 return rv;
965 }
966
qlcnic_send_lro_cleanup(struct qlcnic_adapter * adapter)967 static int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
968 {
969 struct qlcnic_nic_req req;
970 u64 word;
971 int rv;
972
973 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
974 return 0;
975
976 memset(&req, 0, sizeof(struct qlcnic_nic_req));
977 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
978
979 word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
980 ((u64)adapter->portnum << 16) |
981 ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
982
983 req.req_hdr = cpu_to_le64(word);
984
985 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
986 if (rv != 0)
987 dev_err(&adapter->netdev->dev,
988 "could not cleanup lro flows\n");
989
990 return rv;
991 }
992
993 /*
994 * qlcnic_change_mtu - Change the Maximum Transfer Unit
995 * @returns 0 on success, negative on failure
996 */
997
qlcnic_change_mtu(struct net_device * netdev,int mtu)998 int qlcnic_change_mtu(struct net_device *netdev, int mtu)
999 {
1000 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1001 int rc = 0;
1002
1003 if (mtu < P3P_MIN_MTU || mtu > P3P_MAX_MTU) {
1004 dev_err(&adapter->netdev->dev, "%d bytes < mtu < %d bytes"
1005 " not supported\n", P3P_MAX_MTU, P3P_MIN_MTU);
1006 return -EINVAL;
1007 }
1008
1009 rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
1010
1011 if (!rc)
1012 netdev->mtu = mtu;
1013
1014 return rc;
1015 }
1016
qlcnic_process_flags(struct qlcnic_adapter * adapter,netdev_features_t features)1017 static netdev_features_t qlcnic_process_flags(struct qlcnic_adapter *adapter,
1018 netdev_features_t features)
1019 {
1020 u32 offload_flags = adapter->offload_flags;
1021
1022 if (offload_flags & BIT_0) {
1023 features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM |
1024 NETIF_F_IPV6_CSUM;
1025 adapter->rx_csum = 1;
1026 if (QLCNIC_IS_TSO_CAPABLE(adapter)) {
1027 if (!(offload_flags & BIT_1))
1028 features &= ~NETIF_F_TSO;
1029 else
1030 features |= NETIF_F_TSO;
1031
1032 if (!(offload_flags & BIT_2))
1033 features &= ~NETIF_F_TSO6;
1034 else
1035 features |= NETIF_F_TSO6;
1036 }
1037 } else {
1038 features &= ~(NETIF_F_RXCSUM |
1039 NETIF_F_IP_CSUM |
1040 NETIF_F_IPV6_CSUM);
1041
1042 if (QLCNIC_IS_TSO_CAPABLE(adapter))
1043 features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
1044 adapter->rx_csum = 0;
1045 }
1046
1047 return features;
1048 }
1049
qlcnic_fix_features(struct net_device * netdev,netdev_features_t features)1050 netdev_features_t qlcnic_fix_features(struct net_device *netdev,
1051 netdev_features_t features)
1052 {
1053 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1054 netdev_features_t changed;
1055
1056 if (qlcnic_82xx_check(adapter) &&
1057 (adapter->flags & QLCNIC_ESWITCH_ENABLED)) {
1058 if (adapter->flags & QLCNIC_APP_CHANGED_FLAGS) {
1059 features = qlcnic_process_flags(adapter, features);
1060 } else {
1061 changed = features ^ netdev->features;
1062 features ^= changed & (NETIF_F_RXCSUM |
1063 NETIF_F_IP_CSUM |
1064 NETIF_F_IPV6_CSUM |
1065 NETIF_F_TSO |
1066 NETIF_F_TSO6);
1067 }
1068 }
1069
1070 if (!(features & NETIF_F_RXCSUM))
1071 features &= ~NETIF_F_LRO;
1072
1073 return features;
1074 }
1075
1076
qlcnic_set_features(struct net_device * netdev,netdev_features_t features)1077 int qlcnic_set_features(struct net_device *netdev, netdev_features_t features)
1078 {
1079 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1080 netdev_features_t changed = netdev->features ^ features;
1081 int hw_lro = (features & NETIF_F_LRO) ? QLCNIC_LRO_ENABLED : 0;
1082
1083 if (!(changed & NETIF_F_LRO))
1084 return 0;
1085
1086 netdev->features ^= NETIF_F_LRO;
1087
1088 if (qlcnic_config_hw_lro(adapter, hw_lro))
1089 return -EIO;
1090
1091 if (!hw_lro && qlcnic_82xx_check(adapter)) {
1092 if (qlcnic_send_lro_cleanup(adapter))
1093 return -EIO;
1094 }
1095
1096 return 0;
1097 }
1098
1099 /*
1100 * Changes the CRB window to the specified window.
1101 */
1102 /* Returns < 0 if off is not valid,
1103 * 1 if window access is needed. 'off' is set to offset from
1104 * CRB space in 128M pci map
1105 * 0 if no window access is needed. 'off' is set to 2M addr
1106 * In: 'off' is offset from base in 128M pci map
1107 */
qlcnic_pci_get_crb_addr_2M(struct qlcnic_hardware_context * ahw,ulong off,void __iomem ** addr)1108 static int qlcnic_pci_get_crb_addr_2M(struct qlcnic_hardware_context *ahw,
1109 ulong off, void __iomem **addr)
1110 {
1111 const struct crb_128M_2M_sub_block_map *m;
1112
1113 if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
1114 return -EINVAL;
1115
1116 off -= QLCNIC_PCI_CRBSPACE;
1117
1118 /*
1119 * Try direct map
1120 */
1121 m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
1122
1123 if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
1124 *addr = ahw->pci_base0 + m->start_2M +
1125 (off - m->start_128M);
1126 return 0;
1127 }
1128
1129 /*
1130 * Not in direct map, use crb window
1131 */
1132 *addr = ahw->pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
1133 return 1;
1134 }
1135
1136 /*
1137 * In: 'off' is offset from CRB space in 128M pci map
1138 * Out: 'off' is 2M pci map addr
1139 * side effect: lock crb window
1140 */
1141 static int
qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter * adapter,ulong off)1142 qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
1143 {
1144 u32 window;
1145 void __iomem *addr = adapter->ahw->pci_base0 + CRB_WINDOW_2M;
1146
1147 off -= QLCNIC_PCI_CRBSPACE;
1148
1149 window = CRB_HI(off);
1150 if (window == 0) {
1151 dev_err(&adapter->pdev->dev, "Invalid offset 0x%lx\n", off);
1152 return -EIO;
1153 }
1154
1155 writel(window, addr);
1156 if (readl(addr) != window) {
1157 if (printk_ratelimit())
1158 dev_warn(&adapter->pdev->dev,
1159 "failed to set CRB window to %d off 0x%lx\n",
1160 window, off);
1161 return -EIO;
1162 }
1163 return 0;
1164 }
1165
qlcnic_82xx_hw_write_wx_2M(struct qlcnic_adapter * adapter,ulong off,u32 data)1166 int qlcnic_82xx_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off,
1167 u32 data)
1168 {
1169 unsigned long flags;
1170 int rv;
1171 void __iomem *addr = NULL;
1172
1173 rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr);
1174
1175 if (rv == 0) {
1176 writel(data, addr);
1177 return 0;
1178 }
1179
1180 if (rv > 0) {
1181 /* indirect access */
1182 write_lock_irqsave(&adapter->ahw->crb_lock, flags);
1183 crb_win_lock(adapter);
1184 rv = qlcnic_pci_set_crbwindow_2M(adapter, off);
1185 if (!rv)
1186 writel(data, addr);
1187 crb_win_unlock(adapter);
1188 write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
1189 return rv;
1190 }
1191
1192 dev_err(&adapter->pdev->dev,
1193 "%s: invalid offset: 0x%016lx\n", __func__, off);
1194 dump_stack();
1195 return -EIO;
1196 }
1197
qlcnic_82xx_hw_read_wx_2M(struct qlcnic_adapter * adapter,ulong off,int * err)1198 int qlcnic_82xx_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off,
1199 int *err)
1200 {
1201 unsigned long flags;
1202 int rv;
1203 u32 data = -1;
1204 void __iomem *addr = NULL;
1205
1206 rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr);
1207
1208 if (rv == 0)
1209 return readl(addr);
1210
1211 if (rv > 0) {
1212 /* indirect access */
1213 write_lock_irqsave(&adapter->ahw->crb_lock, flags);
1214 crb_win_lock(adapter);
1215 if (!qlcnic_pci_set_crbwindow_2M(adapter, off))
1216 data = readl(addr);
1217 crb_win_unlock(adapter);
1218 write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
1219 return data;
1220 }
1221
1222 dev_err(&adapter->pdev->dev,
1223 "%s: invalid offset: 0x%016lx\n", __func__, off);
1224 dump_stack();
1225 return -1;
1226 }
1227
qlcnic_get_ioaddr(struct qlcnic_hardware_context * ahw,u32 offset)1228 void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *ahw,
1229 u32 offset)
1230 {
1231 void __iomem *addr = NULL;
1232
1233 WARN_ON(qlcnic_pci_get_crb_addr_2M(ahw, offset, &addr));
1234
1235 return addr;
1236 }
1237
qlcnic_pci_mem_access_direct(struct qlcnic_adapter * adapter,u32 window,u64 off,u64 * data,int op)1238 static int qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter,
1239 u32 window, u64 off, u64 *data, int op)
1240 {
1241 void __iomem *addr;
1242 u32 start;
1243
1244 mutex_lock(&adapter->ahw->mem_lock);
1245
1246 writel(window, adapter->ahw->ocm_win_crb);
1247 /* read back to flush */
1248 readl(adapter->ahw->ocm_win_crb);
1249 start = QLCNIC_PCI_OCM0_2M + off;
1250
1251 addr = adapter->ahw->pci_base0 + start;
1252
1253 if (op == 0) /* read */
1254 *data = readq(addr);
1255 else /* write */
1256 writeq(*data, addr);
1257
1258 /* Set window to 0 */
1259 writel(0, adapter->ahw->ocm_win_crb);
1260 readl(adapter->ahw->ocm_win_crb);
1261
1262 mutex_unlock(&adapter->ahw->mem_lock);
1263 return 0;
1264 }
1265
1266 static void
qlcnic_pci_camqm_read_2M(struct qlcnic_adapter * adapter,u64 off,u64 * data)1267 qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
1268 {
1269 void __iomem *addr = adapter->ahw->pci_base0 +
1270 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
1271
1272 mutex_lock(&adapter->ahw->mem_lock);
1273 *data = readq(addr);
1274 mutex_unlock(&adapter->ahw->mem_lock);
1275 }
1276
1277 static void
qlcnic_pci_camqm_write_2M(struct qlcnic_adapter * adapter,u64 off,u64 data)1278 qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
1279 {
1280 void __iomem *addr = adapter->ahw->pci_base0 +
1281 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
1282
1283 mutex_lock(&adapter->ahw->mem_lock);
1284 writeq(data, addr);
1285 mutex_unlock(&adapter->ahw->mem_lock);
1286 }
1287
1288
1289
1290 /* Set MS memory control data for different adapters */
qlcnic_set_ms_controls(struct qlcnic_adapter * adapter,u64 off,struct qlcnic_ms_reg_ctrl * ms)1291 static void qlcnic_set_ms_controls(struct qlcnic_adapter *adapter, u64 off,
1292 struct qlcnic_ms_reg_ctrl *ms)
1293 {
1294 ms->control = QLCNIC_MS_CTRL;
1295 ms->low = QLCNIC_MS_ADDR_LO;
1296 ms->hi = QLCNIC_MS_ADDR_HI;
1297 if (off & 0xf) {
1298 ms->wd[0] = QLCNIC_MS_WRTDATA_LO;
1299 ms->rd[0] = QLCNIC_MS_RDDATA_LO;
1300 ms->wd[1] = QLCNIC_MS_WRTDATA_HI;
1301 ms->rd[1] = QLCNIC_MS_RDDATA_HI;
1302 ms->wd[2] = QLCNIC_MS_WRTDATA_ULO;
1303 ms->wd[3] = QLCNIC_MS_WRTDATA_UHI;
1304 ms->rd[2] = QLCNIC_MS_RDDATA_ULO;
1305 ms->rd[3] = QLCNIC_MS_RDDATA_UHI;
1306 } else {
1307 ms->wd[0] = QLCNIC_MS_WRTDATA_ULO;
1308 ms->rd[0] = QLCNIC_MS_RDDATA_ULO;
1309 ms->wd[1] = QLCNIC_MS_WRTDATA_UHI;
1310 ms->rd[1] = QLCNIC_MS_RDDATA_UHI;
1311 ms->wd[2] = QLCNIC_MS_WRTDATA_LO;
1312 ms->wd[3] = QLCNIC_MS_WRTDATA_HI;
1313 ms->rd[2] = QLCNIC_MS_RDDATA_LO;
1314 ms->rd[3] = QLCNIC_MS_RDDATA_HI;
1315 }
1316
1317 ms->ocm_window = OCM_WIN_P3P(off);
1318 ms->off = GET_MEM_OFFS_2M(off);
1319 }
1320
qlcnic_pci_mem_write_2M(struct qlcnic_adapter * adapter,u64 off,u64 data)1321 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
1322 {
1323 int j, ret = 0;
1324 u32 temp, off8;
1325 struct qlcnic_ms_reg_ctrl ms;
1326
1327 /* Only 64-bit aligned access */
1328 if (off & 7)
1329 return -EIO;
1330
1331 memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl));
1332 if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1333 QLCNIC_ADDR_QDR_NET_MAX) ||
1334 ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET,
1335 QLCNIC_ADDR_DDR_NET_MAX)))
1336 return -EIO;
1337
1338 qlcnic_set_ms_controls(adapter, off, &ms);
1339
1340 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
1341 return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window,
1342 ms.off, &data, 1);
1343
1344 off8 = off & ~0xf;
1345
1346 mutex_lock(&adapter->ahw->mem_lock);
1347
1348 qlcnic_ind_wr(adapter, ms.low, off8);
1349 qlcnic_ind_wr(adapter, ms.hi, 0);
1350
1351 qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE);
1352 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE);
1353
1354 for (j = 0; j < MAX_CTL_CHECK; j++) {
1355 temp = qlcnic_ind_rd(adapter, ms.control);
1356 if ((temp & TA_CTL_BUSY) == 0)
1357 break;
1358 }
1359
1360 if (j >= MAX_CTL_CHECK) {
1361 ret = -EIO;
1362 goto done;
1363 }
1364
1365 /* This is the modify part of read-modify-write */
1366 qlcnic_ind_wr(adapter, ms.wd[0], qlcnic_ind_rd(adapter, ms.rd[0]));
1367 qlcnic_ind_wr(adapter, ms.wd[1], qlcnic_ind_rd(adapter, ms.rd[1]));
1368 /* This is the write part of read-modify-write */
1369 qlcnic_ind_wr(adapter, ms.wd[2], data & 0xffffffff);
1370 qlcnic_ind_wr(adapter, ms.wd[3], (data >> 32) & 0xffffffff);
1371
1372 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_ENABLE);
1373 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_START);
1374
1375 for (j = 0; j < MAX_CTL_CHECK; j++) {
1376 temp = qlcnic_ind_rd(adapter, ms.control);
1377 if ((temp & TA_CTL_BUSY) == 0)
1378 break;
1379 }
1380
1381 if (j >= MAX_CTL_CHECK) {
1382 if (printk_ratelimit())
1383 dev_err(&adapter->pdev->dev,
1384 "failed to write through agent\n");
1385 ret = -EIO;
1386 } else
1387 ret = 0;
1388
1389 done:
1390 mutex_unlock(&adapter->ahw->mem_lock);
1391
1392 return ret;
1393 }
1394
qlcnic_pci_mem_read_2M(struct qlcnic_adapter * adapter,u64 off,u64 * data)1395 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
1396 {
1397 int j, ret;
1398 u32 temp, off8;
1399 u64 val;
1400 struct qlcnic_ms_reg_ctrl ms;
1401
1402 /* Only 64-bit aligned access */
1403 if (off & 7)
1404 return -EIO;
1405 if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1406 QLCNIC_ADDR_QDR_NET_MAX) ||
1407 ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET,
1408 QLCNIC_ADDR_DDR_NET_MAX)))
1409 return -EIO;
1410
1411 memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl));
1412 qlcnic_set_ms_controls(adapter, off, &ms);
1413
1414 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
1415 return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window,
1416 ms.off, data, 0);
1417
1418 mutex_lock(&adapter->ahw->mem_lock);
1419
1420 off8 = off & ~0xf;
1421
1422 qlcnic_ind_wr(adapter, ms.low, off8);
1423 qlcnic_ind_wr(adapter, ms.hi, 0);
1424
1425 qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE);
1426 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE);
1427
1428 for (j = 0; j < MAX_CTL_CHECK; j++) {
1429 temp = qlcnic_ind_rd(adapter, ms.control);
1430 if ((temp & TA_CTL_BUSY) == 0)
1431 break;
1432 }
1433
1434 if (j >= MAX_CTL_CHECK) {
1435 if (printk_ratelimit())
1436 dev_err(&adapter->pdev->dev,
1437 "failed to read through agent\n");
1438 ret = -EIO;
1439 } else {
1440
1441 temp = qlcnic_ind_rd(adapter, ms.rd[3]);
1442 val = (u64)temp << 32;
1443 val |= qlcnic_ind_rd(adapter, ms.rd[2]);
1444 *data = val;
1445 ret = 0;
1446 }
1447
1448 mutex_unlock(&adapter->ahw->mem_lock);
1449
1450 return ret;
1451 }
1452
qlcnic_82xx_get_board_info(struct qlcnic_adapter * adapter)1453 int qlcnic_82xx_get_board_info(struct qlcnic_adapter *adapter)
1454 {
1455 int offset, board_type, magic, err = 0;
1456 struct pci_dev *pdev = adapter->pdev;
1457
1458 offset = QLCNIC_FW_MAGIC_OFFSET;
1459 if (qlcnic_rom_fast_read(adapter, offset, &magic))
1460 return -EIO;
1461
1462 if (magic != QLCNIC_BDINFO_MAGIC) {
1463 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1464 magic);
1465 return -EIO;
1466 }
1467
1468 offset = QLCNIC_BRDTYPE_OFFSET;
1469 if (qlcnic_rom_fast_read(adapter, offset, &board_type))
1470 return -EIO;
1471
1472 adapter->ahw->board_type = board_type;
1473
1474 if (board_type == QLCNIC_BRDTYPE_P3P_4_GB_MM) {
1475 u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I, &err);
1476 if (err == -EIO)
1477 return err;
1478 if ((gpio & 0x8000) == 0)
1479 board_type = QLCNIC_BRDTYPE_P3P_10G_TP;
1480 }
1481
1482 switch (board_type) {
1483 case QLCNIC_BRDTYPE_P3P_HMEZ:
1484 case QLCNIC_BRDTYPE_P3P_XG_LOM:
1485 case QLCNIC_BRDTYPE_P3P_10G_CX4:
1486 case QLCNIC_BRDTYPE_P3P_10G_CX4_LP:
1487 case QLCNIC_BRDTYPE_P3P_IMEZ:
1488 case QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS:
1489 case QLCNIC_BRDTYPE_P3P_10G_SFP_CT:
1490 case QLCNIC_BRDTYPE_P3P_10G_SFP_QT:
1491 case QLCNIC_BRDTYPE_P3P_10G_XFP:
1492 case QLCNIC_BRDTYPE_P3P_10000_BASE_T:
1493 adapter->ahw->port_type = QLCNIC_XGBE;
1494 break;
1495 case QLCNIC_BRDTYPE_P3P_REF_QG:
1496 case QLCNIC_BRDTYPE_P3P_4_GB:
1497 case QLCNIC_BRDTYPE_P3P_4_GB_MM:
1498 adapter->ahw->port_type = QLCNIC_GBE;
1499 break;
1500 case QLCNIC_BRDTYPE_P3P_10G_TP:
1501 adapter->ahw->port_type = (adapter->portnum < 2) ?
1502 QLCNIC_XGBE : QLCNIC_GBE;
1503 break;
1504 default:
1505 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1506 adapter->ahw->port_type = QLCNIC_XGBE;
1507 break;
1508 }
1509
1510 return 0;
1511 }
1512
1513 static int
qlcnic_wol_supported(struct qlcnic_adapter * adapter)1514 qlcnic_wol_supported(struct qlcnic_adapter *adapter)
1515 {
1516 u32 wol_cfg;
1517 int err = 0;
1518
1519 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV, &err);
1520 if (wol_cfg & (1UL << adapter->portnum)) {
1521 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG, &err);
1522 if (err == -EIO)
1523 return err;
1524 if (wol_cfg & (1 << adapter->portnum))
1525 return 1;
1526 }
1527
1528 return 0;
1529 }
1530
qlcnic_82xx_config_led(struct qlcnic_adapter * adapter,u32 state,u32 rate)1531 int qlcnic_82xx_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
1532 {
1533 struct qlcnic_nic_req req;
1534 int rv;
1535 u64 word;
1536
1537 memset(&req, 0, sizeof(struct qlcnic_nic_req));
1538 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1539
1540 word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
1541 req.req_hdr = cpu_to_le64(word);
1542
1543 req.words[0] = cpu_to_le64(((u64)rate << 32) | adapter->portnum);
1544 req.words[1] = cpu_to_le64(state);
1545
1546 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1547 if (rv)
1548 dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
1549
1550 return rv;
1551 }
1552
qlcnic_82xx_get_beacon_state(struct qlcnic_adapter * adapter)1553 void qlcnic_82xx_get_beacon_state(struct qlcnic_adapter *adapter)
1554 {
1555 struct qlcnic_hardware_context *ahw = adapter->ahw;
1556 struct qlcnic_cmd_args cmd;
1557 u8 beacon_state;
1558 int err = 0;
1559
1560 if (ahw->extra_capability[0] & QLCNIC_FW_CAPABILITY_2_BEACON) {
1561 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1562 QLCNIC_CMD_GET_LED_STATUS);
1563 if (!err) {
1564 err = qlcnic_issue_cmd(adapter, &cmd);
1565 if (err) {
1566 netdev_err(adapter->netdev,
1567 "Failed to get current beacon state, err=%d\n",
1568 err);
1569 } else {
1570 beacon_state = cmd.rsp.arg[1];
1571 if (beacon_state == QLCNIC_BEACON_DISABLE)
1572 ahw->beacon_state = QLCNIC_BEACON_OFF;
1573 else if (beacon_state == QLCNIC_BEACON_EANBLE)
1574 ahw->beacon_state = QLCNIC_BEACON_ON;
1575 }
1576 }
1577 qlcnic_free_mbx_args(&cmd);
1578 }
1579
1580 return;
1581 }
1582
qlcnic_82xx_get_func_no(struct qlcnic_adapter * adapter)1583 void qlcnic_82xx_get_func_no(struct qlcnic_adapter *adapter)
1584 {
1585 void __iomem *msix_base_addr;
1586 u32 func;
1587 u32 msix_base;
1588
1589 pci_read_config_dword(adapter->pdev, QLCNIC_MSIX_TABLE_OFFSET, &func);
1590 msix_base_addr = adapter->ahw->pci_base0 + QLCNIC_MSIX_BASE;
1591 msix_base = readl(msix_base_addr);
1592 func = (func - msix_base) / QLCNIC_MSIX_TBL_PGSIZE;
1593 adapter->ahw->pci_func = func;
1594 }
1595
qlcnic_82xx_read_crb(struct qlcnic_adapter * adapter,char * buf,loff_t offset,size_t size)1596 void qlcnic_82xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
1597 loff_t offset, size_t size)
1598 {
1599 int err = 0;
1600 u32 data;
1601 u64 qmdata;
1602
1603 if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM, QLCNIC_PCI_CAMQM_END)) {
1604 qlcnic_pci_camqm_read_2M(adapter, offset, &qmdata);
1605 memcpy(buf, &qmdata, size);
1606 } else {
1607 data = QLCRD32(adapter, offset, &err);
1608 memcpy(buf, &data, size);
1609 }
1610 }
1611
qlcnic_82xx_write_crb(struct qlcnic_adapter * adapter,char * buf,loff_t offset,size_t size)1612 void qlcnic_82xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
1613 loff_t offset, size_t size)
1614 {
1615 u32 data;
1616 u64 qmdata;
1617
1618 if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM, QLCNIC_PCI_CAMQM_END)) {
1619 memcpy(&qmdata, buf, size);
1620 qlcnic_pci_camqm_write_2M(adapter, offset, qmdata);
1621 } else {
1622 memcpy(&data, buf, size);
1623 QLCWR32(adapter, offset, data);
1624 }
1625 }
1626
qlcnic_82xx_api_lock(struct qlcnic_adapter * adapter)1627 int qlcnic_82xx_api_lock(struct qlcnic_adapter *adapter)
1628 {
1629 return qlcnic_pcie_sem_lock(adapter, 5, 0);
1630 }
1631
qlcnic_82xx_api_unlock(struct qlcnic_adapter * adapter)1632 void qlcnic_82xx_api_unlock(struct qlcnic_adapter *adapter)
1633 {
1634 qlcnic_pcie_sem_unlock(adapter, 5);
1635 }
1636
qlcnic_82xx_shutdown(struct pci_dev * pdev)1637 int qlcnic_82xx_shutdown(struct pci_dev *pdev)
1638 {
1639 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
1640 struct net_device *netdev = adapter->netdev;
1641 int retval;
1642
1643 netif_device_detach(netdev);
1644
1645 qlcnic_cancel_idc_work(adapter);
1646
1647 if (netif_running(netdev))
1648 qlcnic_down(adapter, netdev);
1649
1650 qlcnic_clr_all_drv_state(adapter, 0);
1651
1652 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1653
1654 retval = pci_save_state(pdev);
1655 if (retval)
1656 return retval;
1657
1658 if (qlcnic_wol_supported(adapter)) {
1659 pci_enable_wake(pdev, PCI_D3cold, 1);
1660 pci_enable_wake(pdev, PCI_D3hot, 1);
1661 }
1662
1663 return 0;
1664 }
1665
qlcnic_82xx_resume(struct qlcnic_adapter * adapter)1666 int qlcnic_82xx_resume(struct qlcnic_adapter *adapter)
1667 {
1668 struct net_device *netdev = adapter->netdev;
1669 int err;
1670
1671 err = qlcnic_start_firmware(adapter);
1672 if (err) {
1673 dev_err(&adapter->pdev->dev, "failed to start firmware\n");
1674 return err;
1675 }
1676
1677 if (netif_running(netdev)) {
1678 err = qlcnic_up(adapter, netdev);
1679 if (!err)
1680 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
1681 }
1682
1683 netif_device_attach(netdev);
1684 qlcnic_schedule_work(adapter, qlcnic_fw_poll_work, FW_POLL_DELAY);
1685 return err;
1686 }
1687