1 /* SuperH Ethernet device driver
2 *
3 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
4 * Copyright (C) 2008-2014 Renesas Solutions Corp.
5 * Copyright (C) 2013-2014 Cogent Embedded, Inc.
6 * Copyright (C) 2014 Codethink Limited
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * The full GNU General Public License is included in this distribution in
18 * the file called "COPYING".
19 */
20
21 #include <linux/module.h>
22 #include <linux/kernel.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/etherdevice.h>
27 #include <linux/delay.h>
28 #include <linux/platform_device.h>
29 #include <linux/mdio-bitbang.h>
30 #include <linux/netdevice.h>
31 #include <linux/of.h>
32 #include <linux/of_device.h>
33 #include <linux/of_irq.h>
34 #include <linux/of_net.h>
35 #include <linux/phy.h>
36 #include <linux/cache.h>
37 #include <linux/io.h>
38 #include <linux/pm_runtime.h>
39 #include <linux/slab.h>
40 #include <linux/ethtool.h>
41 #include <linux/if_vlan.h>
42 #include <linux/clk.h>
43 #include <linux/sh_eth.h>
44 #include <linux/of_mdio.h>
45
46 #include "sh_eth.h"
47
48 #define SH_ETH_DEF_MSG_ENABLE \
49 (NETIF_MSG_LINK | \
50 NETIF_MSG_TIMER | \
51 NETIF_MSG_RX_ERR| \
52 NETIF_MSG_TX_ERR)
53
54 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
55 [EDSR] = 0x0000,
56 [EDMR] = 0x0400,
57 [EDTRR] = 0x0408,
58 [EDRRR] = 0x0410,
59 [EESR] = 0x0428,
60 [EESIPR] = 0x0430,
61 [TDLAR] = 0x0010,
62 [TDFAR] = 0x0014,
63 [TDFXR] = 0x0018,
64 [TDFFR] = 0x001c,
65 [RDLAR] = 0x0030,
66 [RDFAR] = 0x0034,
67 [RDFXR] = 0x0038,
68 [RDFFR] = 0x003c,
69 [TRSCER] = 0x0438,
70 [RMFCR] = 0x0440,
71 [TFTR] = 0x0448,
72 [FDR] = 0x0450,
73 [RMCR] = 0x0458,
74 [RPADIR] = 0x0460,
75 [FCFTR] = 0x0468,
76 [CSMR] = 0x04E4,
77
78 [ECMR] = 0x0500,
79 [ECSR] = 0x0510,
80 [ECSIPR] = 0x0518,
81 [PIR] = 0x0520,
82 [PSR] = 0x0528,
83 [PIPR] = 0x052c,
84 [RFLR] = 0x0508,
85 [APR] = 0x0554,
86 [MPR] = 0x0558,
87 [PFTCR] = 0x055c,
88 [PFRCR] = 0x0560,
89 [TPAUSER] = 0x0564,
90 [GECMR] = 0x05b0,
91 [BCULR] = 0x05b4,
92 [MAHR] = 0x05c0,
93 [MALR] = 0x05c8,
94 [TROCR] = 0x0700,
95 [CDCR] = 0x0708,
96 [LCCR] = 0x0710,
97 [CEFCR] = 0x0740,
98 [FRECR] = 0x0748,
99 [TSFRCR] = 0x0750,
100 [TLFRCR] = 0x0758,
101 [RFCR] = 0x0760,
102 [CERCR] = 0x0768,
103 [CEECR] = 0x0770,
104 [MAFCR] = 0x0778,
105 [RMII_MII] = 0x0790,
106
107 [ARSTR] = 0x0000,
108 [TSU_CTRST] = 0x0004,
109 [TSU_FWEN0] = 0x0010,
110 [TSU_FWEN1] = 0x0014,
111 [TSU_FCM] = 0x0018,
112 [TSU_BSYSL0] = 0x0020,
113 [TSU_BSYSL1] = 0x0024,
114 [TSU_PRISL0] = 0x0028,
115 [TSU_PRISL1] = 0x002c,
116 [TSU_FWSL0] = 0x0030,
117 [TSU_FWSL1] = 0x0034,
118 [TSU_FWSLC] = 0x0038,
119 [TSU_QTAG0] = 0x0040,
120 [TSU_QTAG1] = 0x0044,
121 [TSU_FWSR] = 0x0050,
122 [TSU_FWINMK] = 0x0054,
123 [TSU_ADQT0] = 0x0048,
124 [TSU_ADQT1] = 0x004c,
125 [TSU_VTAG0] = 0x0058,
126 [TSU_VTAG1] = 0x005c,
127 [TSU_ADSBSY] = 0x0060,
128 [TSU_TEN] = 0x0064,
129 [TSU_POST1] = 0x0070,
130 [TSU_POST2] = 0x0074,
131 [TSU_POST3] = 0x0078,
132 [TSU_POST4] = 0x007c,
133 [TSU_ADRH0] = 0x0100,
134 [TSU_ADRL0] = 0x0104,
135 [TSU_ADRH31] = 0x01f8,
136 [TSU_ADRL31] = 0x01fc,
137
138 [TXNLCR0] = 0x0080,
139 [TXALCR0] = 0x0084,
140 [RXNLCR0] = 0x0088,
141 [RXALCR0] = 0x008c,
142 [FWNLCR0] = 0x0090,
143 [FWALCR0] = 0x0094,
144 [TXNLCR1] = 0x00a0,
145 [TXALCR1] = 0x00a0,
146 [RXNLCR1] = 0x00a8,
147 [RXALCR1] = 0x00ac,
148 [FWNLCR1] = 0x00b0,
149 [FWALCR1] = 0x00b4,
150 };
151
152 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
153 [EDSR] = 0x0000,
154 [EDMR] = 0x0400,
155 [EDTRR] = 0x0408,
156 [EDRRR] = 0x0410,
157 [EESR] = 0x0428,
158 [EESIPR] = 0x0430,
159 [TDLAR] = 0x0010,
160 [TDFAR] = 0x0014,
161 [TDFXR] = 0x0018,
162 [TDFFR] = 0x001c,
163 [RDLAR] = 0x0030,
164 [RDFAR] = 0x0034,
165 [RDFXR] = 0x0038,
166 [RDFFR] = 0x003c,
167 [TRSCER] = 0x0438,
168 [RMFCR] = 0x0440,
169 [TFTR] = 0x0448,
170 [FDR] = 0x0450,
171 [RMCR] = 0x0458,
172 [RPADIR] = 0x0460,
173 [FCFTR] = 0x0468,
174 [CSMR] = 0x04E4,
175
176 [ECMR] = 0x0500,
177 [RFLR] = 0x0508,
178 [ECSR] = 0x0510,
179 [ECSIPR] = 0x0518,
180 [PIR] = 0x0520,
181 [APR] = 0x0554,
182 [MPR] = 0x0558,
183 [PFTCR] = 0x055c,
184 [PFRCR] = 0x0560,
185 [TPAUSER] = 0x0564,
186 [MAHR] = 0x05c0,
187 [MALR] = 0x05c8,
188 [CEFCR] = 0x0740,
189 [FRECR] = 0x0748,
190 [TSFRCR] = 0x0750,
191 [TLFRCR] = 0x0758,
192 [RFCR] = 0x0760,
193 [MAFCR] = 0x0778,
194
195 [ARSTR] = 0x0000,
196 [TSU_CTRST] = 0x0004,
197 [TSU_VTAG0] = 0x0058,
198 [TSU_ADSBSY] = 0x0060,
199 [TSU_TEN] = 0x0064,
200 [TSU_ADRH0] = 0x0100,
201 [TSU_ADRL0] = 0x0104,
202 [TSU_ADRH31] = 0x01f8,
203 [TSU_ADRL31] = 0x01fc,
204
205 [TXNLCR0] = 0x0080,
206 [TXALCR0] = 0x0084,
207 [RXNLCR0] = 0x0088,
208 [RXALCR0] = 0x008C,
209 };
210
211 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
212 [ECMR] = 0x0300,
213 [RFLR] = 0x0308,
214 [ECSR] = 0x0310,
215 [ECSIPR] = 0x0318,
216 [PIR] = 0x0320,
217 [PSR] = 0x0328,
218 [RDMLR] = 0x0340,
219 [IPGR] = 0x0350,
220 [APR] = 0x0354,
221 [MPR] = 0x0358,
222 [RFCF] = 0x0360,
223 [TPAUSER] = 0x0364,
224 [TPAUSECR] = 0x0368,
225 [MAHR] = 0x03c0,
226 [MALR] = 0x03c8,
227 [TROCR] = 0x03d0,
228 [CDCR] = 0x03d4,
229 [LCCR] = 0x03d8,
230 [CNDCR] = 0x03dc,
231 [CEFCR] = 0x03e4,
232 [FRECR] = 0x03e8,
233 [TSFRCR] = 0x03ec,
234 [TLFRCR] = 0x03f0,
235 [RFCR] = 0x03f4,
236 [MAFCR] = 0x03f8,
237
238 [EDMR] = 0x0200,
239 [EDTRR] = 0x0208,
240 [EDRRR] = 0x0210,
241 [TDLAR] = 0x0218,
242 [RDLAR] = 0x0220,
243 [EESR] = 0x0228,
244 [EESIPR] = 0x0230,
245 [TRSCER] = 0x0238,
246 [RMFCR] = 0x0240,
247 [TFTR] = 0x0248,
248 [FDR] = 0x0250,
249 [RMCR] = 0x0258,
250 [TFUCR] = 0x0264,
251 [RFOCR] = 0x0268,
252 [RMIIMODE] = 0x026c,
253 [FCFTR] = 0x0270,
254 [TRIMD] = 0x027c,
255 };
256
257 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
258 [ECMR] = 0x0100,
259 [RFLR] = 0x0108,
260 [ECSR] = 0x0110,
261 [ECSIPR] = 0x0118,
262 [PIR] = 0x0120,
263 [PSR] = 0x0128,
264 [RDMLR] = 0x0140,
265 [IPGR] = 0x0150,
266 [APR] = 0x0154,
267 [MPR] = 0x0158,
268 [TPAUSER] = 0x0164,
269 [RFCF] = 0x0160,
270 [TPAUSECR] = 0x0168,
271 [BCFRR] = 0x016c,
272 [MAHR] = 0x01c0,
273 [MALR] = 0x01c8,
274 [TROCR] = 0x01d0,
275 [CDCR] = 0x01d4,
276 [LCCR] = 0x01d8,
277 [CNDCR] = 0x01dc,
278 [CEFCR] = 0x01e4,
279 [FRECR] = 0x01e8,
280 [TSFRCR] = 0x01ec,
281 [TLFRCR] = 0x01f0,
282 [RFCR] = 0x01f4,
283 [MAFCR] = 0x01f8,
284 [RTRATE] = 0x01fc,
285
286 [EDMR] = 0x0000,
287 [EDTRR] = 0x0008,
288 [EDRRR] = 0x0010,
289 [TDLAR] = 0x0018,
290 [RDLAR] = 0x0020,
291 [EESR] = 0x0028,
292 [EESIPR] = 0x0030,
293 [TRSCER] = 0x0038,
294 [RMFCR] = 0x0040,
295 [TFTR] = 0x0048,
296 [FDR] = 0x0050,
297 [RMCR] = 0x0058,
298 [TFUCR] = 0x0064,
299 [RFOCR] = 0x0068,
300 [FCFTR] = 0x0070,
301 [RPADIR] = 0x0078,
302 [TRIMD] = 0x007c,
303 [RBWAR] = 0x00c8,
304 [RDFAR] = 0x00cc,
305 [TBRAR] = 0x00d4,
306 [TDFAR] = 0x00d8,
307 };
308
309 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
310 [EDMR] = 0x0000,
311 [EDTRR] = 0x0004,
312 [EDRRR] = 0x0008,
313 [TDLAR] = 0x000c,
314 [RDLAR] = 0x0010,
315 [EESR] = 0x0014,
316 [EESIPR] = 0x0018,
317 [TRSCER] = 0x001c,
318 [RMFCR] = 0x0020,
319 [TFTR] = 0x0024,
320 [FDR] = 0x0028,
321 [RMCR] = 0x002c,
322 [EDOCR] = 0x0030,
323 [FCFTR] = 0x0034,
324 [RPADIR] = 0x0038,
325 [TRIMD] = 0x003c,
326 [RBWAR] = 0x0040,
327 [RDFAR] = 0x0044,
328 [TBRAR] = 0x004c,
329 [TDFAR] = 0x0050,
330
331 [ECMR] = 0x0160,
332 [ECSR] = 0x0164,
333 [ECSIPR] = 0x0168,
334 [PIR] = 0x016c,
335 [MAHR] = 0x0170,
336 [MALR] = 0x0174,
337 [RFLR] = 0x0178,
338 [PSR] = 0x017c,
339 [TROCR] = 0x0180,
340 [CDCR] = 0x0184,
341 [LCCR] = 0x0188,
342 [CNDCR] = 0x018c,
343 [CEFCR] = 0x0194,
344 [FRECR] = 0x0198,
345 [TSFRCR] = 0x019c,
346 [TLFRCR] = 0x01a0,
347 [RFCR] = 0x01a4,
348 [MAFCR] = 0x01a8,
349 [IPGR] = 0x01b4,
350 [APR] = 0x01b8,
351 [MPR] = 0x01bc,
352 [TPAUSER] = 0x01c4,
353 [BCFR] = 0x01cc,
354
355 [ARSTR] = 0x0000,
356 [TSU_CTRST] = 0x0004,
357 [TSU_FWEN0] = 0x0010,
358 [TSU_FWEN1] = 0x0014,
359 [TSU_FCM] = 0x0018,
360 [TSU_BSYSL0] = 0x0020,
361 [TSU_BSYSL1] = 0x0024,
362 [TSU_PRISL0] = 0x0028,
363 [TSU_PRISL1] = 0x002c,
364 [TSU_FWSL0] = 0x0030,
365 [TSU_FWSL1] = 0x0034,
366 [TSU_FWSLC] = 0x0038,
367 [TSU_QTAGM0] = 0x0040,
368 [TSU_QTAGM1] = 0x0044,
369 [TSU_ADQT0] = 0x0048,
370 [TSU_ADQT1] = 0x004c,
371 [TSU_FWSR] = 0x0050,
372 [TSU_FWINMK] = 0x0054,
373 [TSU_ADSBSY] = 0x0060,
374 [TSU_TEN] = 0x0064,
375 [TSU_POST1] = 0x0070,
376 [TSU_POST2] = 0x0074,
377 [TSU_POST3] = 0x0078,
378 [TSU_POST4] = 0x007c,
379
380 [TXNLCR0] = 0x0080,
381 [TXALCR0] = 0x0084,
382 [RXNLCR0] = 0x0088,
383 [RXALCR0] = 0x008c,
384 [FWNLCR0] = 0x0090,
385 [FWALCR0] = 0x0094,
386 [TXNLCR1] = 0x00a0,
387 [TXALCR1] = 0x00a0,
388 [RXNLCR1] = 0x00a8,
389 [RXALCR1] = 0x00ac,
390 [FWNLCR1] = 0x00b0,
391 [FWALCR1] = 0x00b4,
392
393 [TSU_ADRH0] = 0x0100,
394 [TSU_ADRL0] = 0x0104,
395 [TSU_ADRL31] = 0x01fc,
396 };
397
sh_eth_is_gether(struct sh_eth_private * mdp)398 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
399 {
400 return mdp->reg_offset == sh_eth_offset_gigabit;
401 }
402
sh_eth_is_rz_fast_ether(struct sh_eth_private * mdp)403 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
404 {
405 return mdp->reg_offset == sh_eth_offset_fast_rz;
406 }
407
sh_eth_select_mii(struct net_device * ndev)408 static void sh_eth_select_mii(struct net_device *ndev)
409 {
410 u32 value = 0x0;
411 struct sh_eth_private *mdp = netdev_priv(ndev);
412
413 switch (mdp->phy_interface) {
414 case PHY_INTERFACE_MODE_GMII:
415 value = 0x2;
416 break;
417 case PHY_INTERFACE_MODE_MII:
418 value = 0x1;
419 break;
420 case PHY_INTERFACE_MODE_RMII:
421 value = 0x0;
422 break;
423 default:
424 netdev_warn(ndev,
425 "PHY interface mode was not setup. Set to MII.\n");
426 value = 0x1;
427 break;
428 }
429
430 sh_eth_write(ndev, value, RMII_MII);
431 }
432
sh_eth_set_duplex(struct net_device * ndev)433 static void sh_eth_set_duplex(struct net_device *ndev)
434 {
435 struct sh_eth_private *mdp = netdev_priv(ndev);
436
437 if (mdp->duplex) /* Full */
438 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
439 else /* Half */
440 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
441 }
442
443 /* There is CPU dependent code */
sh_eth_set_rate_r8a777x(struct net_device * ndev)444 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
445 {
446 struct sh_eth_private *mdp = netdev_priv(ndev);
447
448 switch (mdp->speed) {
449 case 10: /* 10BASE */
450 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
451 break;
452 case 100:/* 100BASE */
453 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
454 break;
455 default:
456 break;
457 }
458 }
459
460 /* R8A7778/9 */
461 static struct sh_eth_cpu_data r8a777x_data = {
462 .set_duplex = sh_eth_set_duplex,
463 .set_rate = sh_eth_set_rate_r8a777x,
464
465 .register_type = SH_ETH_REG_FAST_RCAR,
466
467 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
468 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
469 .eesipr_value = 0x01ff009f,
470
471 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
472 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
473 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
474 EESR_ECI,
475
476 .apr = 1,
477 .mpr = 1,
478 .tpauser = 1,
479 .hw_swap = 1,
480 };
481
482 /* R8A7790/1 */
483 static struct sh_eth_cpu_data r8a779x_data = {
484 .set_duplex = sh_eth_set_duplex,
485 .set_rate = sh_eth_set_rate_r8a777x,
486
487 .register_type = SH_ETH_REG_FAST_RCAR,
488
489 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
490 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
491 .eesipr_value = 0x01ff009f,
492
493 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
494 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
495 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
496 EESR_ECI,
497
498 .apr = 1,
499 .mpr = 1,
500 .tpauser = 1,
501 .hw_swap = 1,
502 .rmiimode = 1,
503 .shift_rd0 = 1,
504 };
505
sh_eth_set_rate_sh7724(struct net_device * ndev)506 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
507 {
508 struct sh_eth_private *mdp = netdev_priv(ndev);
509
510 switch (mdp->speed) {
511 case 10: /* 10BASE */
512 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
513 break;
514 case 100:/* 100BASE */
515 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
516 break;
517 default:
518 break;
519 }
520 }
521
522 /* SH7724 */
523 static struct sh_eth_cpu_data sh7724_data = {
524 .set_duplex = sh_eth_set_duplex,
525 .set_rate = sh_eth_set_rate_sh7724,
526
527 .register_type = SH_ETH_REG_FAST_SH4,
528
529 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
530 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
531 .eesipr_value = 0x01ff009f,
532
533 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
534 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
535 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
536 EESR_ECI,
537
538 .apr = 1,
539 .mpr = 1,
540 .tpauser = 1,
541 .hw_swap = 1,
542 .rpadir = 1,
543 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
544 };
545
sh_eth_set_rate_sh7757(struct net_device * ndev)546 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
547 {
548 struct sh_eth_private *mdp = netdev_priv(ndev);
549
550 switch (mdp->speed) {
551 case 10: /* 10BASE */
552 sh_eth_write(ndev, 0, RTRATE);
553 break;
554 case 100:/* 100BASE */
555 sh_eth_write(ndev, 1, RTRATE);
556 break;
557 default:
558 break;
559 }
560 }
561
562 /* SH7757 */
563 static struct sh_eth_cpu_data sh7757_data = {
564 .set_duplex = sh_eth_set_duplex,
565 .set_rate = sh_eth_set_rate_sh7757,
566
567 .register_type = SH_ETH_REG_FAST_SH4,
568
569 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
570
571 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
572 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
573 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
574 EESR_ECI,
575
576 .irq_flags = IRQF_SHARED,
577 .apr = 1,
578 .mpr = 1,
579 .tpauser = 1,
580 .hw_swap = 1,
581 .no_ade = 1,
582 .rpadir = 1,
583 .rpadir_value = 2 << 16,
584 };
585
586 #define SH_GIGA_ETH_BASE 0xfee00000UL
587 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
588 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
sh_eth_chip_reset_giga(struct net_device * ndev)589 static void sh_eth_chip_reset_giga(struct net_device *ndev)
590 {
591 int i;
592 unsigned long mahr[2], malr[2];
593
594 /* save MAHR and MALR */
595 for (i = 0; i < 2; i++) {
596 malr[i] = ioread32((void *)GIGA_MALR(i));
597 mahr[i] = ioread32((void *)GIGA_MAHR(i));
598 }
599
600 /* reset device */
601 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
602 mdelay(1);
603
604 /* restore MAHR and MALR */
605 for (i = 0; i < 2; i++) {
606 iowrite32(malr[i], (void *)GIGA_MALR(i));
607 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
608 }
609 }
610
sh_eth_set_rate_giga(struct net_device * ndev)611 static void sh_eth_set_rate_giga(struct net_device *ndev)
612 {
613 struct sh_eth_private *mdp = netdev_priv(ndev);
614
615 switch (mdp->speed) {
616 case 10: /* 10BASE */
617 sh_eth_write(ndev, 0x00000000, GECMR);
618 break;
619 case 100:/* 100BASE */
620 sh_eth_write(ndev, 0x00000010, GECMR);
621 break;
622 case 1000: /* 1000BASE */
623 sh_eth_write(ndev, 0x00000020, GECMR);
624 break;
625 default:
626 break;
627 }
628 }
629
630 /* SH7757(GETHERC) */
631 static struct sh_eth_cpu_data sh7757_data_giga = {
632 .chip_reset = sh_eth_chip_reset_giga,
633 .set_duplex = sh_eth_set_duplex,
634 .set_rate = sh_eth_set_rate_giga,
635
636 .register_type = SH_ETH_REG_GIGABIT,
637
638 .ecsr_value = ECSR_ICD | ECSR_MPD,
639 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
640 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
641
642 .tx_check = EESR_TC1 | EESR_FTC,
643 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
644 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
645 EESR_TDE | EESR_ECI,
646 .fdr_value = 0x0000072f,
647
648 .irq_flags = IRQF_SHARED,
649 .apr = 1,
650 .mpr = 1,
651 .tpauser = 1,
652 .bculr = 1,
653 .hw_swap = 1,
654 .rpadir = 1,
655 .rpadir_value = 2 << 16,
656 .no_trimd = 1,
657 .no_ade = 1,
658 .tsu = 1,
659 };
660
sh_eth_chip_reset(struct net_device * ndev)661 static void sh_eth_chip_reset(struct net_device *ndev)
662 {
663 struct sh_eth_private *mdp = netdev_priv(ndev);
664
665 /* reset device */
666 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
667 mdelay(1);
668 }
669
sh_eth_set_rate_gether(struct net_device * ndev)670 static void sh_eth_set_rate_gether(struct net_device *ndev)
671 {
672 struct sh_eth_private *mdp = netdev_priv(ndev);
673
674 switch (mdp->speed) {
675 case 10: /* 10BASE */
676 sh_eth_write(ndev, GECMR_10, GECMR);
677 break;
678 case 100:/* 100BASE */
679 sh_eth_write(ndev, GECMR_100, GECMR);
680 break;
681 case 1000: /* 1000BASE */
682 sh_eth_write(ndev, GECMR_1000, GECMR);
683 break;
684 default:
685 break;
686 }
687 }
688
689 /* SH7734 */
690 static struct sh_eth_cpu_data sh7734_data = {
691 .chip_reset = sh_eth_chip_reset,
692 .set_duplex = sh_eth_set_duplex,
693 .set_rate = sh_eth_set_rate_gether,
694
695 .register_type = SH_ETH_REG_GIGABIT,
696
697 .ecsr_value = ECSR_ICD | ECSR_MPD,
698 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
699 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
700
701 .tx_check = EESR_TC1 | EESR_FTC,
702 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
703 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
704 EESR_TDE | EESR_ECI,
705
706 .apr = 1,
707 .mpr = 1,
708 .tpauser = 1,
709 .bculr = 1,
710 .hw_swap = 1,
711 .no_trimd = 1,
712 .no_ade = 1,
713 .tsu = 1,
714 .hw_crc = 1,
715 .select_mii = 1,
716 };
717
718 /* SH7763 */
719 static struct sh_eth_cpu_data sh7763_data = {
720 .chip_reset = sh_eth_chip_reset,
721 .set_duplex = sh_eth_set_duplex,
722 .set_rate = sh_eth_set_rate_gether,
723
724 .register_type = SH_ETH_REG_GIGABIT,
725
726 .ecsr_value = ECSR_ICD | ECSR_MPD,
727 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
728 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
729
730 .tx_check = EESR_TC1 | EESR_FTC,
731 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
732 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
733 EESR_ECI,
734
735 .apr = 1,
736 .mpr = 1,
737 .tpauser = 1,
738 .bculr = 1,
739 .hw_swap = 1,
740 .no_trimd = 1,
741 .no_ade = 1,
742 .tsu = 1,
743 .irq_flags = IRQF_SHARED,
744 };
745
sh_eth_chip_reset_r8a7740(struct net_device * ndev)746 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
747 {
748 struct sh_eth_private *mdp = netdev_priv(ndev);
749
750 /* reset device */
751 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
752 mdelay(1);
753
754 sh_eth_select_mii(ndev);
755 }
756
757 /* R8A7740 */
758 static struct sh_eth_cpu_data r8a7740_data = {
759 .chip_reset = sh_eth_chip_reset_r8a7740,
760 .set_duplex = sh_eth_set_duplex,
761 .set_rate = sh_eth_set_rate_gether,
762
763 .register_type = SH_ETH_REG_GIGABIT,
764
765 .ecsr_value = ECSR_ICD | ECSR_MPD,
766 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
767 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
768
769 .tx_check = EESR_TC1 | EESR_FTC,
770 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
771 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
772 EESR_TDE | EESR_ECI,
773 .fdr_value = 0x0000070f,
774
775 .apr = 1,
776 .mpr = 1,
777 .tpauser = 1,
778 .bculr = 1,
779 .hw_swap = 1,
780 .rpadir = 1,
781 .rpadir_value = 2 << 16,
782 .no_trimd = 1,
783 .no_ade = 1,
784 .hw_crc = 1,
785 .tsu = 1,
786 .select_mii = 1,
787 .shift_rd0 = 1,
788 };
789
790 /* R7S72100 */
791 static struct sh_eth_cpu_data r7s72100_data = {
792 .chip_reset = sh_eth_chip_reset,
793 .set_duplex = sh_eth_set_duplex,
794
795 .register_type = SH_ETH_REG_FAST_RZ,
796
797 .ecsr_value = ECSR_ICD,
798 .ecsipr_value = ECSIPR_ICDIP,
799 .eesipr_value = 0xff7f009f,
800
801 .tx_check = EESR_TC1 | EESR_FTC,
802 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
803 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
804 EESR_TDE | EESR_ECI,
805 .fdr_value = 0x0000070f,
806
807 .no_psr = 1,
808 .apr = 1,
809 .mpr = 1,
810 .tpauser = 1,
811 .hw_swap = 1,
812 .rpadir = 1,
813 .rpadir_value = 2 << 16,
814 .no_trimd = 1,
815 .no_ade = 1,
816 .hw_crc = 1,
817 .tsu = 1,
818 .shift_rd0 = 1,
819 };
820
821 static struct sh_eth_cpu_data sh7619_data = {
822 .register_type = SH_ETH_REG_FAST_SH3_SH2,
823
824 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
825
826 .apr = 1,
827 .mpr = 1,
828 .tpauser = 1,
829 .hw_swap = 1,
830 };
831
832 static struct sh_eth_cpu_data sh771x_data = {
833 .register_type = SH_ETH_REG_FAST_SH3_SH2,
834
835 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
836 .tsu = 1,
837 };
838
sh_eth_set_default_cpu_data(struct sh_eth_cpu_data * cd)839 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
840 {
841 if (!cd->ecsr_value)
842 cd->ecsr_value = DEFAULT_ECSR_INIT;
843
844 if (!cd->ecsipr_value)
845 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
846
847 if (!cd->fcftr_value)
848 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
849 DEFAULT_FIFO_F_D_RFD;
850
851 if (!cd->fdr_value)
852 cd->fdr_value = DEFAULT_FDR_INIT;
853
854 if (!cd->tx_check)
855 cd->tx_check = DEFAULT_TX_CHECK;
856
857 if (!cd->eesr_err_check)
858 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
859 }
860
sh_eth_check_reset(struct net_device * ndev)861 static int sh_eth_check_reset(struct net_device *ndev)
862 {
863 int ret = 0;
864 int cnt = 100;
865
866 while (cnt > 0) {
867 if (!(sh_eth_read(ndev, EDMR) & 0x3))
868 break;
869 mdelay(1);
870 cnt--;
871 }
872 if (cnt <= 0) {
873 netdev_err(ndev, "Device reset failed\n");
874 ret = -ETIMEDOUT;
875 }
876 return ret;
877 }
878
sh_eth_reset(struct net_device * ndev)879 static int sh_eth_reset(struct net_device *ndev)
880 {
881 struct sh_eth_private *mdp = netdev_priv(ndev);
882 int ret = 0;
883
884 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
885 sh_eth_write(ndev, EDSR_ENALL, EDSR);
886 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
887 EDMR);
888
889 ret = sh_eth_check_reset(ndev);
890 if (ret)
891 return ret;
892
893 /* Table Init */
894 sh_eth_write(ndev, 0x0, TDLAR);
895 sh_eth_write(ndev, 0x0, TDFAR);
896 sh_eth_write(ndev, 0x0, TDFXR);
897 sh_eth_write(ndev, 0x0, TDFFR);
898 sh_eth_write(ndev, 0x0, RDLAR);
899 sh_eth_write(ndev, 0x0, RDFAR);
900 sh_eth_write(ndev, 0x0, RDFXR);
901 sh_eth_write(ndev, 0x0, RDFFR);
902
903 /* Reset HW CRC register */
904 if (mdp->cd->hw_crc)
905 sh_eth_write(ndev, 0x0, CSMR);
906
907 /* Select MII mode */
908 if (mdp->cd->select_mii)
909 sh_eth_select_mii(ndev);
910 } else {
911 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
912 EDMR);
913 mdelay(3);
914 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
915 EDMR);
916 }
917
918 return ret;
919 }
920
sh_eth_set_receive_align(struct sk_buff * skb)921 static void sh_eth_set_receive_align(struct sk_buff *skb)
922 {
923 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
924
925 if (reserve)
926 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
927 }
928
929
930 /* CPU <-> EDMAC endian convert */
cpu_to_edmac(struct sh_eth_private * mdp,u32 x)931 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
932 {
933 switch (mdp->edmac_endian) {
934 case EDMAC_LITTLE_ENDIAN:
935 return cpu_to_le32(x);
936 case EDMAC_BIG_ENDIAN:
937 return cpu_to_be32(x);
938 }
939 return x;
940 }
941
edmac_to_cpu(struct sh_eth_private * mdp,u32 x)942 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
943 {
944 switch (mdp->edmac_endian) {
945 case EDMAC_LITTLE_ENDIAN:
946 return le32_to_cpu(x);
947 case EDMAC_BIG_ENDIAN:
948 return be32_to_cpu(x);
949 }
950 return x;
951 }
952
953 /* Program the hardware MAC address from dev->dev_addr. */
update_mac_address(struct net_device * ndev)954 static void update_mac_address(struct net_device *ndev)
955 {
956 sh_eth_write(ndev,
957 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
958 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
959 sh_eth_write(ndev,
960 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
961 }
962
963 /* Get MAC address from SuperH MAC address register
964 *
965 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
966 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
967 * When you want use this device, you must set MAC address in bootloader.
968 *
969 */
read_mac_address(struct net_device * ndev,unsigned char * mac)970 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
971 {
972 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
973 memcpy(ndev->dev_addr, mac, ETH_ALEN);
974 } else {
975 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
976 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
977 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
978 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
979 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
980 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
981 }
982 }
983
sh_eth_get_edtrr_trns(struct sh_eth_private * mdp)984 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
985 {
986 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
987 return EDTRR_TRNS_GETHER;
988 else
989 return EDTRR_TRNS_ETHER;
990 }
991
992 struct bb_info {
993 void (*set_gate)(void *addr);
994 struct mdiobb_ctrl ctrl;
995 void *addr;
996 u32 mmd_msk;/* MMD */
997 u32 mdo_msk;
998 u32 mdi_msk;
999 u32 mdc_msk;
1000 };
1001
1002 /* PHY bit set */
bb_set(void * addr,u32 msk)1003 static void bb_set(void *addr, u32 msk)
1004 {
1005 iowrite32(ioread32(addr) | msk, addr);
1006 }
1007
1008 /* PHY bit clear */
bb_clr(void * addr,u32 msk)1009 static void bb_clr(void *addr, u32 msk)
1010 {
1011 iowrite32((ioread32(addr) & ~msk), addr);
1012 }
1013
1014 /* PHY bit read */
bb_read(void * addr,u32 msk)1015 static int bb_read(void *addr, u32 msk)
1016 {
1017 return (ioread32(addr) & msk) != 0;
1018 }
1019
1020 /* Data I/O pin control */
sh_mmd_ctrl(struct mdiobb_ctrl * ctrl,int bit)1021 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1022 {
1023 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1024
1025 if (bitbang->set_gate)
1026 bitbang->set_gate(bitbang->addr);
1027
1028 if (bit)
1029 bb_set(bitbang->addr, bitbang->mmd_msk);
1030 else
1031 bb_clr(bitbang->addr, bitbang->mmd_msk);
1032 }
1033
1034 /* Set bit data*/
sh_set_mdio(struct mdiobb_ctrl * ctrl,int bit)1035 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1036 {
1037 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1038
1039 if (bitbang->set_gate)
1040 bitbang->set_gate(bitbang->addr);
1041
1042 if (bit)
1043 bb_set(bitbang->addr, bitbang->mdo_msk);
1044 else
1045 bb_clr(bitbang->addr, bitbang->mdo_msk);
1046 }
1047
1048 /* Get bit data*/
sh_get_mdio(struct mdiobb_ctrl * ctrl)1049 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1050 {
1051 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1052
1053 if (bitbang->set_gate)
1054 bitbang->set_gate(bitbang->addr);
1055
1056 return bb_read(bitbang->addr, bitbang->mdi_msk);
1057 }
1058
1059 /* MDC pin control */
sh_mdc_ctrl(struct mdiobb_ctrl * ctrl,int bit)1060 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1061 {
1062 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1063
1064 if (bitbang->set_gate)
1065 bitbang->set_gate(bitbang->addr);
1066
1067 if (bit)
1068 bb_set(bitbang->addr, bitbang->mdc_msk);
1069 else
1070 bb_clr(bitbang->addr, bitbang->mdc_msk);
1071 }
1072
1073 /* mdio bus control struct */
1074 static struct mdiobb_ops bb_ops = {
1075 .owner = THIS_MODULE,
1076 .set_mdc = sh_mdc_ctrl,
1077 .set_mdio_dir = sh_mmd_ctrl,
1078 .set_mdio_data = sh_set_mdio,
1079 .get_mdio_data = sh_get_mdio,
1080 };
1081
1082 /* free skb and descriptor buffer */
sh_eth_ring_free(struct net_device * ndev)1083 static void sh_eth_ring_free(struct net_device *ndev)
1084 {
1085 struct sh_eth_private *mdp = netdev_priv(ndev);
1086 int i;
1087
1088 /* Free Rx skb ringbuffer */
1089 if (mdp->rx_skbuff) {
1090 for (i = 0; i < mdp->num_rx_ring; i++)
1091 dev_kfree_skb(mdp->rx_skbuff[i]);
1092 }
1093 kfree(mdp->rx_skbuff);
1094 mdp->rx_skbuff = NULL;
1095
1096 /* Free Tx skb ringbuffer */
1097 if (mdp->tx_skbuff) {
1098 for (i = 0; i < mdp->num_tx_ring; i++)
1099 dev_kfree_skb(mdp->tx_skbuff[i]);
1100 }
1101 kfree(mdp->tx_skbuff);
1102 mdp->tx_skbuff = NULL;
1103 }
1104
1105 /* format skb and descriptor buffer */
sh_eth_ring_format(struct net_device * ndev)1106 static void sh_eth_ring_format(struct net_device *ndev)
1107 {
1108 struct sh_eth_private *mdp = netdev_priv(ndev);
1109 int i;
1110 struct sk_buff *skb;
1111 struct sh_eth_rxdesc *rxdesc = NULL;
1112 struct sh_eth_txdesc *txdesc = NULL;
1113 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1114 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1115 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN - 1;
1116 dma_addr_t dma_addr;
1117
1118 mdp->cur_rx = 0;
1119 mdp->cur_tx = 0;
1120 mdp->dirty_rx = 0;
1121 mdp->dirty_tx = 0;
1122
1123 memset(mdp->rx_ring, 0, rx_ringsize);
1124
1125 /* build Rx ring buffer */
1126 for (i = 0; i < mdp->num_rx_ring; i++) {
1127 /* skb */
1128 mdp->rx_skbuff[i] = NULL;
1129 skb = netdev_alloc_skb(ndev, skbuff_size);
1130 if (skb == NULL)
1131 break;
1132 sh_eth_set_receive_align(skb);
1133
1134 /* RX descriptor */
1135 rxdesc = &mdp->rx_ring[i];
1136 /* The size of the buffer is a multiple of 32 bytes. */
1137 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 32);
1138 dma_addr = dma_map_single(&ndev->dev, skb->data,
1139 rxdesc->buffer_length,
1140 DMA_FROM_DEVICE);
1141 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1142 kfree_skb(skb);
1143 break;
1144 }
1145 mdp->rx_skbuff[i] = skb;
1146 rxdesc->addr = dma_addr;
1147 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1148
1149 /* Rx descriptor address set */
1150 if (i == 0) {
1151 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1152 if (sh_eth_is_gether(mdp) ||
1153 sh_eth_is_rz_fast_ether(mdp))
1154 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1155 }
1156 }
1157
1158 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1159
1160 /* Mark the last entry as wrapping the ring. */
1161 if (rxdesc)
1162 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
1163
1164 memset(mdp->tx_ring, 0, tx_ringsize);
1165
1166 /* build Tx ring buffer */
1167 for (i = 0; i < mdp->num_tx_ring; i++) {
1168 mdp->tx_skbuff[i] = NULL;
1169 txdesc = &mdp->tx_ring[i];
1170 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1171 txdesc->buffer_length = 0;
1172 if (i == 0) {
1173 /* Tx descriptor address set */
1174 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1175 if (sh_eth_is_gether(mdp) ||
1176 sh_eth_is_rz_fast_ether(mdp))
1177 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1178 }
1179 }
1180
1181 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1182 }
1183
1184 /* Get skb and descriptor buffer */
sh_eth_ring_init(struct net_device * ndev)1185 static int sh_eth_ring_init(struct net_device *ndev)
1186 {
1187 struct sh_eth_private *mdp = netdev_priv(ndev);
1188 int rx_ringsize, tx_ringsize, ret = 0;
1189
1190 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1191 * card needs room to do 8 byte alignment, +2 so we can reserve
1192 * the first 2 bytes, and +16 gets room for the status word from the
1193 * card.
1194 */
1195 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1196 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1197 if (mdp->cd->rpadir)
1198 mdp->rx_buf_sz += NET_IP_ALIGN;
1199
1200 /* Allocate RX and TX skb rings */
1201 mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1202 sizeof(*mdp->rx_skbuff), GFP_KERNEL);
1203 if (!mdp->rx_skbuff) {
1204 ret = -ENOMEM;
1205 return ret;
1206 }
1207
1208 mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1209 sizeof(*mdp->tx_skbuff), GFP_KERNEL);
1210 if (!mdp->tx_skbuff) {
1211 ret = -ENOMEM;
1212 goto skb_ring_free;
1213 }
1214
1215 /* Allocate all Rx descriptors. */
1216 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1217 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1218 GFP_KERNEL);
1219 if (!mdp->rx_ring) {
1220 ret = -ENOMEM;
1221 goto desc_ring_free;
1222 }
1223
1224 mdp->dirty_rx = 0;
1225
1226 /* Allocate all Tx descriptors. */
1227 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1228 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1229 GFP_KERNEL);
1230 if (!mdp->tx_ring) {
1231 ret = -ENOMEM;
1232 goto desc_ring_free;
1233 }
1234 return ret;
1235
1236 desc_ring_free:
1237 /* free DMA buffer */
1238 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1239
1240 skb_ring_free:
1241 /* Free Rx and Tx skb ring buffer */
1242 sh_eth_ring_free(ndev);
1243 mdp->tx_ring = NULL;
1244 mdp->rx_ring = NULL;
1245
1246 return ret;
1247 }
1248
sh_eth_free_dma_buffer(struct sh_eth_private * mdp)1249 static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1250 {
1251 int ringsize;
1252
1253 if (mdp->rx_ring) {
1254 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1255 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1256 mdp->rx_desc_dma);
1257 mdp->rx_ring = NULL;
1258 }
1259
1260 if (mdp->tx_ring) {
1261 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1262 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1263 mdp->tx_desc_dma);
1264 mdp->tx_ring = NULL;
1265 }
1266 }
1267
sh_eth_dev_init(struct net_device * ndev,bool start)1268 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1269 {
1270 int ret = 0;
1271 struct sh_eth_private *mdp = netdev_priv(ndev);
1272 u32 val;
1273
1274 /* Soft Reset */
1275 ret = sh_eth_reset(ndev);
1276 if (ret)
1277 return ret;
1278
1279 if (mdp->cd->rmiimode)
1280 sh_eth_write(ndev, 0x1, RMIIMODE);
1281
1282 /* Descriptor format */
1283 sh_eth_ring_format(ndev);
1284 if (mdp->cd->rpadir)
1285 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1286
1287 /* all sh_eth int mask */
1288 sh_eth_write(ndev, 0, EESIPR);
1289
1290 #if defined(__LITTLE_ENDIAN)
1291 if (mdp->cd->hw_swap)
1292 sh_eth_write(ndev, EDMR_EL, EDMR);
1293 else
1294 #endif
1295 sh_eth_write(ndev, 0, EDMR);
1296
1297 /* FIFO size set */
1298 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1299 sh_eth_write(ndev, 0, TFTR);
1300
1301 /* Frame recv control (enable multiple-packets per rx irq) */
1302 sh_eth_write(ndev, RMCR_RNC, RMCR);
1303
1304 sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
1305
1306 if (mdp->cd->bculr)
1307 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
1308
1309 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1310
1311 if (!mdp->cd->no_trimd)
1312 sh_eth_write(ndev, 0, TRIMD);
1313
1314 /* Recv frame limit set register */
1315 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1316 RFLR);
1317
1318 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1319 if (start)
1320 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1321
1322 /* PAUSE Prohibition */
1323 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1324 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1325
1326 sh_eth_write(ndev, val, ECMR);
1327
1328 if (mdp->cd->set_rate)
1329 mdp->cd->set_rate(ndev);
1330
1331 /* E-MAC Status Register clear */
1332 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1333
1334 /* E-MAC Interrupt Enable register */
1335 if (start)
1336 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1337
1338 /* Set MAC address */
1339 update_mac_address(ndev);
1340
1341 /* mask reset */
1342 if (mdp->cd->apr)
1343 sh_eth_write(ndev, APR_AP, APR);
1344 if (mdp->cd->mpr)
1345 sh_eth_write(ndev, MPR_MP, MPR);
1346 if (mdp->cd->tpauser)
1347 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1348
1349 if (start) {
1350 /* Setting the Rx mode will start the Rx process. */
1351 sh_eth_write(ndev, EDRRR_R, EDRRR);
1352
1353 netif_start_queue(ndev);
1354 }
1355
1356 return ret;
1357 }
1358
1359 /* free Tx skb function */
sh_eth_txfree(struct net_device * ndev)1360 static int sh_eth_txfree(struct net_device *ndev)
1361 {
1362 struct sh_eth_private *mdp = netdev_priv(ndev);
1363 struct sh_eth_txdesc *txdesc;
1364 int free_num = 0;
1365 int entry = 0;
1366
1367 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1368 entry = mdp->dirty_tx % mdp->num_tx_ring;
1369 txdesc = &mdp->tx_ring[entry];
1370 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1371 break;
1372 /* Free the original skb. */
1373 if (mdp->tx_skbuff[entry]) {
1374 dma_unmap_single(&ndev->dev, txdesc->addr,
1375 txdesc->buffer_length, DMA_TO_DEVICE);
1376 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1377 mdp->tx_skbuff[entry] = NULL;
1378 free_num++;
1379 }
1380 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1381 if (entry >= mdp->num_tx_ring - 1)
1382 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1383
1384 ndev->stats.tx_packets++;
1385 ndev->stats.tx_bytes += txdesc->buffer_length;
1386 }
1387 return free_num;
1388 }
1389
1390 /* Packet receive function */
sh_eth_rx(struct net_device * ndev,u32 intr_status,int * quota)1391 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1392 {
1393 struct sh_eth_private *mdp = netdev_priv(ndev);
1394 struct sh_eth_rxdesc *rxdesc;
1395
1396 int entry = mdp->cur_rx % mdp->num_rx_ring;
1397 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1398 struct sk_buff *skb;
1399 u16 pkt_len = 0;
1400 u32 desc_status;
1401 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN - 1;
1402 dma_addr_t dma_addr;
1403
1404 rxdesc = &mdp->rx_ring[entry];
1405 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1406 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1407 pkt_len = rxdesc->frame_length;
1408
1409 if (--boguscnt < 0)
1410 break;
1411
1412 if (*quota <= 0)
1413 break;
1414
1415 (*quota)--;
1416
1417 if (!(desc_status & RDFEND))
1418 ndev->stats.rx_length_errors++;
1419
1420 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1421 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1422 * bit 0. However, in case of the R8A7740, R8A779x, and
1423 * R7S72100 the RFS bits are from bit 25 to bit 16. So, the
1424 * driver needs right shifting by 16.
1425 */
1426 if (mdp->cd->shift_rd0)
1427 desc_status >>= 16;
1428
1429 skb = mdp->rx_skbuff[entry];
1430 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1431 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1432 ndev->stats.rx_errors++;
1433 if (desc_status & RD_RFS1)
1434 ndev->stats.rx_crc_errors++;
1435 if (desc_status & RD_RFS2)
1436 ndev->stats.rx_frame_errors++;
1437 if (desc_status & RD_RFS3)
1438 ndev->stats.rx_length_errors++;
1439 if (desc_status & RD_RFS4)
1440 ndev->stats.rx_length_errors++;
1441 if (desc_status & RD_RFS6)
1442 ndev->stats.rx_missed_errors++;
1443 if (desc_status & RD_RFS10)
1444 ndev->stats.rx_over_errors++;
1445 } else if (skb) {
1446 if (!mdp->cd->hw_swap)
1447 sh_eth_soft_swap(
1448 phys_to_virt(ALIGN(rxdesc->addr, 4)),
1449 pkt_len + 2);
1450 mdp->rx_skbuff[entry] = NULL;
1451 if (mdp->cd->rpadir)
1452 skb_reserve(skb, NET_IP_ALIGN);
1453 dma_unmap_single(&ndev->dev, rxdesc->addr,
1454 ALIGN(mdp->rx_buf_sz, 32),
1455 DMA_FROM_DEVICE);
1456 skb_put(skb, pkt_len);
1457 skb->protocol = eth_type_trans(skb, ndev);
1458 netif_receive_skb(skb);
1459 ndev->stats.rx_packets++;
1460 ndev->stats.rx_bytes += pkt_len;
1461 }
1462 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1463 rxdesc = &mdp->rx_ring[entry];
1464 }
1465
1466 /* Refill the Rx ring buffers. */
1467 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1468 entry = mdp->dirty_rx % mdp->num_rx_ring;
1469 rxdesc = &mdp->rx_ring[entry];
1470 /* The size of the buffer is 32 byte boundary. */
1471 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 32);
1472
1473 if (mdp->rx_skbuff[entry] == NULL) {
1474 skb = netdev_alloc_skb(ndev, skbuff_size);
1475 if (skb == NULL)
1476 break; /* Better luck next round. */
1477 sh_eth_set_receive_align(skb);
1478 dma_addr = dma_map_single(&ndev->dev, skb->data,
1479 rxdesc->buffer_length,
1480 DMA_FROM_DEVICE);
1481 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1482 kfree_skb(skb);
1483 break;
1484 }
1485 mdp->rx_skbuff[entry] = skb;
1486
1487 skb_checksum_none_assert(skb);
1488 rxdesc->addr = dma_addr;
1489 }
1490 if (entry >= mdp->num_rx_ring - 1)
1491 rxdesc->status |=
1492 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
1493 else
1494 rxdesc->status |=
1495 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1496 }
1497
1498 /* Restart Rx engine if stopped. */
1499 /* If we don't need to check status, don't. -KDU */
1500 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1501 /* fix the values for the next receiving if RDE is set */
1502 if (intr_status & EESR_RDE) {
1503 u32 count = (sh_eth_read(ndev, RDFAR) -
1504 sh_eth_read(ndev, RDLAR)) >> 4;
1505
1506 mdp->cur_rx = count;
1507 mdp->dirty_rx = count;
1508 }
1509 sh_eth_write(ndev, EDRRR_R, EDRRR);
1510 }
1511
1512 return *quota <= 0;
1513 }
1514
sh_eth_rcv_snd_disable(struct net_device * ndev)1515 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1516 {
1517 /* disable tx and rx */
1518 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1519 ~(ECMR_RE | ECMR_TE), ECMR);
1520 }
1521
sh_eth_rcv_snd_enable(struct net_device * ndev)1522 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1523 {
1524 /* enable tx and rx */
1525 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1526 (ECMR_RE | ECMR_TE), ECMR);
1527 }
1528
1529 /* error control function */
sh_eth_error(struct net_device * ndev,int intr_status)1530 static void sh_eth_error(struct net_device *ndev, int intr_status)
1531 {
1532 struct sh_eth_private *mdp = netdev_priv(ndev);
1533 u32 felic_stat;
1534 u32 link_stat;
1535 u32 mask;
1536
1537 if (intr_status & EESR_ECI) {
1538 felic_stat = sh_eth_read(ndev, ECSR);
1539 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1540 if (felic_stat & ECSR_ICD)
1541 ndev->stats.tx_carrier_errors++;
1542 if (felic_stat & ECSR_LCHNG) {
1543 /* Link Changed */
1544 if (mdp->cd->no_psr || mdp->no_ether_link) {
1545 goto ignore_link;
1546 } else {
1547 link_stat = (sh_eth_read(ndev, PSR));
1548 if (mdp->ether_link_active_low)
1549 link_stat = ~link_stat;
1550 }
1551 if (!(link_stat & PHY_ST_LINK)) {
1552 sh_eth_rcv_snd_disable(ndev);
1553 } else {
1554 /* Link Up */
1555 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1556 ~DMAC_M_ECI, EESIPR);
1557 /* clear int */
1558 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1559 ECSR);
1560 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1561 DMAC_M_ECI, EESIPR);
1562 /* enable tx and rx */
1563 sh_eth_rcv_snd_enable(ndev);
1564 }
1565 }
1566 }
1567
1568 ignore_link:
1569 if (intr_status & EESR_TWB) {
1570 /* Unused write back interrupt */
1571 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1572 ndev->stats.tx_aborted_errors++;
1573 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1574 }
1575 }
1576
1577 if (intr_status & EESR_RABT) {
1578 /* Receive Abort int */
1579 if (intr_status & EESR_RFRMER) {
1580 /* Receive Frame Overflow int */
1581 ndev->stats.rx_frame_errors++;
1582 netif_err(mdp, rx_err, ndev, "Receive Abort\n");
1583 }
1584 }
1585
1586 if (intr_status & EESR_TDE) {
1587 /* Transmit Descriptor Empty int */
1588 ndev->stats.tx_fifo_errors++;
1589 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1590 }
1591
1592 if (intr_status & EESR_TFE) {
1593 /* FIFO under flow */
1594 ndev->stats.tx_fifo_errors++;
1595 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1596 }
1597
1598 if (intr_status & EESR_RDE) {
1599 /* Receive Descriptor Empty int */
1600 ndev->stats.rx_over_errors++;
1601 netif_err(mdp, rx_err, ndev, "Receive Descriptor Empty\n");
1602 }
1603
1604 if (intr_status & EESR_RFE) {
1605 /* Receive FIFO Overflow int */
1606 ndev->stats.rx_fifo_errors++;
1607 netif_err(mdp, rx_err, ndev, "Receive FIFO Overflow\n");
1608 }
1609
1610 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1611 /* Address Error */
1612 ndev->stats.tx_fifo_errors++;
1613 netif_err(mdp, tx_err, ndev, "Address Error\n");
1614 }
1615
1616 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1617 if (mdp->cd->no_ade)
1618 mask &= ~EESR_ADE;
1619 if (intr_status & mask) {
1620 /* Tx error */
1621 u32 edtrr = sh_eth_read(ndev, EDTRR);
1622
1623 /* dmesg */
1624 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1625 intr_status, mdp->cur_tx, mdp->dirty_tx,
1626 (u32)ndev->state, edtrr);
1627 /* dirty buffer free */
1628 sh_eth_txfree(ndev);
1629
1630 /* SH7712 BUG */
1631 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1632 /* tx dma start */
1633 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1634 }
1635 /* wakeup */
1636 netif_wake_queue(ndev);
1637 }
1638 }
1639
sh_eth_interrupt(int irq,void * netdev)1640 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1641 {
1642 struct net_device *ndev = netdev;
1643 struct sh_eth_private *mdp = netdev_priv(ndev);
1644 struct sh_eth_cpu_data *cd = mdp->cd;
1645 irqreturn_t ret = IRQ_NONE;
1646 unsigned long intr_status, intr_enable;
1647
1648 spin_lock(&mdp->lock);
1649
1650 /* Get interrupt status */
1651 intr_status = sh_eth_read(ndev, EESR);
1652 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1653 * enabled since it's the one that comes thru regardless of the mask,
1654 * and we need to fully handle it in sh_eth_error() in order to quench
1655 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1656 */
1657 intr_enable = sh_eth_read(ndev, EESIPR);
1658 intr_status &= intr_enable | DMAC_M_ECI;
1659 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1660 ret = IRQ_HANDLED;
1661 else
1662 goto other_irq;
1663
1664 if (intr_status & EESR_RX_CHECK) {
1665 if (napi_schedule_prep(&mdp->napi)) {
1666 /* Mask Rx interrupts */
1667 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1668 EESIPR);
1669 __napi_schedule(&mdp->napi);
1670 } else {
1671 netdev_warn(ndev,
1672 "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n",
1673 intr_status, intr_enable);
1674 }
1675 }
1676
1677 /* Tx Check */
1678 if (intr_status & cd->tx_check) {
1679 /* Clear Tx interrupts */
1680 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1681
1682 sh_eth_txfree(ndev);
1683 netif_wake_queue(ndev);
1684 }
1685
1686 if (intr_status & cd->eesr_err_check) {
1687 /* Clear error interrupts */
1688 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1689
1690 sh_eth_error(ndev, intr_status);
1691 }
1692
1693 other_irq:
1694 spin_unlock(&mdp->lock);
1695
1696 return ret;
1697 }
1698
sh_eth_poll(struct napi_struct * napi,int budget)1699 static int sh_eth_poll(struct napi_struct *napi, int budget)
1700 {
1701 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1702 napi);
1703 struct net_device *ndev = napi->dev;
1704 int quota = budget;
1705 unsigned long intr_status;
1706
1707 for (;;) {
1708 intr_status = sh_eth_read(ndev, EESR);
1709 if (!(intr_status & EESR_RX_CHECK))
1710 break;
1711 /* Clear Rx interrupts */
1712 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1713
1714 if (sh_eth_rx(ndev, intr_status, "a))
1715 goto out;
1716 }
1717
1718 napi_complete(napi);
1719
1720 /* Reenable Rx interrupts */
1721 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1722 out:
1723 return budget - quota;
1724 }
1725
1726 /* PHY state control function */
sh_eth_adjust_link(struct net_device * ndev)1727 static void sh_eth_adjust_link(struct net_device *ndev)
1728 {
1729 struct sh_eth_private *mdp = netdev_priv(ndev);
1730 struct phy_device *phydev = mdp->phydev;
1731 int new_state = 0;
1732
1733 if (phydev->link) {
1734 if (phydev->duplex != mdp->duplex) {
1735 new_state = 1;
1736 mdp->duplex = phydev->duplex;
1737 if (mdp->cd->set_duplex)
1738 mdp->cd->set_duplex(ndev);
1739 }
1740
1741 if (phydev->speed != mdp->speed) {
1742 new_state = 1;
1743 mdp->speed = phydev->speed;
1744 if (mdp->cd->set_rate)
1745 mdp->cd->set_rate(ndev);
1746 }
1747 if (!mdp->link) {
1748 sh_eth_write(ndev,
1749 sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1750 ECMR);
1751 new_state = 1;
1752 mdp->link = phydev->link;
1753 if (mdp->cd->no_psr || mdp->no_ether_link)
1754 sh_eth_rcv_snd_enable(ndev);
1755 }
1756 } else if (mdp->link) {
1757 new_state = 1;
1758 mdp->link = 0;
1759 mdp->speed = 0;
1760 mdp->duplex = -1;
1761 if (mdp->cd->no_psr || mdp->no_ether_link)
1762 sh_eth_rcv_snd_disable(ndev);
1763 }
1764
1765 if (new_state && netif_msg_link(mdp))
1766 phy_print_status(phydev);
1767 }
1768
1769 /* PHY init function */
sh_eth_phy_init(struct net_device * ndev)1770 static int sh_eth_phy_init(struct net_device *ndev)
1771 {
1772 struct device_node *np = ndev->dev.parent->of_node;
1773 struct sh_eth_private *mdp = netdev_priv(ndev);
1774 struct phy_device *phydev = NULL;
1775
1776 mdp->link = 0;
1777 mdp->speed = 0;
1778 mdp->duplex = -1;
1779
1780 /* Try connect to PHY */
1781 if (np) {
1782 struct device_node *pn;
1783
1784 pn = of_parse_phandle(np, "phy-handle", 0);
1785 phydev = of_phy_connect(ndev, pn,
1786 sh_eth_adjust_link, 0,
1787 mdp->phy_interface);
1788
1789 if (!phydev)
1790 phydev = ERR_PTR(-ENOENT);
1791 } else {
1792 char phy_id[MII_BUS_ID_SIZE + 3];
1793
1794 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1795 mdp->mii_bus->id, mdp->phy_id);
1796
1797 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1798 mdp->phy_interface);
1799 }
1800
1801 if (IS_ERR(phydev)) {
1802 netdev_err(ndev, "failed to connect PHY\n");
1803 return PTR_ERR(phydev);
1804 }
1805
1806 netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
1807 phydev->addr, phydev->irq, phydev->drv->name);
1808
1809 mdp->phydev = phydev;
1810
1811 return 0;
1812 }
1813
1814 /* PHY control start function */
sh_eth_phy_start(struct net_device * ndev)1815 static int sh_eth_phy_start(struct net_device *ndev)
1816 {
1817 struct sh_eth_private *mdp = netdev_priv(ndev);
1818 int ret;
1819
1820 ret = sh_eth_phy_init(ndev);
1821 if (ret)
1822 return ret;
1823
1824 phy_start(mdp->phydev);
1825
1826 return 0;
1827 }
1828
sh_eth_get_settings(struct net_device * ndev,struct ethtool_cmd * ecmd)1829 static int sh_eth_get_settings(struct net_device *ndev,
1830 struct ethtool_cmd *ecmd)
1831 {
1832 struct sh_eth_private *mdp = netdev_priv(ndev);
1833 unsigned long flags;
1834 int ret;
1835
1836 if (!mdp->phydev)
1837 return -ENODEV;
1838
1839 spin_lock_irqsave(&mdp->lock, flags);
1840 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1841 spin_unlock_irqrestore(&mdp->lock, flags);
1842
1843 return ret;
1844 }
1845
sh_eth_set_settings(struct net_device * ndev,struct ethtool_cmd * ecmd)1846 static int sh_eth_set_settings(struct net_device *ndev,
1847 struct ethtool_cmd *ecmd)
1848 {
1849 struct sh_eth_private *mdp = netdev_priv(ndev);
1850 unsigned long flags;
1851 int ret;
1852
1853 if (!mdp->phydev)
1854 return -ENODEV;
1855
1856 spin_lock_irqsave(&mdp->lock, flags);
1857
1858 /* disable tx and rx */
1859 sh_eth_rcv_snd_disable(ndev);
1860
1861 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1862 if (ret)
1863 goto error_exit;
1864
1865 if (ecmd->duplex == DUPLEX_FULL)
1866 mdp->duplex = 1;
1867 else
1868 mdp->duplex = 0;
1869
1870 if (mdp->cd->set_duplex)
1871 mdp->cd->set_duplex(ndev);
1872
1873 error_exit:
1874 mdelay(1);
1875
1876 /* enable tx and rx */
1877 sh_eth_rcv_snd_enable(ndev);
1878
1879 spin_unlock_irqrestore(&mdp->lock, flags);
1880
1881 return ret;
1882 }
1883
sh_eth_nway_reset(struct net_device * ndev)1884 static int sh_eth_nway_reset(struct net_device *ndev)
1885 {
1886 struct sh_eth_private *mdp = netdev_priv(ndev);
1887 unsigned long flags;
1888 int ret;
1889
1890 if (!mdp->phydev)
1891 return -ENODEV;
1892
1893 spin_lock_irqsave(&mdp->lock, flags);
1894 ret = phy_start_aneg(mdp->phydev);
1895 spin_unlock_irqrestore(&mdp->lock, flags);
1896
1897 return ret;
1898 }
1899
sh_eth_get_msglevel(struct net_device * ndev)1900 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1901 {
1902 struct sh_eth_private *mdp = netdev_priv(ndev);
1903 return mdp->msg_enable;
1904 }
1905
sh_eth_set_msglevel(struct net_device * ndev,u32 value)1906 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1907 {
1908 struct sh_eth_private *mdp = netdev_priv(ndev);
1909 mdp->msg_enable = value;
1910 }
1911
1912 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1913 "rx_current", "tx_current",
1914 "rx_dirty", "tx_dirty",
1915 };
1916 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1917
sh_eth_get_sset_count(struct net_device * netdev,int sset)1918 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1919 {
1920 switch (sset) {
1921 case ETH_SS_STATS:
1922 return SH_ETH_STATS_LEN;
1923 default:
1924 return -EOPNOTSUPP;
1925 }
1926 }
1927
sh_eth_get_ethtool_stats(struct net_device * ndev,struct ethtool_stats * stats,u64 * data)1928 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1929 struct ethtool_stats *stats, u64 *data)
1930 {
1931 struct sh_eth_private *mdp = netdev_priv(ndev);
1932 int i = 0;
1933
1934 /* device-specific stats */
1935 data[i++] = mdp->cur_rx;
1936 data[i++] = mdp->cur_tx;
1937 data[i++] = mdp->dirty_rx;
1938 data[i++] = mdp->dirty_tx;
1939 }
1940
sh_eth_get_strings(struct net_device * ndev,u32 stringset,u8 * data)1941 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1942 {
1943 switch (stringset) {
1944 case ETH_SS_STATS:
1945 memcpy(data, *sh_eth_gstrings_stats,
1946 sizeof(sh_eth_gstrings_stats));
1947 break;
1948 }
1949 }
1950
sh_eth_get_ringparam(struct net_device * ndev,struct ethtool_ringparam * ring)1951 static void sh_eth_get_ringparam(struct net_device *ndev,
1952 struct ethtool_ringparam *ring)
1953 {
1954 struct sh_eth_private *mdp = netdev_priv(ndev);
1955
1956 ring->rx_max_pending = RX_RING_MAX;
1957 ring->tx_max_pending = TX_RING_MAX;
1958 ring->rx_pending = mdp->num_rx_ring;
1959 ring->tx_pending = mdp->num_tx_ring;
1960 }
1961
sh_eth_set_ringparam(struct net_device * ndev,struct ethtool_ringparam * ring)1962 static int sh_eth_set_ringparam(struct net_device *ndev,
1963 struct ethtool_ringparam *ring)
1964 {
1965 struct sh_eth_private *mdp = netdev_priv(ndev);
1966 int ret;
1967
1968 if (ring->tx_pending > TX_RING_MAX ||
1969 ring->rx_pending > RX_RING_MAX ||
1970 ring->tx_pending < TX_RING_MIN ||
1971 ring->rx_pending < RX_RING_MIN)
1972 return -EINVAL;
1973 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1974 return -EINVAL;
1975
1976 if (netif_running(ndev)) {
1977 netif_tx_disable(ndev);
1978 /* Disable interrupts by clearing the interrupt mask. */
1979 sh_eth_write(ndev, 0x0000, EESIPR);
1980 /* Stop the chip's Tx and Rx processes. */
1981 sh_eth_write(ndev, 0, EDTRR);
1982 sh_eth_write(ndev, 0, EDRRR);
1983 synchronize_irq(ndev->irq);
1984 }
1985
1986 /* Free all the skbuffs in the Rx queue. */
1987 sh_eth_ring_free(ndev);
1988 /* Free DMA buffer */
1989 sh_eth_free_dma_buffer(mdp);
1990
1991 /* Set new parameters */
1992 mdp->num_rx_ring = ring->rx_pending;
1993 mdp->num_tx_ring = ring->tx_pending;
1994
1995 ret = sh_eth_ring_init(ndev);
1996 if (ret < 0) {
1997 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n", __func__);
1998 return ret;
1999 }
2000 ret = sh_eth_dev_init(ndev, false);
2001 if (ret < 0) {
2002 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n", __func__);
2003 return ret;
2004 }
2005
2006 if (netif_running(ndev)) {
2007 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
2008 /* Setting the Rx mode will start the Rx process. */
2009 sh_eth_write(ndev, EDRRR_R, EDRRR);
2010 netif_wake_queue(ndev);
2011 }
2012
2013 return 0;
2014 }
2015
2016 static const struct ethtool_ops sh_eth_ethtool_ops = {
2017 .get_settings = sh_eth_get_settings,
2018 .set_settings = sh_eth_set_settings,
2019 .nway_reset = sh_eth_nway_reset,
2020 .get_msglevel = sh_eth_get_msglevel,
2021 .set_msglevel = sh_eth_set_msglevel,
2022 .get_link = ethtool_op_get_link,
2023 .get_strings = sh_eth_get_strings,
2024 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2025 .get_sset_count = sh_eth_get_sset_count,
2026 .get_ringparam = sh_eth_get_ringparam,
2027 .set_ringparam = sh_eth_set_ringparam,
2028 };
2029
2030 /* network device open function */
sh_eth_open(struct net_device * ndev)2031 static int sh_eth_open(struct net_device *ndev)
2032 {
2033 int ret = 0;
2034 struct sh_eth_private *mdp = netdev_priv(ndev);
2035
2036 pm_runtime_get_sync(&mdp->pdev->dev);
2037
2038 napi_enable(&mdp->napi);
2039
2040 ret = request_irq(ndev->irq, sh_eth_interrupt,
2041 mdp->cd->irq_flags, ndev->name, ndev);
2042 if (ret) {
2043 netdev_err(ndev, "Can not assign IRQ number\n");
2044 goto out_napi_off;
2045 }
2046
2047 /* Descriptor set */
2048 ret = sh_eth_ring_init(ndev);
2049 if (ret)
2050 goto out_free_irq;
2051
2052 /* device init */
2053 ret = sh_eth_dev_init(ndev, true);
2054 if (ret)
2055 goto out_free_irq;
2056
2057 /* PHY control start*/
2058 ret = sh_eth_phy_start(ndev);
2059 if (ret)
2060 goto out_free_irq;
2061
2062 mdp->is_opened = 1;
2063
2064 return ret;
2065
2066 out_free_irq:
2067 free_irq(ndev->irq, ndev);
2068 out_napi_off:
2069 napi_disable(&mdp->napi);
2070 pm_runtime_put_sync(&mdp->pdev->dev);
2071 return ret;
2072 }
2073
2074 /* Timeout function */
sh_eth_tx_timeout(struct net_device * ndev)2075 static void sh_eth_tx_timeout(struct net_device *ndev)
2076 {
2077 struct sh_eth_private *mdp = netdev_priv(ndev);
2078 struct sh_eth_rxdesc *rxdesc;
2079 int i;
2080
2081 netif_stop_queue(ndev);
2082
2083 netif_err(mdp, timer, ndev,
2084 "transmit timed out, status %8.8x, resetting...\n",
2085 (int)sh_eth_read(ndev, EESR));
2086
2087 /* tx_errors count up */
2088 ndev->stats.tx_errors++;
2089
2090 /* Free all the skbuffs in the Rx queue. */
2091 for (i = 0; i < mdp->num_rx_ring; i++) {
2092 rxdesc = &mdp->rx_ring[i];
2093 rxdesc->status = 0;
2094 rxdesc->addr = 0xBADF00D0;
2095 dev_kfree_skb(mdp->rx_skbuff[i]);
2096 mdp->rx_skbuff[i] = NULL;
2097 }
2098 for (i = 0; i < mdp->num_tx_ring; i++) {
2099 dev_kfree_skb(mdp->tx_skbuff[i]);
2100 mdp->tx_skbuff[i] = NULL;
2101 }
2102
2103 /* device init */
2104 sh_eth_dev_init(ndev, true);
2105 }
2106
2107 /* Packet transmit function */
sh_eth_start_xmit(struct sk_buff * skb,struct net_device * ndev)2108 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2109 {
2110 struct sh_eth_private *mdp = netdev_priv(ndev);
2111 struct sh_eth_txdesc *txdesc;
2112 u32 entry;
2113 unsigned long flags;
2114
2115 spin_lock_irqsave(&mdp->lock, flags);
2116 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2117 if (!sh_eth_txfree(ndev)) {
2118 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2119 netif_stop_queue(ndev);
2120 spin_unlock_irqrestore(&mdp->lock, flags);
2121 return NETDEV_TX_BUSY;
2122 }
2123 }
2124 spin_unlock_irqrestore(&mdp->lock, flags);
2125
2126 entry = mdp->cur_tx % mdp->num_tx_ring;
2127 mdp->tx_skbuff[entry] = skb;
2128 txdesc = &mdp->tx_ring[entry];
2129 /* soft swap. */
2130 if (!mdp->cd->hw_swap)
2131 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2132 skb->len + 2);
2133 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2134 DMA_TO_DEVICE);
2135 if (skb->len < ETH_ZLEN)
2136 txdesc->buffer_length = ETH_ZLEN;
2137 else
2138 txdesc->buffer_length = skb->len;
2139
2140 if (entry >= mdp->num_tx_ring - 1)
2141 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2142 else
2143 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
2144
2145 mdp->cur_tx++;
2146
2147 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2148 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2149
2150 return NETDEV_TX_OK;
2151 }
2152
sh_eth_get_stats(struct net_device * ndev)2153 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2154 {
2155 struct sh_eth_private *mdp = netdev_priv(ndev);
2156
2157 if (sh_eth_is_rz_fast_ether(mdp))
2158 return &ndev->stats;
2159
2160 if (!mdp->is_opened)
2161 return &ndev->stats;
2162
2163 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
2164 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
2165 ndev->stats.collisions += sh_eth_read(ndev, CDCR);
2166 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
2167 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
2168 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
2169
2170 if (sh_eth_is_gether(mdp)) {
2171 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
2172 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
2173 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
2174 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
2175 } else {
2176 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
2177 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
2178 }
2179
2180 return &ndev->stats;
2181 }
2182
2183 /* device close function */
sh_eth_close(struct net_device * ndev)2184 static int sh_eth_close(struct net_device *ndev)
2185 {
2186 struct sh_eth_private *mdp = netdev_priv(ndev);
2187
2188 netif_stop_queue(ndev);
2189
2190 /* Disable interrupts by clearing the interrupt mask. */
2191 sh_eth_write(ndev, 0x0000, EESIPR);
2192
2193 /* Stop the chip's Tx and Rx processes. */
2194 sh_eth_write(ndev, 0, EDTRR);
2195 sh_eth_write(ndev, 0, EDRRR);
2196
2197 sh_eth_get_stats(ndev);
2198 /* PHY Disconnect */
2199 if (mdp->phydev) {
2200 phy_stop(mdp->phydev);
2201 phy_disconnect(mdp->phydev);
2202 mdp->phydev = NULL;
2203 }
2204
2205 free_irq(ndev->irq, ndev);
2206
2207 napi_disable(&mdp->napi);
2208
2209 /* Free all the skbuffs in the Rx queue. */
2210 sh_eth_ring_free(ndev);
2211
2212 /* free DMA buffer */
2213 sh_eth_free_dma_buffer(mdp);
2214
2215 pm_runtime_put_sync(&mdp->pdev->dev);
2216
2217 mdp->is_opened = 0;
2218
2219 return 0;
2220 }
2221
2222 /* ioctl to device function */
sh_eth_do_ioctl(struct net_device * ndev,struct ifreq * rq,int cmd)2223 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2224 {
2225 struct sh_eth_private *mdp = netdev_priv(ndev);
2226 struct phy_device *phydev = mdp->phydev;
2227
2228 if (!netif_running(ndev))
2229 return -EINVAL;
2230
2231 if (!phydev)
2232 return -ENODEV;
2233
2234 return phy_mii_ioctl(phydev, rq, cmd);
2235 }
2236
2237 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
sh_eth_tsu_get_post_reg_offset(struct sh_eth_private * mdp,int entry)2238 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2239 int entry)
2240 {
2241 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2242 }
2243
sh_eth_tsu_get_post_mask(int entry)2244 static u32 sh_eth_tsu_get_post_mask(int entry)
2245 {
2246 return 0x0f << (28 - ((entry % 8) * 4));
2247 }
2248
sh_eth_tsu_get_post_bit(struct sh_eth_private * mdp,int entry)2249 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2250 {
2251 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2252 }
2253
sh_eth_tsu_enable_cam_entry_post(struct net_device * ndev,int entry)2254 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2255 int entry)
2256 {
2257 struct sh_eth_private *mdp = netdev_priv(ndev);
2258 u32 tmp;
2259 void *reg_offset;
2260
2261 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2262 tmp = ioread32(reg_offset);
2263 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2264 }
2265
sh_eth_tsu_disable_cam_entry_post(struct net_device * ndev,int entry)2266 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2267 int entry)
2268 {
2269 struct sh_eth_private *mdp = netdev_priv(ndev);
2270 u32 post_mask, ref_mask, tmp;
2271 void *reg_offset;
2272
2273 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2274 post_mask = sh_eth_tsu_get_post_mask(entry);
2275 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2276
2277 tmp = ioread32(reg_offset);
2278 iowrite32(tmp & ~post_mask, reg_offset);
2279
2280 /* If other port enables, the function returns "true" */
2281 return tmp & ref_mask;
2282 }
2283
sh_eth_tsu_busy(struct net_device * ndev)2284 static int sh_eth_tsu_busy(struct net_device *ndev)
2285 {
2286 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2287 struct sh_eth_private *mdp = netdev_priv(ndev);
2288
2289 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2290 udelay(10);
2291 timeout--;
2292 if (timeout <= 0) {
2293 netdev_err(ndev, "%s: timeout\n", __func__);
2294 return -ETIMEDOUT;
2295 }
2296 }
2297
2298 return 0;
2299 }
2300
sh_eth_tsu_write_entry(struct net_device * ndev,void * reg,const u8 * addr)2301 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2302 const u8 *addr)
2303 {
2304 u32 val;
2305
2306 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2307 iowrite32(val, reg);
2308 if (sh_eth_tsu_busy(ndev) < 0)
2309 return -EBUSY;
2310
2311 val = addr[4] << 8 | addr[5];
2312 iowrite32(val, reg + 4);
2313 if (sh_eth_tsu_busy(ndev) < 0)
2314 return -EBUSY;
2315
2316 return 0;
2317 }
2318
sh_eth_tsu_read_entry(void * reg,u8 * addr)2319 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2320 {
2321 u32 val;
2322
2323 val = ioread32(reg);
2324 addr[0] = (val >> 24) & 0xff;
2325 addr[1] = (val >> 16) & 0xff;
2326 addr[2] = (val >> 8) & 0xff;
2327 addr[3] = val & 0xff;
2328 val = ioread32(reg + 4);
2329 addr[4] = (val >> 8) & 0xff;
2330 addr[5] = val & 0xff;
2331 }
2332
2333
sh_eth_tsu_find_entry(struct net_device * ndev,const u8 * addr)2334 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2335 {
2336 struct sh_eth_private *mdp = netdev_priv(ndev);
2337 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2338 int i;
2339 u8 c_addr[ETH_ALEN];
2340
2341 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2342 sh_eth_tsu_read_entry(reg_offset, c_addr);
2343 if (ether_addr_equal(addr, c_addr))
2344 return i;
2345 }
2346
2347 return -ENOENT;
2348 }
2349
sh_eth_tsu_find_empty(struct net_device * ndev)2350 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2351 {
2352 u8 blank[ETH_ALEN];
2353 int entry;
2354
2355 memset(blank, 0, sizeof(blank));
2356 entry = sh_eth_tsu_find_entry(ndev, blank);
2357 return (entry < 0) ? -ENOMEM : entry;
2358 }
2359
sh_eth_tsu_disable_cam_entry_table(struct net_device * ndev,int entry)2360 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2361 int entry)
2362 {
2363 struct sh_eth_private *mdp = netdev_priv(ndev);
2364 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2365 int ret;
2366 u8 blank[ETH_ALEN];
2367
2368 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2369 ~(1 << (31 - entry)), TSU_TEN);
2370
2371 memset(blank, 0, sizeof(blank));
2372 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2373 if (ret < 0)
2374 return ret;
2375 return 0;
2376 }
2377
sh_eth_tsu_add_entry(struct net_device * ndev,const u8 * addr)2378 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2379 {
2380 struct sh_eth_private *mdp = netdev_priv(ndev);
2381 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2382 int i, ret;
2383
2384 if (!mdp->cd->tsu)
2385 return 0;
2386
2387 i = sh_eth_tsu_find_entry(ndev, addr);
2388 if (i < 0) {
2389 /* No entry found, create one */
2390 i = sh_eth_tsu_find_empty(ndev);
2391 if (i < 0)
2392 return -ENOMEM;
2393 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2394 if (ret < 0)
2395 return ret;
2396
2397 /* Enable the entry */
2398 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2399 (1 << (31 - i)), TSU_TEN);
2400 }
2401
2402 /* Entry found or created, enable POST */
2403 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2404
2405 return 0;
2406 }
2407
sh_eth_tsu_del_entry(struct net_device * ndev,const u8 * addr)2408 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2409 {
2410 struct sh_eth_private *mdp = netdev_priv(ndev);
2411 int i, ret;
2412
2413 if (!mdp->cd->tsu)
2414 return 0;
2415
2416 i = sh_eth_tsu_find_entry(ndev, addr);
2417 if (i) {
2418 /* Entry found */
2419 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2420 goto done;
2421
2422 /* Disable the entry if both ports was disabled */
2423 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2424 if (ret < 0)
2425 return ret;
2426 }
2427 done:
2428 return 0;
2429 }
2430
sh_eth_tsu_purge_all(struct net_device * ndev)2431 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2432 {
2433 struct sh_eth_private *mdp = netdev_priv(ndev);
2434 int i, ret;
2435
2436 if (unlikely(!mdp->cd->tsu))
2437 return 0;
2438
2439 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2440 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2441 continue;
2442
2443 /* Disable the entry if both ports was disabled */
2444 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2445 if (ret < 0)
2446 return ret;
2447 }
2448
2449 return 0;
2450 }
2451
sh_eth_tsu_purge_mcast(struct net_device * ndev)2452 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2453 {
2454 struct sh_eth_private *mdp = netdev_priv(ndev);
2455 u8 addr[ETH_ALEN];
2456 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2457 int i;
2458
2459 if (unlikely(!mdp->cd->tsu))
2460 return;
2461
2462 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2463 sh_eth_tsu_read_entry(reg_offset, addr);
2464 if (is_multicast_ether_addr(addr))
2465 sh_eth_tsu_del_entry(ndev, addr);
2466 }
2467 }
2468
2469 /* Multicast reception directions set */
sh_eth_set_multicast_list(struct net_device * ndev)2470 static void sh_eth_set_multicast_list(struct net_device *ndev)
2471 {
2472 struct sh_eth_private *mdp = netdev_priv(ndev);
2473 u32 ecmr_bits;
2474 int mcast_all = 0;
2475 unsigned long flags;
2476
2477 spin_lock_irqsave(&mdp->lock, flags);
2478 /* Initial condition is MCT = 1, PRM = 0.
2479 * Depending on ndev->flags, set PRM or clear MCT
2480 */
2481 ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2482
2483 if (!(ndev->flags & IFF_MULTICAST)) {
2484 sh_eth_tsu_purge_mcast(ndev);
2485 mcast_all = 1;
2486 }
2487 if (ndev->flags & IFF_ALLMULTI) {
2488 sh_eth_tsu_purge_mcast(ndev);
2489 ecmr_bits &= ~ECMR_MCT;
2490 mcast_all = 1;
2491 }
2492
2493 if (ndev->flags & IFF_PROMISC) {
2494 sh_eth_tsu_purge_all(ndev);
2495 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2496 } else if (mdp->cd->tsu) {
2497 struct netdev_hw_addr *ha;
2498 netdev_for_each_mc_addr(ha, ndev) {
2499 if (mcast_all && is_multicast_ether_addr(ha->addr))
2500 continue;
2501
2502 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2503 if (!mcast_all) {
2504 sh_eth_tsu_purge_mcast(ndev);
2505 ecmr_bits &= ~ECMR_MCT;
2506 mcast_all = 1;
2507 }
2508 }
2509 }
2510 } else {
2511 /* Normal, unicast/broadcast-only mode. */
2512 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
2513 }
2514
2515 /* update the ethernet mode */
2516 sh_eth_write(ndev, ecmr_bits, ECMR);
2517
2518 spin_unlock_irqrestore(&mdp->lock, flags);
2519 }
2520
sh_eth_get_vtag_index(struct sh_eth_private * mdp)2521 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2522 {
2523 if (!mdp->port)
2524 return TSU_VTAG0;
2525 else
2526 return TSU_VTAG1;
2527 }
2528
sh_eth_vlan_rx_add_vid(struct net_device * ndev,__be16 proto,u16 vid)2529 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2530 __be16 proto, u16 vid)
2531 {
2532 struct sh_eth_private *mdp = netdev_priv(ndev);
2533 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2534
2535 if (unlikely(!mdp->cd->tsu))
2536 return -EPERM;
2537
2538 /* No filtering if vid = 0 */
2539 if (!vid)
2540 return 0;
2541
2542 mdp->vlan_num_ids++;
2543
2544 /* The controller has one VLAN tag HW filter. So, if the filter is
2545 * already enabled, the driver disables it and the filte
2546 */
2547 if (mdp->vlan_num_ids > 1) {
2548 /* disable VLAN filter */
2549 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2550 return 0;
2551 }
2552
2553 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2554 vtag_reg_index);
2555
2556 return 0;
2557 }
2558
sh_eth_vlan_rx_kill_vid(struct net_device * ndev,__be16 proto,u16 vid)2559 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2560 __be16 proto, u16 vid)
2561 {
2562 struct sh_eth_private *mdp = netdev_priv(ndev);
2563 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2564
2565 if (unlikely(!mdp->cd->tsu))
2566 return -EPERM;
2567
2568 /* No filtering if vid = 0 */
2569 if (!vid)
2570 return 0;
2571
2572 mdp->vlan_num_ids--;
2573 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2574
2575 return 0;
2576 }
2577
2578 /* SuperH's TSU register init function */
sh_eth_tsu_init(struct sh_eth_private * mdp)2579 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2580 {
2581 if (sh_eth_is_rz_fast_ether(mdp)) {
2582 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2583 return;
2584 }
2585
2586 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2587 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2588 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2589 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2590 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2591 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2592 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2593 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2594 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2595 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2596 if (sh_eth_is_gether(mdp)) {
2597 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2598 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2599 } else {
2600 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2601 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2602 }
2603 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2604 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2605 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2606 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2607 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2608 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2609 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
2610 }
2611
2612 /* MDIO bus release function */
sh_mdio_release(struct sh_eth_private * mdp)2613 static int sh_mdio_release(struct sh_eth_private *mdp)
2614 {
2615 /* unregister mdio bus */
2616 mdiobus_unregister(mdp->mii_bus);
2617
2618 /* free bitbang info */
2619 free_mdio_bitbang(mdp->mii_bus);
2620
2621 return 0;
2622 }
2623
2624 /* MDIO bus init function */
sh_mdio_init(struct sh_eth_private * mdp,struct sh_eth_plat_data * pd)2625 static int sh_mdio_init(struct sh_eth_private *mdp,
2626 struct sh_eth_plat_data *pd)
2627 {
2628 int ret, i;
2629 struct bb_info *bitbang;
2630 struct platform_device *pdev = mdp->pdev;
2631 struct device *dev = &mdp->pdev->dev;
2632
2633 /* create bit control struct for PHY */
2634 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2635 if (!bitbang)
2636 return -ENOMEM;
2637
2638 /* bitbang init */
2639 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2640 bitbang->set_gate = pd->set_mdio_gate;
2641 bitbang->mdi_msk = PIR_MDI;
2642 bitbang->mdo_msk = PIR_MDO;
2643 bitbang->mmd_msk = PIR_MMD;
2644 bitbang->mdc_msk = PIR_MDC;
2645 bitbang->ctrl.ops = &bb_ops;
2646
2647 /* MII controller setting */
2648 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2649 if (!mdp->mii_bus)
2650 return -ENOMEM;
2651
2652 /* Hook up MII support for ethtool */
2653 mdp->mii_bus->name = "sh_mii";
2654 mdp->mii_bus->parent = dev;
2655 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2656 pdev->name, pdev->id);
2657
2658 /* PHY IRQ */
2659 mdp->mii_bus->irq = devm_kmalloc_array(dev, PHY_MAX_ADDR, sizeof(int),
2660 GFP_KERNEL);
2661 if (!mdp->mii_bus->irq) {
2662 ret = -ENOMEM;
2663 goto out_free_bus;
2664 }
2665
2666 /* register MDIO bus */
2667 if (dev->of_node) {
2668 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2669 } else {
2670 for (i = 0; i < PHY_MAX_ADDR; i++)
2671 mdp->mii_bus->irq[i] = PHY_POLL;
2672 if (pd->phy_irq > 0)
2673 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2674
2675 ret = mdiobus_register(mdp->mii_bus);
2676 }
2677
2678 if (ret)
2679 goto out_free_bus;
2680
2681 return 0;
2682
2683 out_free_bus:
2684 free_mdio_bitbang(mdp->mii_bus);
2685 return ret;
2686 }
2687
sh_eth_get_register_offset(int register_type)2688 static const u16 *sh_eth_get_register_offset(int register_type)
2689 {
2690 const u16 *reg_offset = NULL;
2691
2692 switch (register_type) {
2693 case SH_ETH_REG_GIGABIT:
2694 reg_offset = sh_eth_offset_gigabit;
2695 break;
2696 case SH_ETH_REG_FAST_RZ:
2697 reg_offset = sh_eth_offset_fast_rz;
2698 break;
2699 case SH_ETH_REG_FAST_RCAR:
2700 reg_offset = sh_eth_offset_fast_rcar;
2701 break;
2702 case SH_ETH_REG_FAST_SH4:
2703 reg_offset = sh_eth_offset_fast_sh4;
2704 break;
2705 case SH_ETH_REG_FAST_SH3_SH2:
2706 reg_offset = sh_eth_offset_fast_sh3_sh2;
2707 break;
2708 default:
2709 break;
2710 }
2711
2712 return reg_offset;
2713 }
2714
2715 static const struct net_device_ops sh_eth_netdev_ops = {
2716 .ndo_open = sh_eth_open,
2717 .ndo_stop = sh_eth_close,
2718 .ndo_start_xmit = sh_eth_start_xmit,
2719 .ndo_get_stats = sh_eth_get_stats,
2720 .ndo_tx_timeout = sh_eth_tx_timeout,
2721 .ndo_do_ioctl = sh_eth_do_ioctl,
2722 .ndo_validate_addr = eth_validate_addr,
2723 .ndo_set_mac_address = eth_mac_addr,
2724 .ndo_change_mtu = eth_change_mtu,
2725 };
2726
2727 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2728 .ndo_open = sh_eth_open,
2729 .ndo_stop = sh_eth_close,
2730 .ndo_start_xmit = sh_eth_start_xmit,
2731 .ndo_get_stats = sh_eth_get_stats,
2732 .ndo_set_rx_mode = sh_eth_set_multicast_list,
2733 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2734 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2735 .ndo_tx_timeout = sh_eth_tx_timeout,
2736 .ndo_do_ioctl = sh_eth_do_ioctl,
2737 .ndo_validate_addr = eth_validate_addr,
2738 .ndo_set_mac_address = eth_mac_addr,
2739 .ndo_change_mtu = eth_change_mtu,
2740 };
2741
2742 #ifdef CONFIG_OF
sh_eth_parse_dt(struct device * dev)2743 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2744 {
2745 struct device_node *np = dev->of_node;
2746 struct sh_eth_plat_data *pdata;
2747 const char *mac_addr;
2748
2749 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2750 if (!pdata)
2751 return NULL;
2752
2753 pdata->phy_interface = of_get_phy_mode(np);
2754
2755 mac_addr = of_get_mac_address(np);
2756 if (mac_addr)
2757 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2758
2759 pdata->no_ether_link =
2760 of_property_read_bool(np, "renesas,no-ether-link");
2761 pdata->ether_link_active_low =
2762 of_property_read_bool(np, "renesas,ether-link-active-low");
2763
2764 return pdata;
2765 }
2766
2767 static const struct of_device_id sh_eth_match_table[] = {
2768 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2769 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2770 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2771 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2772 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
2773 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
2774 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2775 { }
2776 };
2777 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2778 #else
sh_eth_parse_dt(struct device * dev)2779 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2780 {
2781 return NULL;
2782 }
2783 #endif
2784
sh_eth_drv_probe(struct platform_device * pdev)2785 static int sh_eth_drv_probe(struct platform_device *pdev)
2786 {
2787 int ret, devno = 0;
2788 struct resource *res;
2789 struct net_device *ndev = NULL;
2790 struct sh_eth_private *mdp = NULL;
2791 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
2792 const struct platform_device_id *id = platform_get_device_id(pdev);
2793
2794 /* get base addr */
2795 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2796 if (unlikely(res == NULL)) {
2797 dev_err(&pdev->dev, "invalid resource\n");
2798 return -EINVAL;
2799 }
2800
2801 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2802 if (!ndev)
2803 return -ENOMEM;
2804
2805 pm_runtime_enable(&pdev->dev);
2806 pm_runtime_get_sync(&pdev->dev);
2807
2808 /* The sh Ether-specific entries in the device structure. */
2809 ndev->base_addr = res->start;
2810 devno = pdev->id;
2811 if (devno < 0)
2812 devno = 0;
2813
2814 ndev->dma = -1;
2815 ret = platform_get_irq(pdev, 0);
2816 if (ret < 0) {
2817 ret = -ENODEV;
2818 goto out_release;
2819 }
2820 ndev->irq = ret;
2821
2822 SET_NETDEV_DEV(ndev, &pdev->dev);
2823
2824 mdp = netdev_priv(ndev);
2825 mdp->num_tx_ring = TX_RING_SIZE;
2826 mdp->num_rx_ring = RX_RING_SIZE;
2827 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2828 if (IS_ERR(mdp->addr)) {
2829 ret = PTR_ERR(mdp->addr);
2830 goto out_release;
2831 }
2832
2833 spin_lock_init(&mdp->lock);
2834 mdp->pdev = pdev;
2835
2836 if (pdev->dev.of_node)
2837 pd = sh_eth_parse_dt(&pdev->dev);
2838 if (!pd) {
2839 dev_err(&pdev->dev, "no platform data\n");
2840 ret = -EINVAL;
2841 goto out_release;
2842 }
2843
2844 /* get PHY ID */
2845 mdp->phy_id = pd->phy;
2846 mdp->phy_interface = pd->phy_interface;
2847 /* EDMAC endian */
2848 mdp->edmac_endian = pd->edmac_endian;
2849 mdp->no_ether_link = pd->no_ether_link;
2850 mdp->ether_link_active_low = pd->ether_link_active_low;
2851
2852 /* set cpu data */
2853 if (id) {
2854 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
2855 } else {
2856 const struct of_device_id *match;
2857
2858 match = of_match_device(of_match_ptr(sh_eth_match_table),
2859 &pdev->dev);
2860 mdp->cd = (struct sh_eth_cpu_data *)match->data;
2861 }
2862 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
2863 if (!mdp->reg_offset) {
2864 dev_err(&pdev->dev, "Unknown register type (%d)\n",
2865 mdp->cd->register_type);
2866 ret = -EINVAL;
2867 goto out_release;
2868 }
2869 sh_eth_set_default_cpu_data(mdp->cd);
2870
2871 /* set function */
2872 if (mdp->cd->tsu)
2873 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
2874 else
2875 ndev->netdev_ops = &sh_eth_netdev_ops;
2876 ndev->ethtool_ops = &sh_eth_ethtool_ops;
2877 ndev->watchdog_timeo = TX_TIMEOUT;
2878
2879 /* debug message level */
2880 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
2881
2882 /* read and set MAC address */
2883 read_mac_address(ndev, pd->mac_addr);
2884 if (!is_valid_ether_addr(ndev->dev_addr)) {
2885 dev_warn(&pdev->dev,
2886 "no valid MAC address supplied, using a random one.\n");
2887 eth_hw_addr_random(ndev);
2888 }
2889
2890 /* ioremap the TSU registers */
2891 if (mdp->cd->tsu) {
2892 struct resource *rtsu;
2893
2894 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2895 if (!rtsu) {
2896 dev_err(&pdev->dev, "no TSU resource\n");
2897 ret = -ENODEV;
2898 goto out_release;
2899 }
2900 /* We can only request the TSU region for the first port
2901 * of the two sharing this TSU for the probe to succeed...
2902 */
2903 if (devno % 2 == 0 &&
2904 !devm_request_mem_region(&pdev->dev, rtsu->start,
2905 resource_size(rtsu),
2906 dev_name(&pdev->dev))) {
2907 dev_err(&pdev->dev, "can't request TSU resource.\n");
2908 ret = -EBUSY;
2909 goto out_release;
2910 }
2911 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start,
2912 resource_size(rtsu));
2913 if (!mdp->tsu_addr) {
2914 dev_err(&pdev->dev, "TSU region ioremap() failed.\n");
2915 ret = -ENOMEM;
2916 goto out_release;
2917 }
2918 mdp->port = devno % 2;
2919 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
2920 }
2921
2922 /* Need to init only the first port of the two sharing a TSU */
2923 if (devno % 2 == 0) {
2924 if (mdp->cd->chip_reset)
2925 mdp->cd->chip_reset(ndev);
2926
2927 if (mdp->cd->tsu) {
2928 /* TSU init (Init only)*/
2929 sh_eth_tsu_init(mdp);
2930 }
2931 }
2932
2933 /* MDIO bus init */
2934 ret = sh_mdio_init(mdp, pd);
2935 if (ret) {
2936 dev_err(&ndev->dev, "failed to initialise MDIO\n");
2937 goto out_release;
2938 }
2939
2940 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
2941
2942 /* network device register */
2943 ret = register_netdev(ndev);
2944 if (ret)
2945 goto out_napi_del;
2946
2947 /* print device information */
2948 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
2949 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2950
2951 pm_runtime_put(&pdev->dev);
2952 platform_set_drvdata(pdev, ndev);
2953
2954 return ret;
2955
2956 out_napi_del:
2957 netif_napi_del(&mdp->napi);
2958 sh_mdio_release(mdp);
2959
2960 out_release:
2961 /* net_dev free */
2962 if (ndev)
2963 free_netdev(ndev);
2964
2965 pm_runtime_put(&pdev->dev);
2966 pm_runtime_disable(&pdev->dev);
2967 return ret;
2968 }
2969
sh_eth_drv_remove(struct platform_device * pdev)2970 static int sh_eth_drv_remove(struct platform_device *pdev)
2971 {
2972 struct net_device *ndev = platform_get_drvdata(pdev);
2973 struct sh_eth_private *mdp = netdev_priv(ndev);
2974
2975 unregister_netdev(ndev);
2976 netif_napi_del(&mdp->napi);
2977 sh_mdio_release(mdp);
2978 pm_runtime_disable(&pdev->dev);
2979 free_netdev(ndev);
2980
2981 return 0;
2982 }
2983
2984 #ifdef CONFIG_PM
sh_eth_runtime_nop(struct device * dev)2985 static int sh_eth_runtime_nop(struct device *dev)
2986 {
2987 /* Runtime PM callback shared between ->runtime_suspend()
2988 * and ->runtime_resume(). Simply returns success.
2989 *
2990 * This driver re-initializes all registers after
2991 * pm_runtime_get_sync() anyway so there is no need
2992 * to save and restore registers here.
2993 */
2994 return 0;
2995 }
2996
2997 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
2998 .runtime_suspend = sh_eth_runtime_nop,
2999 .runtime_resume = sh_eth_runtime_nop,
3000 };
3001 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3002 #else
3003 #define SH_ETH_PM_OPS NULL
3004 #endif
3005
3006 static struct platform_device_id sh_eth_id_table[] = {
3007 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3008 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3009 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3010 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3011 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3012 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3013 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3014 { "r7s72100-ether", (kernel_ulong_t)&r7s72100_data },
3015 { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
3016 { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
3017 { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
3018 { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
3019 { "r8a7794-ether", (kernel_ulong_t)&r8a779x_data },
3020 { }
3021 };
3022 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3023
3024 static struct platform_driver sh_eth_driver = {
3025 .probe = sh_eth_drv_probe,
3026 .remove = sh_eth_drv_remove,
3027 .id_table = sh_eth_id_table,
3028 .driver = {
3029 .name = CARDNAME,
3030 .pm = SH_ETH_PM_OPS,
3031 .of_match_table = of_match_ptr(sh_eth_match_table),
3032 },
3033 };
3034
3035 module_platform_driver(sh_eth_driver);
3036
3037 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3038 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3039 MODULE_LICENSE("GPL v2");
3040