1 /*
2 * Broadcom BCM7xxx internal transceivers support.
3 *
4 * Copyright (C) 2014, Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12 #include <linux/module.h>
13 #include <linux/phy.h>
14 #include <linux/delay.h>
15 #include <linux/bitops.h>
16 #include <linux/brcmphy.h>
17 #include <linux/mdio.h>
18
19 /* Broadcom BCM7xxx internal PHY registers */
20 #define MII_BCM7XXX_CHANNEL_WIDTH 0x2000
21
22 /* 40nm only register definitions */
23 #define MII_BCM7XXX_100TX_AUX_CTL 0x10
24 #define MII_BCM7XXX_100TX_FALSE_CAR 0x13
25 #define MII_BCM7XXX_100TX_DISC 0x14
26 #define MII_BCM7XXX_AUX_MODE 0x1d
27 #define MII_BCM7XX_64CLK_MDIO BIT(12)
28 #define MII_BCM7XXX_CORE_BASE1E 0x1e
29 #define MII_BCM7XXX_TEST 0x1f
30 #define MII_BCM7XXX_SHD_MODE_2 BIT(2)
31
32 /* 28nm only register definitions */
33 #define MISC_ADDR(base, channel) base, channel
34
35 #define DSP_TAP10 MISC_ADDR(0x0a, 0)
36 #define PLL_PLLCTRL_1 MISC_ADDR(0x32, 1)
37 #define PLL_PLLCTRL_2 MISC_ADDR(0x32, 2)
38 #define PLL_PLLCTRL_4 MISC_ADDR(0x33, 0)
39
40 #define AFE_RXCONFIG_0 MISC_ADDR(0x38, 0)
41 #define AFE_RXCONFIG_1 MISC_ADDR(0x38, 1)
42 #define AFE_RX_LP_COUNTER MISC_ADDR(0x38, 3)
43 #define AFE_TX_CONFIG MISC_ADDR(0x39, 0)
44 #define AFE_HPF_TRIM_OTHERS MISC_ADDR(0x3a, 0)
45
46 #define CORE_EXPB0 0xb0
47
bcm7445_config_init(struct phy_device * phydev)48 static int bcm7445_config_init(struct phy_device *phydev)
49 {
50 int ret;
51 const struct bcm7445_regs {
52 int reg;
53 u16 value;
54 } bcm7445_regs_cfg[] = {
55 /* increases ADC latency by 24ns */
56 { MII_BCM54XX_EXP_SEL, 0x0038 },
57 { MII_BCM54XX_EXP_DATA, 0xAB95 },
58 /* increases internal 1V LDO voltage by 5% */
59 { MII_BCM54XX_EXP_SEL, 0x2038 },
60 { MII_BCM54XX_EXP_DATA, 0xBB22 },
61 /* reduce RX low pass filter corner frequency */
62 { MII_BCM54XX_EXP_SEL, 0x6038 },
63 { MII_BCM54XX_EXP_DATA, 0xFFC5 },
64 /* reduce RX high pass filter corner frequency */
65 { MII_BCM54XX_EXP_SEL, 0x003a },
66 { MII_BCM54XX_EXP_DATA, 0x2002 },
67 };
68 unsigned int i;
69
70 for (i = 0; i < ARRAY_SIZE(bcm7445_regs_cfg); i++) {
71 ret = phy_write(phydev,
72 bcm7445_regs_cfg[i].reg,
73 bcm7445_regs_cfg[i].value);
74 if (ret)
75 return ret;
76 }
77
78 return 0;
79 }
80
phy_write_exp(struct phy_device * phydev,u16 reg,u16 value)81 static void phy_write_exp(struct phy_device *phydev,
82 u16 reg, u16 value)
83 {
84 phy_write(phydev, MII_BCM54XX_EXP_SEL, MII_BCM54XX_EXP_SEL_ER | reg);
85 phy_write(phydev, MII_BCM54XX_EXP_DATA, value);
86 }
87
phy_write_misc(struct phy_device * phydev,u16 reg,u16 chl,u16 value)88 static void phy_write_misc(struct phy_device *phydev,
89 u16 reg, u16 chl, u16 value)
90 {
91 int tmp;
92
93 phy_write(phydev, MII_BCM54XX_AUX_CTL, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
94
95 tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL);
96 tmp |= MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA;
97 phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp);
98
99 tmp = (chl * MII_BCM7XXX_CHANNEL_WIDTH) | reg;
100 phy_write(phydev, MII_BCM54XX_EXP_SEL, tmp);
101
102 phy_write(phydev, MII_BCM54XX_EXP_DATA, value);
103 }
104
bcm7xxx_28nm_afe_config_init(struct phy_device * phydev)105 static int bcm7xxx_28nm_afe_config_init(struct phy_device *phydev)
106 {
107 /* Increase VCO range to prevent unlocking problem of PLL at low
108 * temp
109 */
110 phy_write_misc(phydev, PLL_PLLCTRL_1, 0x0048);
111
112 /* Change Ki to 011 */
113 phy_write_misc(phydev, PLL_PLLCTRL_2, 0x021b);
114
115 /* Disable loading of TVCO buffer to bandgap, set bandgap trim
116 * to 111
117 */
118 phy_write_misc(phydev, PLL_PLLCTRL_4, 0x0e20);
119
120 /* Adjust bias current trim by -3 */
121 phy_write_misc(phydev, DSP_TAP10, 0x690b);
122
123 /* Switch to CORE_BASE1E */
124 phy_write(phydev, MII_BCM7XXX_CORE_BASE1E, 0xd);
125
126 /* Reset R_CAL/RC_CAL Engine */
127 phy_write_exp(phydev, CORE_EXPB0, 0x0010);
128
129 /* Disable Reset R_CAL/RC_CAL Engine */
130 phy_write_exp(phydev, CORE_EXPB0, 0x0000);
131
132 /* write AFE_RXCONFIG_0 */
133 phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19);
134
135 /* write AFE_RXCONFIG_1 */
136 phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f);
137
138 /* write AFE_RX_LP_COUNTER */
139 phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
140
141 /* write AFE_HPF_TRIM_OTHERS */
142 phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b);
143
144 /* write AFTE_TX_CONFIG */
145 phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800);
146
147 return 0;
148 }
149
bcm7xxx_apd_enable(struct phy_device * phydev)150 static int bcm7xxx_apd_enable(struct phy_device *phydev)
151 {
152 int val;
153
154 /* Enable powering down of the DLL during auto-power down */
155 val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_SCR3);
156 if (val < 0)
157 return val;
158
159 val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
160 bcm54xx_shadow_write(phydev, BCM54XX_SHD_SCR3, val);
161
162 /* Enable auto-power down */
163 val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_APD);
164 if (val < 0)
165 return val;
166
167 val |= BCM54XX_SHD_APD_EN;
168 return bcm54xx_shadow_write(phydev, BCM54XX_SHD_APD, val);
169 }
170
bcm7xxx_eee_enable(struct phy_device * phydev)171 static int bcm7xxx_eee_enable(struct phy_device *phydev)
172 {
173 int val;
174
175 val = phy_read_mmd_indirect(phydev, BRCM_CL45VEN_EEE_CONTROL,
176 MDIO_MMD_AN, phydev->addr);
177 if (val < 0)
178 return val;
179
180 /* Enable general EEE feature at the PHY level */
181 val |= LPI_FEATURE_EN | LPI_FEATURE_EN_DIG1000X;
182
183 phy_write_mmd_indirect(phydev, BRCM_CL45VEN_EEE_CONTROL,
184 MDIO_MMD_AN, phydev->addr, val);
185
186 /* Advertise supported modes */
187 val = phy_read_mmd_indirect(phydev, MDIO_AN_EEE_ADV,
188 MDIO_MMD_AN, phydev->addr);
189
190 val |= (MDIO_AN_EEE_ADV_100TX | MDIO_AN_EEE_ADV_1000T);
191 phy_write_mmd_indirect(phydev, MDIO_AN_EEE_ADV,
192 MDIO_MMD_AN, phydev->addr, val);
193
194 return 0;
195 }
196
bcm7xxx_28nm_config_init(struct phy_device * phydev)197 static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
198 {
199 u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);
200 u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);
201 int ret = 0;
202
203 dev_info(&phydev->dev, "PHY revision: 0x%02x, patch: %d\n", rev, patch);
204
205 switch (rev) {
206 case 0xa0:
207 case 0xb0:
208 ret = bcm7445_config_init(phydev);
209 break;
210 default:
211 ret = bcm7xxx_28nm_afe_config_init(phydev);
212 break;
213 }
214
215 if (ret)
216 return ret;
217
218 ret = bcm7xxx_eee_enable(phydev);
219 if (ret)
220 return ret;
221
222 return bcm7xxx_apd_enable(phydev);
223 }
224
bcm7xxx_28nm_resume(struct phy_device * phydev)225 static int bcm7xxx_28nm_resume(struct phy_device *phydev)
226 {
227 int ret;
228
229 /* Re-apply workarounds coming out suspend/resume */
230 ret = bcm7xxx_28nm_config_init(phydev);
231 if (ret)
232 return ret;
233
234 /* 28nm Gigabit PHYs come out of reset without any half-duplex
235 * or "hub" compliant advertised mode, fix that. This does not
236 * cause any problems with the PHY library since genphy_config_aneg()
237 * gracefully handles auto-negotiated and forced modes.
238 */
239 return genphy_config_aneg(phydev);
240 }
241
phy_set_clr_bits(struct phy_device * dev,int location,int set_mask,int clr_mask)242 static int phy_set_clr_bits(struct phy_device *dev, int location,
243 int set_mask, int clr_mask)
244 {
245 int v, ret;
246
247 v = phy_read(dev, location);
248 if (v < 0)
249 return v;
250
251 v &= ~clr_mask;
252 v |= set_mask;
253
254 ret = phy_write(dev, location, v);
255 if (ret < 0)
256 return ret;
257
258 return v;
259 }
260
bcm7xxx_config_init(struct phy_device * phydev)261 static int bcm7xxx_config_init(struct phy_device *phydev)
262 {
263 int ret;
264
265 /* Enable 64 clock MDIO */
266 phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XX_64CLK_MDIO);
267 phy_read(phydev, MII_BCM7XXX_AUX_MODE);
268
269 /* Workaround only required for 100Mbits/sec capable PHYs */
270 if (phydev->supported & PHY_GBIT_FEATURES)
271 return 0;
272
273 /* set shadow mode 2 */
274 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
275 MII_BCM7XXX_SHD_MODE_2, MII_BCM7XXX_SHD_MODE_2);
276 if (ret < 0)
277 return ret;
278
279 /* set iddq_clkbias */
280 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00);
281 udelay(10);
282
283 /* reset iddq_clkbias */
284 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00);
285
286 phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555);
287
288 /* reset shadow mode 2 */
289 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, MII_BCM7XXX_SHD_MODE_2, 0);
290 if (ret < 0)
291 return ret;
292
293 return 0;
294 }
295
296 /* Workaround for putting the PHY in IDDQ mode, required
297 * for all BCM7XXX 40nm and 65nm PHYs
298 */
bcm7xxx_suspend(struct phy_device * phydev)299 static int bcm7xxx_suspend(struct phy_device *phydev)
300 {
301 int ret;
302 const struct bcm7xxx_regs {
303 int reg;
304 u16 value;
305 } bcm7xxx_suspend_cfg[] = {
306 { MII_BCM7XXX_TEST, 0x008b },
307 { MII_BCM7XXX_100TX_AUX_CTL, 0x01c0 },
308 { MII_BCM7XXX_100TX_DISC, 0x7000 },
309 { MII_BCM7XXX_TEST, 0x000f },
310 { MII_BCM7XXX_100TX_AUX_CTL, 0x20d0 },
311 { MII_BCM7XXX_TEST, 0x000b },
312 };
313 unsigned int i;
314
315 for (i = 0; i < ARRAY_SIZE(bcm7xxx_suspend_cfg); i++) {
316 ret = phy_write(phydev,
317 bcm7xxx_suspend_cfg[i].reg,
318 bcm7xxx_suspend_cfg[i].value);
319 if (ret)
320 return ret;
321 }
322
323 return 0;
324 }
325
bcm7xxx_dummy_config_init(struct phy_device * phydev)326 static int bcm7xxx_dummy_config_init(struct phy_device *phydev)
327 {
328 return 0;
329 }
330
331 #define BCM7XXX_28NM_GPHY(_oui, _name) \
332 { \
333 .phy_id = (_oui), \
334 .phy_id_mask = 0xfffffff0, \
335 .name = _name, \
336 .features = PHY_GBIT_FEATURES | \
337 SUPPORTED_Pause | SUPPORTED_Asym_Pause, \
338 .flags = PHY_IS_INTERNAL, \
339 .config_init = bcm7xxx_28nm_afe_config_init, \
340 .config_aneg = genphy_config_aneg, \
341 .read_status = genphy_read_status, \
342 .resume = bcm7xxx_28nm_resume, \
343 .driver = { .owner = THIS_MODULE }, \
344 }
345
346 static struct phy_driver bcm7xxx_driver[] = {
347 BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"),
348 BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"),
349 BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"),
350 BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"),
351 BCM7XXX_28NM_GPHY(PHY_ID_BCM7445, "Broadcom BCM7445"),
352 {
353 .phy_id = PHY_ID_BCM7425,
354 .phy_id_mask = 0xfffffff0,
355 .name = "Broadcom BCM7425",
356 .features = PHY_GBIT_FEATURES |
357 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
358 .flags = 0,
359 .config_init = bcm7xxx_config_init,
360 .config_aneg = genphy_config_aneg,
361 .read_status = genphy_read_status,
362 .suspend = bcm7xxx_suspend,
363 .resume = bcm7xxx_config_init,
364 .driver = { .owner = THIS_MODULE },
365 }, {
366 .phy_id = PHY_ID_BCM7429,
367 .phy_id_mask = 0xfffffff0,
368 .name = "Broadcom BCM7429",
369 .features = PHY_GBIT_FEATURES |
370 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
371 .flags = PHY_IS_INTERNAL,
372 .config_init = bcm7xxx_config_init,
373 .config_aneg = genphy_config_aneg,
374 .read_status = genphy_read_status,
375 .suspend = bcm7xxx_suspend,
376 .resume = bcm7xxx_config_init,
377 .driver = { .owner = THIS_MODULE },
378 }, {
379 .phy_id = PHY_BCM_OUI_4,
380 .phy_id_mask = 0xffff0000,
381 .name = "Broadcom BCM7XXX 40nm",
382 .features = PHY_GBIT_FEATURES |
383 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
384 .flags = PHY_IS_INTERNAL,
385 .config_init = bcm7xxx_config_init,
386 .config_aneg = genphy_config_aneg,
387 .read_status = genphy_read_status,
388 .suspend = bcm7xxx_suspend,
389 .resume = bcm7xxx_config_init,
390 .driver = { .owner = THIS_MODULE },
391 }, {
392 .phy_id = PHY_BCM_OUI_5,
393 .phy_id_mask = 0xffffff00,
394 .name = "Broadcom BCM7XXX 65nm",
395 .features = PHY_BASIC_FEATURES |
396 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
397 .flags = PHY_IS_INTERNAL,
398 .config_init = bcm7xxx_dummy_config_init,
399 .config_aneg = genphy_config_aneg,
400 .read_status = genphy_read_status,
401 .suspend = bcm7xxx_suspend,
402 .resume = bcm7xxx_config_init,
403 .driver = { .owner = THIS_MODULE },
404 } };
405
406 static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
407 { PHY_ID_BCM7250, 0xfffffff0, },
408 { PHY_ID_BCM7364, 0xfffffff0, },
409 { PHY_ID_BCM7366, 0xfffffff0, },
410 { PHY_ID_BCM7425, 0xfffffff0, },
411 { PHY_ID_BCM7429, 0xfffffff0, },
412 { PHY_ID_BCM7439, 0xfffffff0, },
413 { PHY_ID_BCM7445, 0xfffffff0, },
414 { PHY_BCM_OUI_4, 0xffff0000 },
415 { PHY_BCM_OUI_5, 0xffffff00 },
416 { }
417 };
418
bcm7xxx_phy_init(void)419 static int __init bcm7xxx_phy_init(void)
420 {
421 return phy_drivers_register(bcm7xxx_driver,
422 ARRAY_SIZE(bcm7xxx_driver));
423 }
424
bcm7xxx_phy_exit(void)425 static void __exit bcm7xxx_phy_exit(void)
426 {
427 phy_drivers_unregister(bcm7xxx_driver,
428 ARRAY_SIZE(bcm7xxx_driver));
429 }
430
431 module_init(bcm7xxx_phy_init);
432 module_exit(bcm7xxx_phy_exit);
433
434 MODULE_DEVICE_TABLE(mdio, bcm7xxx_tbl);
435
436 MODULE_DESCRIPTION("Broadcom BCM7xxx internal PHY driver");
437 MODULE_LICENSE("GPL");
438 MODULE_AUTHOR("Broadcom Corporation");
439