1 /*
2 * drivers/net/phy/national.c
3 *
4 * Driver for National Semiconductor PHYs
5 *
6 * Author: Stuart Menefy <stuart.menefy@st.com>
7 * Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
8 *
9 * Copyright (c) 2008 STMicroelectronics Limited
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/mii.h>
23 #include <linux/ethtool.h>
24 #include <linux/phy.h>
25 #include <linux/netdevice.h>
26
27 #define DEBUG
28
29 /* DP83865 phy identifier values */
30 #define DP83865_PHY_ID 0x20005c7a
31
32 #define DP83865_INT_STATUS 0x14
33 #define DP83865_INT_MASK 0x15
34 #define DP83865_INT_CLEAR 0x17
35
36 #define DP83865_INT_REMOTE_FAULT 0x0008
37 #define DP83865_INT_ANE_COMPLETED 0x0010
38 #define DP83865_INT_LINK_CHANGE 0xe000
39 #define DP83865_INT_MASK_DEFAULT (DP83865_INT_REMOTE_FAULT | \
40 DP83865_INT_ANE_COMPLETED | \
41 DP83865_INT_LINK_CHANGE)
42
43 /* Advanced proprietary configuration */
44 #define NS_EXP_MEM_CTL 0x16
45 #define NS_EXP_MEM_DATA 0x1d
46 #define NS_EXP_MEM_ADD 0x1e
47
48 #define LED_CTRL_REG 0x13
49 #define AN_FALLBACK_AN 0x0001
50 #define AN_FALLBACK_CRC 0x0002
51 #define AN_FALLBACK_IE 0x0004
52 #define ALL_FALLBACK_ON (AN_FALLBACK_AN | AN_FALLBACK_CRC | AN_FALLBACK_IE)
53
54 enum hdx_loopback {
55 hdx_loopback_on = 0,
56 hdx_loopback_off = 1,
57 };
58
ns_exp_read(struct phy_device * phydev,u16 reg)59 static u8 ns_exp_read(struct phy_device *phydev, u16 reg)
60 {
61 phy_write(phydev, NS_EXP_MEM_ADD, reg);
62 return phy_read(phydev, NS_EXP_MEM_DATA);
63 }
64
ns_exp_write(struct phy_device * phydev,u16 reg,u8 data)65 static void ns_exp_write(struct phy_device *phydev, u16 reg, u8 data)
66 {
67 phy_write(phydev, NS_EXP_MEM_ADD, reg);
68 phy_write(phydev, NS_EXP_MEM_DATA, data);
69 }
70
ns_config_intr(struct phy_device * phydev)71 static int ns_config_intr(struct phy_device *phydev)
72 {
73 int err;
74
75 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
76 err = phy_write(phydev, DP83865_INT_MASK,
77 DP83865_INT_MASK_DEFAULT);
78 else
79 err = phy_write(phydev, DP83865_INT_MASK, 0);
80
81 return err;
82 }
83
ns_ack_interrupt(struct phy_device * phydev)84 static int ns_ack_interrupt(struct phy_device *phydev)
85 {
86 int ret = phy_read(phydev, DP83865_INT_STATUS);
87 if (ret < 0)
88 return ret;
89
90 /* Clear the interrupt status bit by writing a “1”
91 * to the corresponding bit in INT_CLEAR (2:0 are reserved) */
92 ret = phy_write(phydev, DP83865_INT_CLEAR, ret & ~0x7);
93
94 return ret;
95 }
96
ns_giga_speed_fallback(struct phy_device * phydev,int mode)97 static void ns_giga_speed_fallback(struct phy_device *phydev, int mode)
98 {
99 int bmcr = phy_read(phydev, MII_BMCR);
100
101 phy_write(phydev, MII_BMCR, (bmcr | BMCR_PDOWN));
102
103 /* Enable 8 bit expended memory read/write (no auto increment) */
104 phy_write(phydev, NS_EXP_MEM_CTL, 0);
105 phy_write(phydev, NS_EXP_MEM_ADD, 0x1C0);
106 phy_write(phydev, NS_EXP_MEM_DATA, 0x0008);
107 phy_write(phydev, MII_BMCR, (bmcr & ~BMCR_PDOWN));
108 phy_write(phydev, LED_CTRL_REG, mode);
109 }
110
ns_10_base_t_hdx_loopack(struct phy_device * phydev,int disable)111 static void ns_10_base_t_hdx_loopack(struct phy_device *phydev, int disable)
112 {
113 if (disable)
114 ns_exp_write(phydev, 0x1c0, ns_exp_read(phydev, 0x1c0) | 1);
115 else
116 ns_exp_write(phydev, 0x1c0,
117 ns_exp_read(phydev, 0x1c0) & 0xfffe);
118
119 pr_debug("10BASE-T HDX loopback %s\n",
120 (ns_exp_read(phydev, 0x1c0) & 0x0001) ? "off" : "on");
121 }
122
ns_config_init(struct phy_device * phydev)123 static int ns_config_init(struct phy_device *phydev)
124 {
125 ns_giga_speed_fallback(phydev, ALL_FALLBACK_ON);
126 /* In the latest MAC or switches design, the 10 Mbps loopback
127 is desired to be turned off. */
128 ns_10_base_t_hdx_loopack(phydev, hdx_loopback_off);
129 return ns_ack_interrupt(phydev);
130 }
131
132 static struct phy_driver dp83865_driver = {
133 .phy_id = DP83865_PHY_ID,
134 .phy_id_mask = 0xfffffff0,
135 .name = "NatSemi DP83865",
136 .features = PHY_GBIT_FEATURES | SUPPORTED_Pause | SUPPORTED_Asym_Pause,
137 .flags = PHY_HAS_INTERRUPT,
138 .config_init = ns_config_init,
139 .config_aneg = genphy_config_aneg,
140 .read_status = genphy_read_status,
141 .ack_interrupt = ns_ack_interrupt,
142 .config_intr = ns_config_intr,
143 .driver = {.owner = THIS_MODULE,}
144 };
145
ns_init(void)146 static int __init ns_init(void)
147 {
148 return phy_driver_register(&dp83865_driver);
149 }
150
ns_exit(void)151 static void __exit ns_exit(void)
152 {
153 phy_driver_unregister(&dp83865_driver);
154 }
155
156 MODULE_DESCRIPTION("NatSemi PHY driver");
157 MODULE_AUTHOR("Stuart Menefy");
158 MODULE_LICENSE("GPL");
159
160 module_init(ns_init);
161 module_exit(ns_exit);
162
163 static struct mdio_device_id __maybe_unused ns_tbl[] = {
164 { DP83865_PHY_ID, 0xfffffff0 },
165 { }
166 };
167
168 MODULE_DEVICE_TABLE(mdio, ns_tbl);
169