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1 /*
2  * Goramo PCI200SYN synchronous serial card driver for Linux
3  *
4  * Copyright (C) 2002-2008 Krzysztof Halasa <khc@pm.waw.pl>
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of version 2 of the GNU General Public License
8  * as published by the Free Software Foundation.
9  *
10  * For information see <http://www.kernel.org/pub/linux/utils/net/hdlc/>
11  *
12  * Sources of information:
13  *    Hitachi HD64572 SCA-II User's Manual
14  *    PLX Technology Inc. PCI9052 Data Book
15  */
16 
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18 
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/capability.h>
22 #include <linux/slab.h>
23 #include <linux/types.h>
24 #include <linux/fcntl.h>
25 #include <linux/in.h>
26 #include <linux/string.h>
27 #include <linux/errno.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/moduleparam.h>
31 #include <linux/netdevice.h>
32 #include <linux/hdlc.h>
33 #include <linux/pci.h>
34 #include <linux/delay.h>
35 #include <asm/io.h>
36 
37 #include "hd64572.h"
38 
39 #undef DEBUG_PKT
40 #define DEBUG_RINGS
41 
42 #define PCI200SYN_PLX_SIZE	0x80	/* PLX control window size (128b) */
43 #define PCI200SYN_SCA_SIZE	0x400	/* SCA window size (1Kb) */
44 #define MAX_TX_BUFFERS		10
45 
46 static int pci_clock_freq = 33000000;
47 #define CLOCK_BASE pci_clock_freq
48 
49 /*
50  *      PLX PCI9052 local configuration and shared runtime registers.
51  *      This structure can be used to access 9052 registers (memory mapped).
52  */
53 typedef struct {
54 	u32 loc_addr_range[4];	/* 00-0Ch : Local Address Ranges */
55 	u32 loc_rom_range;	/* 10h : Local ROM Range */
56 	u32 loc_addr_base[4];	/* 14-20h : Local Address Base Addrs */
57 	u32 loc_rom_base;	/* 24h : Local ROM Base */
58 	u32 loc_bus_descr[4];	/* 28-34h : Local Bus Descriptors */
59 	u32 rom_bus_descr;	/* 38h : ROM Bus Descriptor */
60 	u32 cs_base[4];		/* 3C-48h : Chip Select Base Addrs */
61 	u32 intr_ctrl_stat;	/* 4Ch : Interrupt Control/Status */
62 	u32 init_ctrl;		/* 50h : EEPROM ctrl, Init Ctrl, etc */
63 }plx9052;
64 
65 
66 
67 typedef struct port_s {
68 	struct napi_struct napi;
69 	struct net_device *netdev;
70 	struct card_s *card;
71 	spinlock_t lock;	/* TX lock */
72 	sync_serial_settings settings;
73 	int rxpart;		/* partial frame received, next frame invalid*/
74 	unsigned short encoding;
75 	unsigned short parity;
76 	u16 rxin;		/* rx ring buffer 'in' pointer */
77 	u16 txin;		/* tx ring buffer 'in' and 'last' pointers */
78 	u16 txlast;
79 	u8 rxs, txs, tmc;	/* SCA registers */
80 	u8 chan;		/* physical port # - 0 or 1 */
81 }port_t;
82 
83 
84 
85 typedef struct card_s {
86 	u8 __iomem *rambase;	/* buffer memory base (virtual) */
87 	u8 __iomem *scabase;	/* SCA memory base (virtual) */
88 	plx9052 __iomem *plxbase;/* PLX registers memory base (virtual) */
89 	u16 rx_ring_buffers;	/* number of buffers in a ring */
90 	u16 tx_ring_buffers;
91 	u16 buff_offset;	/* offset of first buffer of first channel */
92 	u8 irq;			/* interrupt request level */
93 
94 	port_t ports[2];
95 }card_t;
96 
97 
98 #define get_port(card, port)	     (&card->ports[port])
99 #define sca_flush(card)		     (sca_in(IER0, card));
100 
new_memcpy_toio(char __iomem * dest,char * src,int length)101 static inline void new_memcpy_toio(char __iomem *dest, char *src, int length)
102 {
103 	int len;
104 	do {
105 		len = length > 256 ? 256 : length;
106 		memcpy_toio(dest, src, len);
107 		dest += len;
108 		src += len;
109 		length -= len;
110 		readb(dest);
111 	} while (len);
112 }
113 
114 #undef memcpy_toio
115 #define memcpy_toio new_memcpy_toio
116 
117 #include "hd64572.c"
118 
119 
pci200_set_iface(port_t * port)120 static void pci200_set_iface(port_t *port)
121 {
122 	card_t *card = port->card;
123 	u16 msci = get_msci(port);
124 	u8 rxs = port->rxs & CLK_BRG_MASK;
125 	u8 txs = port->txs & CLK_BRG_MASK;
126 
127 	sca_out(EXS_TES1, (port->chan ? MSCI1_OFFSET : MSCI0_OFFSET) + EXS,
128 		port->card);
129 	switch(port->settings.clock_type) {
130 	case CLOCK_INT:
131 		rxs |= CLK_BRG; /* BRG output */
132 		txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
133 		break;
134 
135 	case CLOCK_TXINT:
136 		rxs |= CLK_LINE; /* RXC input */
137 		txs |= CLK_PIN_OUT | CLK_BRG; /* BRG output */
138 		break;
139 
140 	case CLOCK_TXFROMRX:
141 		rxs |= CLK_LINE; /* RXC input */
142 		txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
143 		break;
144 
145 	default:		/* EXTernal clock */
146 		rxs |= CLK_LINE; /* RXC input */
147 		txs |= CLK_PIN_OUT | CLK_LINE; /* TXC input */
148 		break;
149 	}
150 
151 	port->rxs = rxs;
152 	port->txs = txs;
153 	sca_out(rxs, msci + RXS, card);
154 	sca_out(txs, msci + TXS, card);
155 	sca_set_port(port);
156 }
157 
158 
159 
pci200_open(struct net_device * dev)160 static int pci200_open(struct net_device *dev)
161 {
162 	port_t *port = dev_to_port(dev);
163 
164 	int result = hdlc_open(dev);
165 	if (result)
166 		return result;
167 
168 	sca_open(dev);
169 	pci200_set_iface(port);
170 	sca_flush(port->card);
171 	return 0;
172 }
173 
174 
175 
pci200_close(struct net_device * dev)176 static int pci200_close(struct net_device *dev)
177 {
178 	sca_close(dev);
179 	sca_flush(dev_to_port(dev)->card);
180 	hdlc_close(dev);
181 	return 0;
182 }
183 
184 
185 
pci200_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)186 static int pci200_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
187 {
188 	const size_t size = sizeof(sync_serial_settings);
189 	sync_serial_settings new_line;
190 	sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
191 	port_t *port = dev_to_port(dev);
192 
193 #ifdef DEBUG_RINGS
194 	if (cmd == SIOCDEVPRIVATE) {
195 		sca_dump_rings(dev);
196 		return 0;
197 	}
198 #endif
199 	if (cmd != SIOCWANDEV)
200 		return hdlc_ioctl(dev, ifr, cmd);
201 
202 	switch(ifr->ifr_settings.type) {
203 	case IF_GET_IFACE:
204 		ifr->ifr_settings.type = IF_IFACE_V35;
205 		if (ifr->ifr_settings.size < size) {
206 			ifr->ifr_settings.size = size; /* data size wanted */
207 			return -ENOBUFS;
208 		}
209 		if (copy_to_user(line, &port->settings, size))
210 			return -EFAULT;
211 		return 0;
212 
213 	case IF_IFACE_V35:
214 	case IF_IFACE_SYNC_SERIAL:
215 		if (!capable(CAP_NET_ADMIN))
216 			return -EPERM;
217 
218 		if (copy_from_user(&new_line, line, size))
219 			return -EFAULT;
220 
221 		if (new_line.clock_type != CLOCK_EXT &&
222 		    new_line.clock_type != CLOCK_TXFROMRX &&
223 		    new_line.clock_type != CLOCK_INT &&
224 		    new_line.clock_type != CLOCK_TXINT)
225 			return -EINVAL;	/* No such clock setting */
226 
227 		if (new_line.loopback != 0 && new_line.loopback != 1)
228 			return -EINVAL;
229 
230 		memcpy(&port->settings, &new_line, size); /* Update settings */
231 		pci200_set_iface(port);
232 		sca_flush(port->card);
233 		return 0;
234 
235 	default:
236 		return hdlc_ioctl(dev, ifr, cmd);
237 	}
238 }
239 
240 
241 
pci200_pci_remove_one(struct pci_dev * pdev)242 static void pci200_pci_remove_one(struct pci_dev *pdev)
243 {
244 	int i;
245 	card_t *card = pci_get_drvdata(pdev);
246 
247 	for (i = 0; i < 2; i++)
248 		if (card->ports[i].card)
249 			unregister_hdlc_device(card->ports[i].netdev);
250 
251 	if (card->irq)
252 		free_irq(card->irq, card);
253 
254 	if (card->rambase)
255 		iounmap(card->rambase);
256 	if (card->scabase)
257 		iounmap(card->scabase);
258 	if (card->plxbase)
259 		iounmap(card->plxbase);
260 
261 	pci_release_regions(pdev);
262 	pci_disable_device(pdev);
263 	if (card->ports[0].netdev)
264 		free_netdev(card->ports[0].netdev);
265 	if (card->ports[1].netdev)
266 		free_netdev(card->ports[1].netdev);
267 	kfree(card);
268 }
269 
270 static const struct net_device_ops pci200_ops = {
271 	.ndo_open       = pci200_open,
272 	.ndo_stop       = pci200_close,
273 	.ndo_change_mtu = hdlc_change_mtu,
274 	.ndo_start_xmit = hdlc_start_xmit,
275 	.ndo_do_ioctl   = pci200_ioctl,
276 };
277 
pci200_pci_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)278 static int pci200_pci_init_one(struct pci_dev *pdev,
279 			       const struct pci_device_id *ent)
280 {
281 	card_t *card;
282 	u32 __iomem *p;
283 	int i;
284 	u32 ramsize;
285 	u32 ramphys;		/* buffer memory base */
286 	u32 scaphys;		/* SCA memory base */
287 	u32 plxphys;		/* PLX registers memory base */
288 
289 	i = pci_enable_device(pdev);
290 	if (i)
291 		return i;
292 
293 	i = pci_request_regions(pdev, "PCI200SYN");
294 	if (i) {
295 		pci_disable_device(pdev);
296 		return i;
297 	}
298 
299 	card = kzalloc(sizeof(card_t), GFP_KERNEL);
300 	if (card == NULL) {
301 		pci_release_regions(pdev);
302 		pci_disable_device(pdev);
303 		return -ENOBUFS;
304 	}
305 	pci_set_drvdata(pdev, card);
306 	card->ports[0].netdev = alloc_hdlcdev(&card->ports[0]);
307 	card->ports[1].netdev = alloc_hdlcdev(&card->ports[1]);
308 	if (!card->ports[0].netdev || !card->ports[1].netdev) {
309 		pr_err("unable to allocate memory\n");
310 		pci200_pci_remove_one(pdev);
311 		return -ENOMEM;
312 	}
313 
314 	if (pci_resource_len(pdev, 0) != PCI200SYN_PLX_SIZE ||
315 	    pci_resource_len(pdev, 2) != PCI200SYN_SCA_SIZE ||
316 	    pci_resource_len(pdev, 3) < 16384) {
317 		pr_err("invalid card EEPROM parameters\n");
318 		pci200_pci_remove_one(pdev);
319 		return -EFAULT;
320 	}
321 
322 	plxphys = pci_resource_start(pdev,0) & PCI_BASE_ADDRESS_MEM_MASK;
323 	card->plxbase = ioremap(plxphys, PCI200SYN_PLX_SIZE);
324 
325 	scaphys = pci_resource_start(pdev,2) & PCI_BASE_ADDRESS_MEM_MASK;
326 	card->scabase = ioremap(scaphys, PCI200SYN_SCA_SIZE);
327 
328 	ramphys = pci_resource_start(pdev,3) & PCI_BASE_ADDRESS_MEM_MASK;
329 	card->rambase = pci_ioremap_bar(pdev, 3);
330 
331 	if (card->plxbase == NULL ||
332 	    card->scabase == NULL ||
333 	    card->rambase == NULL) {
334 		pr_err("ioremap() failed\n");
335 		pci200_pci_remove_one(pdev);
336 		return -EFAULT;
337 	}
338 
339 	/* Reset PLX */
340 	p = &card->plxbase->init_ctrl;
341 	writel(readl(p) | 0x40000000, p);
342 	readl(p);		/* Flush the write - do not use sca_flush */
343 	udelay(1);
344 
345 	writel(readl(p) & ~0x40000000, p);
346 	readl(p);		/* Flush the write - do not use sca_flush */
347 	udelay(1);
348 
349 	ramsize = sca_detect_ram(card, card->rambase,
350 				 pci_resource_len(pdev, 3));
351 
352 	/* number of TX + RX buffers for one port - this is dual port card */
353 	i = ramsize / (2 * (sizeof(pkt_desc) + HDLC_MAX_MRU));
354 	card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS);
355 	card->rx_ring_buffers = i - card->tx_ring_buffers;
356 
357 	card->buff_offset = 2 * sizeof(pkt_desc) * (card->tx_ring_buffers +
358 						    card->rx_ring_buffers);
359 
360 	pr_info("%u KB RAM at 0x%x, IRQ%u, using %u TX + %u RX packets rings\n",
361 		ramsize / 1024, ramphys,
362 		pdev->irq, card->tx_ring_buffers, card->rx_ring_buffers);
363 
364 	if (card->tx_ring_buffers < 1) {
365 		pr_err("RAM test failed\n");
366 		pci200_pci_remove_one(pdev);
367 		return -EFAULT;
368 	}
369 
370 	/* Enable interrupts on the PCI bridge */
371 	p = &card->plxbase->intr_ctrl_stat;
372 	writew(readw(p) | 0x0040, p);
373 
374 	/* Allocate IRQ */
375 	if (request_irq(pdev->irq, sca_intr, IRQF_SHARED, "pci200syn", card)) {
376 		pr_warn("could not allocate IRQ%d\n", pdev->irq);
377 		pci200_pci_remove_one(pdev);
378 		return -EBUSY;
379 	}
380 	card->irq = pdev->irq;
381 
382 	sca_init(card, 0);
383 
384 	for (i = 0; i < 2; i++) {
385 		port_t *port = &card->ports[i];
386 		struct net_device *dev = port->netdev;
387 		hdlc_device *hdlc = dev_to_hdlc(dev);
388 		port->chan = i;
389 
390 		spin_lock_init(&port->lock);
391 		dev->irq = card->irq;
392 		dev->mem_start = ramphys;
393 		dev->mem_end = ramphys + ramsize - 1;
394 		dev->tx_queue_len = 50;
395 		dev->netdev_ops = &pci200_ops;
396 		hdlc->attach = sca_attach;
397 		hdlc->xmit = sca_xmit;
398 		port->settings.clock_type = CLOCK_EXT;
399 		port->card = card;
400 		sca_init_port(port);
401 		if (register_hdlc_device(dev)) {
402 			pr_err("unable to register hdlc device\n");
403 			port->card = NULL;
404 			pci200_pci_remove_one(pdev);
405 			return -ENOBUFS;
406 		}
407 
408 		netdev_info(dev, "PCI200SYN channel %d\n", port->chan);
409 	}
410 
411 	sca_flush(card);
412 	return 0;
413 }
414 
415 
416 
417 static const struct pci_device_id pci200_pci_tbl[] = {
418 	{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, PCI_VENDOR_ID_PLX,
419 	  PCI_DEVICE_ID_PLX_PCI200SYN, 0, 0, 0 },
420 	{ 0, }
421 };
422 
423 
424 static struct pci_driver pci200_pci_driver = {
425 	.name		= "PCI200SYN",
426 	.id_table	= pci200_pci_tbl,
427 	.probe		= pci200_pci_init_one,
428 	.remove		= pci200_pci_remove_one,
429 };
430 
431 
pci200_init_module(void)432 static int __init pci200_init_module(void)
433 {
434 	if (pci_clock_freq < 1000000 || pci_clock_freq > 80000000) {
435 		pr_err("Invalid PCI clock frequency\n");
436 		return -EINVAL;
437 	}
438 	return pci_register_driver(&pci200_pci_driver);
439 }
440 
441 
442 
pci200_cleanup_module(void)443 static void __exit pci200_cleanup_module(void)
444 {
445 	pci_unregister_driver(&pci200_pci_driver);
446 }
447 
448 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
449 MODULE_DESCRIPTION("Goramo PCI200SYN serial port driver");
450 MODULE_LICENSE("GPL v2");
451 MODULE_DEVICE_TABLE(pci, pci200_pci_tbl);
452 module_param(pci_clock_freq, int, 0444);
453 MODULE_PARM_DESC(pci_clock_freq, "System PCI clock frequency in Hz");
454 module_init(pci200_init_module);
455 module_exit(pci200_cleanup_module);
456