1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
23 * USA
24 *
25 * The full GNU General Public License is included in this distribution
26 * in the file called COPYING.
27 *
28 * Contact Information:
29 * Intel Linux Wireless <ilw@linux.intel.com>
30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 *
32 * BSD LICENSE
33 *
34 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
35 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
36 * All rights reserved.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 *
42 * * Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * * Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in
46 * the documentation and/or other materials provided with the
47 * distribution.
48 * * Neither the name Intel Corporation nor the names of its
49 * contributors may be used to endorse or promote products derived
50 * from this software without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *
64 *****************************************************************************/
65 #include <linux/pci.h>
66 #include <linux/pci-aspm.h>
67 #include <linux/interrupt.h>
68 #include <linux/debugfs.h>
69 #include <linux/sched.h>
70 #include <linux/bitops.h>
71 #include <linux/gfp.h>
72 #include <linux/vmalloc.h>
73
74 #include "iwl-drv.h"
75 #include "iwl-trans.h"
76 #include "iwl-csr.h"
77 #include "iwl-prph.h"
78 #include "iwl-agn-hw.h"
79 #include "iwl-fw-error-dump.h"
80 #include "internal.h"
81
82 /* extended range in FW SRAM */
83 #define IWL_FW_MEM_EXTENDED_START 0x40000
84 #define IWL_FW_MEM_EXTENDED_END 0x57FFF
85
iwl_pcie_free_fw_monitor(struct iwl_trans * trans)86 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
87 {
88 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
89
90 if (!trans_pcie->fw_mon_page)
91 return;
92
93 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
94 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
95 __free_pages(trans_pcie->fw_mon_page,
96 get_order(trans_pcie->fw_mon_size));
97 trans_pcie->fw_mon_page = NULL;
98 trans_pcie->fw_mon_phys = 0;
99 trans_pcie->fw_mon_size = 0;
100 }
101
iwl_pcie_alloc_fw_monitor(struct iwl_trans * trans)102 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans)
103 {
104 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
105 struct page *page = NULL;
106 dma_addr_t phys;
107 u32 size;
108 u8 power;
109
110 if (trans_pcie->fw_mon_page) {
111 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
112 trans_pcie->fw_mon_size,
113 DMA_FROM_DEVICE);
114 return;
115 }
116
117 phys = 0;
118 for (power = 26; power >= 11; power--) {
119 int order;
120
121 size = BIT(power);
122 order = get_order(size);
123 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
124 order);
125 if (!page)
126 continue;
127
128 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
129 DMA_FROM_DEVICE);
130 if (dma_mapping_error(trans->dev, phys)) {
131 __free_pages(page, order);
132 page = NULL;
133 continue;
134 }
135 IWL_INFO(trans,
136 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
137 size, order);
138 break;
139 }
140
141 if (!page)
142 return;
143
144 trans_pcie->fw_mon_page = page;
145 trans_pcie->fw_mon_phys = phys;
146 trans_pcie->fw_mon_size = size;
147 }
148
iwl_trans_pcie_read_shr(struct iwl_trans * trans,u32 reg)149 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
150 {
151 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
152 ((reg & 0x0000ffff) | (2 << 28)));
153 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
154 }
155
iwl_trans_pcie_write_shr(struct iwl_trans * trans,u32 reg,u32 val)156 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
157 {
158 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
159 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
160 ((reg & 0x0000ffff) | (3 << 28)));
161 }
162
iwl_pcie_set_pwr(struct iwl_trans * trans,bool vaux)163 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
164 {
165 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
166 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
167 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
168 ~APMG_PS_CTRL_MSK_PWR_SRC);
169 else
170 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
171 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
172 ~APMG_PS_CTRL_MSK_PWR_SRC);
173 }
174
175 /* PCI registers */
176 #define PCI_CFG_RETRY_TIMEOUT 0x041
177
iwl_pcie_apm_config(struct iwl_trans * trans)178 static void iwl_pcie_apm_config(struct iwl_trans *trans)
179 {
180 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
181 u16 lctl;
182 u16 cap;
183
184 /*
185 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
186 * Check if BIOS (or OS) enabled L1-ASPM on this device.
187 * If so (likely), disable L0S, so device moves directly L0->L1;
188 * costs negligible amount of power savings.
189 * If not (unlikely), enable L0S, so there is at least some
190 * power savings, even without L1.
191 */
192 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
193 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
194 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
195 else
196 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
197 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
198
199 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
200 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
201 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
202 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
203 trans->ltr_enabled ? "En" : "Dis");
204 }
205
206 /*
207 * Start up NIC's basic functionality after it has been reset
208 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
209 * NOTE: This does not load uCode nor start the embedded processor
210 */
iwl_pcie_apm_init(struct iwl_trans * trans)211 static int iwl_pcie_apm_init(struct iwl_trans *trans)
212 {
213 int ret = 0;
214 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
215
216 /*
217 * Use "set_bit" below rather than "write", to preserve any hardware
218 * bits already set by default after reset.
219 */
220
221 /* Disable L0S exit timer (platform NMI Work/Around) */
222 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
223 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
224 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
225
226 /*
227 * Disable L0s without affecting L1;
228 * don't wait for ICH L0s (ICH bug W/A)
229 */
230 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
231 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
232
233 /* Set FH wait threshold to maximum (HW error during stress W/A) */
234 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
235
236 /*
237 * Enable HAP INTA (interrupt from management bus) to
238 * wake device's PCI Express link L1a -> L0s
239 */
240 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
241 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
242
243 iwl_pcie_apm_config(trans);
244
245 /* Configure analog phase-lock-loop before activating to D0A */
246 if (trans->cfg->base_params->pll_cfg_val)
247 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
248 trans->cfg->base_params->pll_cfg_val);
249
250 /*
251 * Set "initialization complete" bit to move adapter from
252 * D0U* --> D0A* (powered-up active) state.
253 */
254 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
255
256 /*
257 * Wait for clock stabilization; once stabilized, access to
258 * device-internal resources is supported, e.g. iwl_write_prph()
259 * and accesses to uCode SRAM.
260 */
261 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
262 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
263 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
264 if (ret < 0) {
265 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
266 goto out;
267 }
268
269 if (trans->cfg->host_interrupt_operation_mode) {
270 /*
271 * This is a bit of an abuse - This is needed for 7260 / 3160
272 * only check host_interrupt_operation_mode even if this is
273 * not related to host_interrupt_operation_mode.
274 *
275 * Enable the oscillator to count wake up time for L1 exit. This
276 * consumes slightly more power (100uA) - but allows to be sure
277 * that we wake up from L1 on time.
278 *
279 * This looks weird: read twice the same register, discard the
280 * value, set a bit, and yet again, read that same register
281 * just to discard the value. But that's the way the hardware
282 * seems to like it.
283 */
284 iwl_read_prph(trans, OSC_CLK);
285 iwl_read_prph(trans, OSC_CLK);
286 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
287 iwl_read_prph(trans, OSC_CLK);
288 iwl_read_prph(trans, OSC_CLK);
289 }
290
291 /*
292 * Enable DMA clock and wait for it to stabilize.
293 *
294 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
295 * bits do not disable clocks. This preserves any hardware
296 * bits already set by default in "CLK_CTRL_REG" after reset.
297 */
298 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
299 iwl_write_prph(trans, APMG_CLK_EN_REG,
300 APMG_CLK_VAL_DMA_CLK_RQT);
301 udelay(20);
302
303 /* Disable L1-Active */
304 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
305 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
306
307 /* Clear the interrupt in APMG if the NIC is in RFKILL */
308 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
309 APMG_RTC_INT_STT_RFKILL);
310 }
311
312 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
313
314 out:
315 return ret;
316 }
317
318 /*
319 * Enable LP XTAL to avoid HW bug where device may consume much power if
320 * FW is not loaded after device reset. LP XTAL is disabled by default
321 * after device HW reset. Do it only if XTAL is fed by internal source.
322 * Configure device's "persistence" mode to avoid resetting XTAL again when
323 * SHRD_HW_RST occurs in S3.
324 */
iwl_pcie_apm_lp_xtal_enable(struct iwl_trans * trans)325 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
326 {
327 int ret;
328 u32 apmg_gp1_reg;
329 u32 apmg_xtal_cfg_reg;
330 u32 dl_cfg_reg;
331
332 /* Force XTAL ON */
333 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
334 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
335
336 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
337 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
338
339 udelay(10);
340
341 /*
342 * Set "initialization complete" bit to move adapter from
343 * D0U* --> D0A* (powered-up active) state.
344 */
345 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
346
347 /*
348 * Wait for clock stabilization; once stabilized, access to
349 * device-internal resources is possible.
350 */
351 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
352 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
353 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
354 25000);
355 if (WARN_ON(ret < 0)) {
356 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
357 /* Release XTAL ON request */
358 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
359 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
360 return;
361 }
362
363 /*
364 * Clear "disable persistence" to avoid LP XTAL resetting when
365 * SHRD_HW_RST is applied in S3.
366 */
367 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
368 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
369
370 /*
371 * Force APMG XTAL to be active to prevent its disabling by HW
372 * caused by APMG idle state.
373 */
374 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
375 SHR_APMG_XTAL_CFG_REG);
376 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
377 apmg_xtal_cfg_reg |
378 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
379
380 /*
381 * Reset entire device again - do controller reset (results in
382 * SHRD_HW_RST). Turn MAC off before proceeding.
383 */
384 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
385
386 udelay(10);
387
388 /* Enable LP XTAL by indirect access through CSR */
389 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
390 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
391 SHR_APMG_GP1_WF_XTAL_LP_EN |
392 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
393
394 /* Clear delay line clock power up */
395 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
396 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
397 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
398
399 /*
400 * Enable persistence mode to avoid LP XTAL resetting when
401 * SHRD_HW_RST is applied in S3.
402 */
403 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
404 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
405
406 /*
407 * Clear "initialization complete" bit to move adapter from
408 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
409 */
410 iwl_clear_bit(trans, CSR_GP_CNTRL,
411 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
412
413 /* Activates XTAL resources monitor */
414 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
415 CSR_MONITOR_XTAL_RESOURCES);
416
417 /* Release XTAL ON request */
418 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
419 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
420 udelay(10);
421
422 /* Release APMG XTAL */
423 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
424 apmg_xtal_cfg_reg &
425 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
426 }
427
iwl_pcie_apm_stop_master(struct iwl_trans * trans)428 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
429 {
430 int ret = 0;
431
432 /* stop device's busmaster DMA activity */
433 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
434
435 ret = iwl_poll_bit(trans, CSR_RESET,
436 CSR_RESET_REG_FLAG_MASTER_DISABLED,
437 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
438 if (ret < 0)
439 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
440
441 IWL_DEBUG_INFO(trans, "stop master\n");
442
443 return ret;
444 }
445
iwl_pcie_apm_stop(struct iwl_trans * trans)446 static void iwl_pcie_apm_stop(struct iwl_trans *trans)
447 {
448 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
449
450 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
451
452 /* Stop device's DMA activity */
453 iwl_pcie_apm_stop_master(trans);
454
455 if (trans->cfg->lp_xtal_workaround) {
456 iwl_pcie_apm_lp_xtal_enable(trans);
457 return;
458 }
459
460 /* Reset the entire device */
461 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
462
463 udelay(10);
464
465 /*
466 * Clear "initialization complete" bit to move adapter from
467 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
468 */
469 iwl_clear_bit(trans, CSR_GP_CNTRL,
470 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
471 }
472
iwl_pcie_nic_init(struct iwl_trans * trans)473 static int iwl_pcie_nic_init(struct iwl_trans *trans)
474 {
475 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
476
477 /* nic_init */
478 spin_lock(&trans_pcie->irq_lock);
479 iwl_pcie_apm_init(trans);
480
481 spin_unlock(&trans_pcie->irq_lock);
482
483 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
484 iwl_pcie_set_pwr(trans, false);
485
486 iwl_op_mode_nic_config(trans->op_mode);
487
488 /* Allocate the RX queue, or reset if it is already allocated */
489 iwl_pcie_rx_init(trans);
490
491 /* Allocate or reset and init all Tx and Command queues */
492 if (iwl_pcie_tx_init(trans))
493 return -ENOMEM;
494
495 if (trans->cfg->base_params->shadow_reg_enable) {
496 /* enable shadow regs in HW */
497 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
498 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
499 }
500
501 return 0;
502 }
503
504 #define HW_READY_TIMEOUT (50)
505
506 /* Note: returns poll_bit return value, which is >= 0 if success */
iwl_pcie_set_hw_ready(struct iwl_trans * trans)507 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
508 {
509 int ret;
510
511 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
512 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
513
514 /* See if we got it */
515 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
516 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
517 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
518 HW_READY_TIMEOUT);
519
520 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
521 return ret;
522 }
523
524 /* Note: returns standard 0/-ERROR code */
iwl_pcie_prepare_card_hw(struct iwl_trans * trans)525 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
526 {
527 int ret;
528 int t = 0;
529 int iter;
530
531 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
532
533 ret = iwl_pcie_set_hw_ready(trans);
534 /* If the card is ready, exit 0 */
535 if (ret >= 0)
536 return 0;
537
538 for (iter = 0; iter < 10; iter++) {
539 /* If HW is not ready, prepare the conditions to check again */
540 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
541 CSR_HW_IF_CONFIG_REG_PREPARE);
542
543 do {
544 ret = iwl_pcie_set_hw_ready(trans);
545 if (ret >= 0)
546 return 0;
547
548 usleep_range(200, 1000);
549 t += 200;
550 } while (t < 150000);
551 msleep(25);
552 }
553
554 IWL_ERR(trans, "Couldn't prepare the card\n");
555
556 return ret;
557 }
558
559 /*
560 * ucode
561 */
iwl_pcie_load_firmware_chunk(struct iwl_trans * trans,u32 dst_addr,dma_addr_t phy_addr,u32 byte_cnt)562 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
563 dma_addr_t phy_addr, u32 byte_cnt)
564 {
565 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
566 int ret;
567
568 trans_pcie->ucode_write_complete = false;
569
570 iwl_write_direct32(trans,
571 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
572 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
573
574 iwl_write_direct32(trans,
575 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
576 dst_addr);
577
578 iwl_write_direct32(trans,
579 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
580 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
581
582 iwl_write_direct32(trans,
583 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
584 (iwl_get_dma_hi_addr(phy_addr)
585 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
586
587 iwl_write_direct32(trans,
588 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
589 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
590 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
591 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
592
593 iwl_write_direct32(trans,
594 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
595 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
596 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
597 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
598
599 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
600 trans_pcie->ucode_write_complete, 5 * HZ);
601 if (!ret) {
602 IWL_ERR(trans, "Failed to load firmware chunk!\n");
603 return -ETIMEDOUT;
604 }
605
606 return 0;
607 }
608
iwl_pcie_load_section(struct iwl_trans * trans,u8 section_num,const struct fw_desc * section)609 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
610 const struct fw_desc *section)
611 {
612 u8 *v_addr;
613 dma_addr_t p_addr;
614 u32 offset, chunk_sz = section->len;
615 int ret = 0;
616
617 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
618 section_num);
619
620 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
621 GFP_KERNEL | __GFP_NOWARN);
622 if (!v_addr) {
623 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
624 chunk_sz = PAGE_SIZE;
625 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
626 &p_addr, GFP_KERNEL);
627 if (!v_addr)
628 return -ENOMEM;
629 }
630
631 for (offset = 0; offset < section->len; offset += chunk_sz) {
632 u32 copy_size, dst_addr;
633 bool extended_addr = false;
634
635 copy_size = min_t(u32, chunk_sz, section->len - offset);
636 dst_addr = section->offset + offset;
637
638 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
639 dst_addr <= IWL_FW_MEM_EXTENDED_END)
640 extended_addr = true;
641
642 if (extended_addr)
643 iwl_set_bits_prph(trans, LMPM_CHICK,
644 LMPM_CHICK_EXTENDED_ADDR_SPACE);
645
646 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
647 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
648 copy_size);
649
650 if (extended_addr)
651 iwl_clear_bits_prph(trans, LMPM_CHICK,
652 LMPM_CHICK_EXTENDED_ADDR_SPACE);
653
654 if (ret) {
655 IWL_ERR(trans,
656 "Could not load the [%d] uCode section\n",
657 section_num);
658 break;
659 }
660 }
661
662 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
663 return ret;
664 }
665
iwl_pcie_load_cpu_secured_sections(struct iwl_trans * trans,const struct fw_img * image,int cpu,int * first_ucode_section)666 static int iwl_pcie_load_cpu_secured_sections(struct iwl_trans *trans,
667 const struct fw_img *image,
668 int cpu,
669 int *first_ucode_section)
670 {
671 int shift_param;
672 int i, ret = 0;
673 u32 last_read_idx = 0;
674
675 if (cpu == 1) {
676 shift_param = 0;
677 *first_ucode_section = 0;
678 } else {
679 shift_param = 16;
680 (*first_ucode_section)++;
681 }
682
683 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
684 last_read_idx = i;
685
686 if (!image->sec[i].data ||
687 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
688 IWL_DEBUG_FW(trans,
689 "Break since Data not valid or Empty section, sec = %d\n",
690 i);
691 break;
692 }
693
694 if (i == (*first_ucode_section) + 1)
695 /* set CPU to started */
696 iwl_set_bits_prph(trans,
697 CSR_UCODE_LOAD_STATUS_ADDR,
698 LMPM_CPU_HDRS_LOADING_COMPLETED
699 << shift_param);
700
701 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
702 if (ret)
703 return ret;
704 }
705 /* image loading complete */
706 iwl_set_bits_prph(trans,
707 CSR_UCODE_LOAD_STATUS_ADDR,
708 LMPM_CPU_UCODE_LOADING_COMPLETED << shift_param);
709
710 *first_ucode_section = last_read_idx;
711
712 return 0;
713 }
714
iwl_pcie_load_cpu_sections(struct iwl_trans * trans,const struct fw_img * image,int cpu,int * first_ucode_section)715 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
716 const struct fw_img *image,
717 int cpu,
718 int *first_ucode_section)
719 {
720 int shift_param;
721 int i, ret = 0;
722 u32 last_read_idx = 0;
723
724 if (cpu == 1) {
725 shift_param = 0;
726 *first_ucode_section = 0;
727 } else {
728 shift_param = 16;
729 (*first_ucode_section)++;
730 }
731
732 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
733 last_read_idx = i;
734
735 if (!image->sec[i].data ||
736 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
737 IWL_DEBUG_FW(trans,
738 "Break since Data not valid or Empty section, sec = %d\n",
739 i);
740 break;
741 }
742
743 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
744 if (ret)
745 return ret;
746 }
747
748 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
749 iwl_set_bits_prph(trans,
750 CSR_UCODE_LOAD_STATUS_ADDR,
751 (LMPM_CPU_UCODE_LOADING_COMPLETED |
752 LMPM_CPU_HDRS_LOADING_COMPLETED |
753 LMPM_CPU_UCODE_LOADING_STARTED) <<
754 shift_param);
755
756 *first_ucode_section = last_read_idx;
757
758 return 0;
759 }
760
iwl_pcie_load_given_ucode(struct iwl_trans * trans,const struct fw_img * image)761 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
762 const struct fw_img *image)
763 {
764 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
765 int ret = 0;
766 int first_ucode_section;
767
768 IWL_DEBUG_FW(trans,
769 "working with %s image\n",
770 image->is_secure ? "Secured" : "Non Secured");
771 IWL_DEBUG_FW(trans,
772 "working with %s CPU\n",
773 image->is_dual_cpus ? "Dual" : "Single");
774
775 /* configure the ucode to be ready to get the secured image */
776 if (image->is_secure) {
777 /* set secure boot inspector addresses */
778 iwl_write_prph(trans,
779 LMPM_SECURE_INSPECTOR_CODE_ADDR,
780 LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE);
781
782 iwl_write_prph(trans,
783 LMPM_SECURE_INSPECTOR_DATA_ADDR,
784 LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE);
785
786 /* set CPU1 header address */
787 iwl_write_prph(trans,
788 LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR,
789 LMPM_SECURE_CPU1_HDR_MEM_SPACE);
790
791 /* load to FW the binary Secured sections of CPU1 */
792 ret = iwl_pcie_load_cpu_secured_sections(trans, image, 1,
793 &first_ucode_section);
794 if (ret)
795 return ret;
796
797 } else {
798 /* load to FW the binary Non secured sections of CPU1 */
799 ret = iwl_pcie_load_cpu_sections(trans, image, 1,
800 &first_ucode_section);
801 if (ret)
802 return ret;
803 }
804
805 if (image->is_dual_cpus) {
806 /* set CPU2 header address */
807 iwl_write_prph(trans,
808 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
809 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
810
811 /* load to FW the binary sections of CPU2 */
812 if (image->is_secure)
813 ret = iwl_pcie_load_cpu_secured_sections(
814 trans, image, 2,
815 &first_ucode_section);
816 else
817 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
818 &first_ucode_section);
819 if (ret)
820 return ret;
821 }
822
823 /* supported for 7000 only for the moment */
824 if (iwlwifi_mod_params.fw_monitor &&
825 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
826 iwl_pcie_alloc_fw_monitor(trans);
827
828 if (trans_pcie->fw_mon_size) {
829 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
830 trans_pcie->fw_mon_phys >> 4);
831 iwl_write_prph(trans, MON_BUFF_END_ADDR,
832 (trans_pcie->fw_mon_phys +
833 trans_pcie->fw_mon_size) >> 4);
834 }
835 }
836
837 /* release CPU reset */
838 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
839 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
840 else
841 iwl_write32(trans, CSR_RESET, 0);
842
843 if (image->is_secure) {
844 /* wait for image verification to complete */
845 ret = iwl_poll_prph_bit(trans,
846 LMPM_SECURE_BOOT_CPU1_STATUS_ADDR,
847 LMPM_SECURE_BOOT_STATUS_SUCCESS,
848 LMPM_SECURE_BOOT_STATUS_SUCCESS,
849 LMPM_SECURE_TIME_OUT);
850
851 if (ret < 0) {
852 IWL_ERR(trans, "Time out on secure boot process\n");
853 return ret;
854 }
855 }
856
857 return 0;
858 }
859
iwl_trans_pcie_start_fw(struct iwl_trans * trans,const struct fw_img * fw,bool run_in_rfkill)860 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
861 const struct fw_img *fw, bool run_in_rfkill)
862 {
863 int ret;
864 bool hw_rfkill;
865
866 /* This may fail if AMT took ownership of the device */
867 if (iwl_pcie_prepare_card_hw(trans)) {
868 IWL_WARN(trans, "Exit HW not ready\n");
869 return -EIO;
870 }
871
872 iwl_enable_rfkill_int(trans);
873
874 /* If platform's RF_KILL switch is NOT set to KILL */
875 hw_rfkill = iwl_is_rfkill_set(trans);
876 if (hw_rfkill)
877 set_bit(STATUS_RFKILL, &trans->status);
878 else
879 clear_bit(STATUS_RFKILL, &trans->status);
880 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
881 if (hw_rfkill && !run_in_rfkill)
882 return -ERFKILL;
883
884 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
885
886 ret = iwl_pcie_nic_init(trans);
887 if (ret) {
888 IWL_ERR(trans, "Unable to init nic\n");
889 return ret;
890 }
891
892 /* make sure rfkill handshake bits are cleared */
893 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
894 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
895 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
896
897 /* clear (again), then enable host interrupts */
898 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
899 iwl_enable_interrupts(trans);
900
901 /* really make sure rfkill handshake bits are cleared */
902 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
903 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
904
905 /* Load the given image to the HW */
906 return iwl_pcie_load_given_ucode(trans, fw);
907 }
908
iwl_trans_pcie_fw_alive(struct iwl_trans * trans,u32 scd_addr)909 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
910 {
911 iwl_pcie_reset_ict(trans);
912 iwl_pcie_tx_start(trans, scd_addr);
913 }
914
iwl_trans_pcie_stop_device(struct iwl_trans * trans)915 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
916 {
917 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
918 bool hw_rfkill, was_hw_rfkill;
919
920 was_hw_rfkill = iwl_is_rfkill_set(trans);
921
922 /* tell the device to stop sending interrupts */
923 spin_lock(&trans_pcie->irq_lock);
924 iwl_disable_interrupts(trans);
925 spin_unlock(&trans_pcie->irq_lock);
926
927 /* device going down, Stop using ICT table */
928 iwl_pcie_disable_ict(trans);
929
930 /*
931 * If a HW restart happens during firmware loading,
932 * then the firmware loading might call this function
933 * and later it might be called again due to the
934 * restart. So don't process again if the device is
935 * already dead.
936 */
937 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
938 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
939 iwl_pcie_tx_stop(trans);
940 iwl_pcie_rx_stop(trans);
941
942 /* Power-down device's busmaster DMA clocks */
943 iwl_write_prph(trans, APMG_CLK_DIS_REG,
944 APMG_CLK_VAL_DMA_CLK_RQT);
945 udelay(5);
946 }
947
948 /* Make sure (redundant) we've released our request to stay awake */
949 iwl_clear_bit(trans, CSR_GP_CNTRL,
950 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
951
952 /* Stop the device, and put it in low power state */
953 iwl_pcie_apm_stop(trans);
954
955 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
956 * Clean again the interrupt here
957 */
958 spin_lock(&trans_pcie->irq_lock);
959 iwl_disable_interrupts(trans);
960 spin_unlock(&trans_pcie->irq_lock);
961
962 /* stop and reset the on-board processor */
963 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
964
965 /* clear all status bits */
966 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
967 clear_bit(STATUS_INT_ENABLED, &trans->status);
968 clear_bit(STATUS_TPOWER_PMI, &trans->status);
969 clear_bit(STATUS_RFKILL, &trans->status);
970
971 /*
972 * Even if we stop the HW, we still want the RF kill
973 * interrupt
974 */
975 iwl_enable_rfkill_int(trans);
976
977 /*
978 * Check again since the RF kill state may have changed while
979 * all the interrupts were disabled, in this case we couldn't
980 * receive the RF kill interrupt and update the state in the
981 * op_mode.
982 * Don't call the op_mode if the rkfill state hasn't changed.
983 * This allows the op_mode to call stop_device from the rfkill
984 * notification without endless recursion. Under very rare
985 * circumstances, we might have a small recursion if the rfkill
986 * state changed exactly now while we were called from stop_device.
987 * This is very unlikely but can happen and is supported.
988 */
989 hw_rfkill = iwl_is_rfkill_set(trans);
990 if (hw_rfkill)
991 set_bit(STATUS_RFKILL, &trans->status);
992 else
993 clear_bit(STATUS_RFKILL, &trans->status);
994 if (hw_rfkill != was_hw_rfkill)
995 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
996 }
997
iwl_trans_pcie_rf_kill(struct iwl_trans * trans,bool state)998 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
999 {
1000 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
1001 iwl_trans_pcie_stop_device(trans);
1002 }
1003
iwl_trans_pcie_d3_suspend(struct iwl_trans * trans,bool test)1004 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
1005 {
1006 iwl_disable_interrupts(trans);
1007
1008 /*
1009 * in testing mode, the host stays awake and the
1010 * hardware won't be reset (not even partially)
1011 */
1012 if (test)
1013 return;
1014
1015 iwl_pcie_disable_ict(trans);
1016
1017 iwl_clear_bit(trans, CSR_GP_CNTRL,
1018 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1019 iwl_clear_bit(trans, CSR_GP_CNTRL,
1020 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1021
1022 /*
1023 * reset TX queues -- some of their registers reset during S3
1024 * so if we don't reset everything here the D3 image would try
1025 * to execute some invalid memory upon resume
1026 */
1027 iwl_trans_pcie_tx_reset(trans);
1028
1029 iwl_pcie_set_pwr(trans, true);
1030 }
1031
iwl_trans_pcie_d3_resume(struct iwl_trans * trans,enum iwl_d3_status * status,bool test)1032 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1033 enum iwl_d3_status *status,
1034 bool test)
1035 {
1036 u32 val;
1037 int ret;
1038
1039 if (test) {
1040 iwl_enable_interrupts(trans);
1041 *status = IWL_D3_STATUS_ALIVE;
1042 return 0;
1043 }
1044
1045 iwl_pcie_set_pwr(trans, false);
1046
1047 val = iwl_read32(trans, CSR_RESET);
1048 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) {
1049 *status = IWL_D3_STATUS_RESET;
1050 return 0;
1051 }
1052
1053 /*
1054 * Also enables interrupts - none will happen as the device doesn't
1055 * know we're waking it up, only when the opmode actually tells it
1056 * after this call.
1057 */
1058 iwl_pcie_reset_ict(trans);
1059
1060 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1061 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1062
1063 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1064 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1065 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1066 25000);
1067 if (ret < 0) {
1068 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1069 return ret;
1070 }
1071
1072 iwl_trans_pcie_tx_reset(trans);
1073
1074 ret = iwl_pcie_rx_init(trans);
1075 if (ret) {
1076 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
1077 return ret;
1078 }
1079
1080 *status = IWL_D3_STATUS_ALIVE;
1081 return 0;
1082 }
1083
iwl_trans_pcie_start_hw(struct iwl_trans * trans)1084 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1085 {
1086 bool hw_rfkill;
1087 int err;
1088
1089 err = iwl_pcie_prepare_card_hw(trans);
1090 if (err) {
1091 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1092 return err;
1093 }
1094
1095 /* Reset the entire device */
1096 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1097
1098 usleep_range(10, 15);
1099
1100 iwl_pcie_apm_init(trans);
1101
1102 /* From now on, the op_mode will be kept updated about RF kill state */
1103 iwl_enable_rfkill_int(trans);
1104
1105 hw_rfkill = iwl_is_rfkill_set(trans);
1106 if (hw_rfkill)
1107 set_bit(STATUS_RFKILL, &trans->status);
1108 else
1109 clear_bit(STATUS_RFKILL, &trans->status);
1110 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1111
1112 return 0;
1113 }
1114
iwl_trans_pcie_op_mode_leave(struct iwl_trans * trans)1115 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1116 {
1117 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1118
1119 /* disable interrupts - don't enable HW RF kill interrupt */
1120 spin_lock(&trans_pcie->irq_lock);
1121 iwl_disable_interrupts(trans);
1122 spin_unlock(&trans_pcie->irq_lock);
1123
1124 iwl_pcie_apm_stop(trans);
1125
1126 spin_lock(&trans_pcie->irq_lock);
1127 iwl_disable_interrupts(trans);
1128 spin_unlock(&trans_pcie->irq_lock);
1129
1130 iwl_pcie_disable_ict(trans);
1131 }
1132
iwl_trans_pcie_write8(struct iwl_trans * trans,u32 ofs,u8 val)1133 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1134 {
1135 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1136 }
1137
iwl_trans_pcie_write32(struct iwl_trans * trans,u32 ofs,u32 val)1138 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1139 {
1140 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1141 }
1142
iwl_trans_pcie_read32(struct iwl_trans * trans,u32 ofs)1143 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1144 {
1145 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1146 }
1147
iwl_trans_pcie_read_prph(struct iwl_trans * trans,u32 reg)1148 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1149 {
1150 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1151 ((reg & 0x000FFFFF) | (3 << 24)));
1152 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1153 }
1154
iwl_trans_pcie_write_prph(struct iwl_trans * trans,u32 addr,u32 val)1155 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1156 u32 val)
1157 {
1158 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1159 ((addr & 0x000FFFFF) | (3 << 24)));
1160 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1161 }
1162
iwl_pcie_dummy_napi_poll(struct napi_struct * napi,int budget)1163 static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1164 {
1165 WARN_ON(1);
1166 return 0;
1167 }
1168
iwl_trans_pcie_configure(struct iwl_trans * trans,const struct iwl_trans_config * trans_cfg)1169 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1170 const struct iwl_trans_config *trans_cfg)
1171 {
1172 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1173
1174 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1175 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1176 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1177 trans_pcie->n_no_reclaim_cmds = 0;
1178 else
1179 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1180 if (trans_pcie->n_no_reclaim_cmds)
1181 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1182 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1183
1184 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1185 if (trans_pcie->rx_buf_size_8k)
1186 trans_pcie->rx_page_order = get_order(8 * 1024);
1187 else
1188 trans_pcie->rx_page_order = get_order(4 * 1024);
1189
1190 trans_pcie->wd_timeout =
1191 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
1192
1193 trans_pcie->command_names = trans_cfg->command_names;
1194 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1195 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1196
1197 /* Initialize NAPI here - it should be before registering to mac80211
1198 * in the opmode but after the HW struct is allocated.
1199 * As this function may be called again in some corner cases don't
1200 * do anything if NAPI was already initialized.
1201 */
1202 if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) {
1203 init_dummy_netdev(&trans_pcie->napi_dev);
1204 iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi,
1205 &trans_pcie->napi_dev,
1206 iwl_pcie_dummy_napi_poll, 64);
1207 }
1208 }
1209
iwl_trans_pcie_free(struct iwl_trans * trans)1210 void iwl_trans_pcie_free(struct iwl_trans *trans)
1211 {
1212 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1213
1214 synchronize_irq(trans_pcie->pci_dev->irq);
1215
1216 iwl_pcie_tx_free(trans);
1217 iwl_pcie_rx_free(trans);
1218
1219 free_irq(trans_pcie->pci_dev->irq, trans);
1220 iwl_pcie_free_ict(trans);
1221
1222 pci_disable_msi(trans_pcie->pci_dev);
1223 iounmap(trans_pcie->hw_base);
1224 pci_release_regions(trans_pcie->pci_dev);
1225 pci_disable_device(trans_pcie->pci_dev);
1226 kmem_cache_destroy(trans->dev_cmd_pool);
1227
1228 if (trans_pcie->napi.poll)
1229 netif_napi_del(&trans_pcie->napi);
1230
1231 iwl_pcie_free_fw_monitor(trans);
1232
1233 kfree(trans);
1234 }
1235
iwl_trans_pcie_set_pmi(struct iwl_trans * trans,bool state)1236 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1237 {
1238 if (state)
1239 set_bit(STATUS_TPOWER_PMI, &trans->status);
1240 else
1241 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1242 }
1243
iwl_trans_pcie_grab_nic_access(struct iwl_trans * trans,bool silent,unsigned long * flags)1244 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1245 unsigned long *flags)
1246 {
1247 int ret;
1248 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1249
1250 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1251
1252 if (trans_pcie->cmd_in_flight)
1253 goto out;
1254
1255 /* this bit wakes up the NIC */
1256 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1257 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1258
1259 /*
1260 * These bits say the device is running, and should keep running for
1261 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1262 * but they do not indicate that embedded SRAM is restored yet;
1263 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1264 * to/from host DRAM when sleeping/waking for power-saving.
1265 * Each direction takes approximately 1/4 millisecond; with this
1266 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1267 * series of register accesses are expected (e.g. reading Event Log),
1268 * to keep device from sleeping.
1269 *
1270 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1271 * SRAM is okay/restored. We don't check that here because this call
1272 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1273 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1274 *
1275 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1276 * and do not save/restore SRAM when power cycling.
1277 */
1278 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1279 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1280 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1281 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1282 if (unlikely(ret < 0)) {
1283 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1284 if (!silent) {
1285 u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1286 WARN_ONCE(1,
1287 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1288 val);
1289 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1290 return false;
1291 }
1292 }
1293
1294 out:
1295 /*
1296 * Fool sparse by faking we release the lock - sparse will
1297 * track nic_access anyway.
1298 */
1299 __release(&trans_pcie->reg_lock);
1300 return true;
1301 }
1302
iwl_trans_pcie_release_nic_access(struct iwl_trans * trans,unsigned long * flags)1303 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1304 unsigned long *flags)
1305 {
1306 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1307
1308 lockdep_assert_held(&trans_pcie->reg_lock);
1309
1310 /*
1311 * Fool sparse by faking we acquiring the lock - sparse will
1312 * track nic_access anyway.
1313 */
1314 __acquire(&trans_pcie->reg_lock);
1315
1316 if (trans_pcie->cmd_in_flight)
1317 goto out;
1318
1319 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1320 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1321 /*
1322 * Above we read the CSR_GP_CNTRL register, which will flush
1323 * any previous writes, but we need the write that clears the
1324 * MAC_ACCESS_REQ bit to be performed before any other writes
1325 * scheduled on different CPUs (after we drop reg_lock).
1326 */
1327 mmiowb();
1328 out:
1329 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1330 }
1331
iwl_trans_pcie_read_mem(struct iwl_trans * trans,u32 addr,void * buf,int dwords)1332 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1333 void *buf, int dwords)
1334 {
1335 unsigned long flags;
1336 int offs, ret = 0;
1337 u32 *vals = buf;
1338
1339 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1340 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1341 for (offs = 0; offs < dwords; offs++)
1342 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1343 iwl_trans_release_nic_access(trans, &flags);
1344 } else {
1345 ret = -EBUSY;
1346 }
1347 return ret;
1348 }
1349
iwl_trans_pcie_write_mem(struct iwl_trans * trans,u32 addr,const void * buf,int dwords)1350 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1351 const void *buf, int dwords)
1352 {
1353 unsigned long flags;
1354 int offs, ret = 0;
1355 const u32 *vals = buf;
1356
1357 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1358 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1359 for (offs = 0; offs < dwords; offs++)
1360 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1361 vals ? vals[offs] : 0);
1362 iwl_trans_release_nic_access(trans, &flags);
1363 } else {
1364 ret = -EBUSY;
1365 }
1366 return ret;
1367 }
1368
1369 #define IWL_FLUSH_WAIT_MS 2000
1370
iwl_trans_pcie_wait_txq_empty(struct iwl_trans * trans,u32 txq_bm)1371 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
1372 {
1373 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1374 struct iwl_txq *txq;
1375 struct iwl_queue *q;
1376 int cnt;
1377 unsigned long now = jiffies;
1378 u32 scd_sram_addr;
1379 u8 buf[16];
1380 int ret = 0;
1381
1382 /* waiting for all the tx frames complete might take a while */
1383 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1384 u8 wr_ptr;
1385
1386 if (cnt == trans_pcie->cmd_queue)
1387 continue;
1388 if (!test_bit(cnt, trans_pcie->queue_used))
1389 continue;
1390 if (!(BIT(cnt) & txq_bm))
1391 continue;
1392
1393 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
1394 txq = &trans_pcie->txq[cnt];
1395 q = &txq->q;
1396 wr_ptr = ACCESS_ONCE(q->write_ptr);
1397
1398 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1399 !time_after(jiffies,
1400 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1401 u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1402
1403 if (WARN_ONCE(wr_ptr != write_ptr,
1404 "WR pointer moved while flushing %d -> %d\n",
1405 wr_ptr, write_ptr))
1406 return -ETIMEDOUT;
1407 msleep(1);
1408 }
1409
1410 if (q->read_ptr != q->write_ptr) {
1411 IWL_ERR(trans,
1412 "fail to flush all tx fifo queues Q %d\n", cnt);
1413 ret = -ETIMEDOUT;
1414 break;
1415 }
1416 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
1417 }
1418
1419 if (!ret)
1420 return 0;
1421
1422 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1423 txq->q.read_ptr, txq->q.write_ptr);
1424
1425 scd_sram_addr = trans_pcie->scd_base_addr +
1426 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1427 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1428
1429 iwl_print_hex_error(trans, buf, sizeof(buf));
1430
1431 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1432 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1433 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1434
1435 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1436 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1437 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1438 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1439 u32 tbl_dw =
1440 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1441 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1442
1443 if (cnt & 0x1)
1444 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1445 else
1446 tbl_dw = tbl_dw & 0x0000FFFF;
1447
1448 IWL_ERR(trans,
1449 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1450 cnt, active ? "" : "in", fifo, tbl_dw,
1451 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1452 (TFD_QUEUE_SIZE_MAX - 1),
1453 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1454 }
1455
1456 return ret;
1457 }
1458
iwl_trans_pcie_set_bits_mask(struct iwl_trans * trans,u32 reg,u32 mask,u32 value)1459 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1460 u32 mask, u32 value)
1461 {
1462 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1463 unsigned long flags;
1464
1465 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1466 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1467 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1468 }
1469
get_csr_string(int cmd)1470 static const char *get_csr_string(int cmd)
1471 {
1472 #define IWL_CMD(x) case x: return #x
1473 switch (cmd) {
1474 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1475 IWL_CMD(CSR_INT_COALESCING);
1476 IWL_CMD(CSR_INT);
1477 IWL_CMD(CSR_INT_MASK);
1478 IWL_CMD(CSR_FH_INT_STATUS);
1479 IWL_CMD(CSR_GPIO_IN);
1480 IWL_CMD(CSR_RESET);
1481 IWL_CMD(CSR_GP_CNTRL);
1482 IWL_CMD(CSR_HW_REV);
1483 IWL_CMD(CSR_EEPROM_REG);
1484 IWL_CMD(CSR_EEPROM_GP);
1485 IWL_CMD(CSR_OTP_GP_REG);
1486 IWL_CMD(CSR_GIO_REG);
1487 IWL_CMD(CSR_GP_UCODE_REG);
1488 IWL_CMD(CSR_GP_DRIVER_REG);
1489 IWL_CMD(CSR_UCODE_DRV_GP1);
1490 IWL_CMD(CSR_UCODE_DRV_GP2);
1491 IWL_CMD(CSR_LED_REG);
1492 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1493 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1494 IWL_CMD(CSR_ANA_PLL_CFG);
1495 IWL_CMD(CSR_HW_REV_WA_REG);
1496 IWL_CMD(CSR_MONITOR_STATUS_REG);
1497 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1498 default:
1499 return "UNKNOWN";
1500 }
1501 #undef IWL_CMD
1502 }
1503
iwl_pcie_dump_csr(struct iwl_trans * trans)1504 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1505 {
1506 int i;
1507 static const u32 csr_tbl[] = {
1508 CSR_HW_IF_CONFIG_REG,
1509 CSR_INT_COALESCING,
1510 CSR_INT,
1511 CSR_INT_MASK,
1512 CSR_FH_INT_STATUS,
1513 CSR_GPIO_IN,
1514 CSR_RESET,
1515 CSR_GP_CNTRL,
1516 CSR_HW_REV,
1517 CSR_EEPROM_REG,
1518 CSR_EEPROM_GP,
1519 CSR_OTP_GP_REG,
1520 CSR_GIO_REG,
1521 CSR_GP_UCODE_REG,
1522 CSR_GP_DRIVER_REG,
1523 CSR_UCODE_DRV_GP1,
1524 CSR_UCODE_DRV_GP2,
1525 CSR_LED_REG,
1526 CSR_DRAM_INT_TBL_REG,
1527 CSR_GIO_CHICKEN_BITS,
1528 CSR_ANA_PLL_CFG,
1529 CSR_MONITOR_STATUS_REG,
1530 CSR_HW_REV_WA_REG,
1531 CSR_DBG_HPET_MEM_REG
1532 };
1533 IWL_ERR(trans, "CSR values:\n");
1534 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1535 "CSR_INT_PERIODIC_REG)\n");
1536 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1537 IWL_ERR(trans, " %25s: 0X%08x\n",
1538 get_csr_string(csr_tbl[i]),
1539 iwl_read32(trans, csr_tbl[i]));
1540 }
1541 }
1542
1543 #ifdef CONFIG_IWLWIFI_DEBUGFS
1544 /* create and remove of files */
1545 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1546 if (!debugfs_create_file(#name, mode, parent, trans, \
1547 &iwl_dbgfs_##name##_ops)) \
1548 goto err; \
1549 } while (0)
1550
1551 /* file operation */
1552 #define DEBUGFS_READ_FILE_OPS(name) \
1553 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1554 .read = iwl_dbgfs_##name##_read, \
1555 .open = simple_open, \
1556 .llseek = generic_file_llseek, \
1557 };
1558
1559 #define DEBUGFS_WRITE_FILE_OPS(name) \
1560 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1561 .write = iwl_dbgfs_##name##_write, \
1562 .open = simple_open, \
1563 .llseek = generic_file_llseek, \
1564 };
1565
1566 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1567 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1568 .write = iwl_dbgfs_##name##_write, \
1569 .read = iwl_dbgfs_##name##_read, \
1570 .open = simple_open, \
1571 .llseek = generic_file_llseek, \
1572 };
1573
iwl_dbgfs_tx_queue_read(struct file * file,char __user * user_buf,size_t count,loff_t * ppos)1574 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1575 char __user *user_buf,
1576 size_t count, loff_t *ppos)
1577 {
1578 struct iwl_trans *trans = file->private_data;
1579 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1580 struct iwl_txq *txq;
1581 struct iwl_queue *q;
1582 char *buf;
1583 int pos = 0;
1584 int cnt;
1585 int ret;
1586 size_t bufsz;
1587
1588 bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1589
1590 if (!trans_pcie->txq)
1591 return -EAGAIN;
1592
1593 buf = kzalloc(bufsz, GFP_KERNEL);
1594 if (!buf)
1595 return -ENOMEM;
1596
1597 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1598 txq = &trans_pcie->txq[cnt];
1599 q = &txq->q;
1600 pos += scnprintf(buf + pos, bufsz - pos,
1601 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d%s\n",
1602 cnt, q->read_ptr, q->write_ptr,
1603 !!test_bit(cnt, trans_pcie->queue_used),
1604 !!test_bit(cnt, trans_pcie->queue_stopped),
1605 txq->need_update,
1606 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
1607 }
1608 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1609 kfree(buf);
1610 return ret;
1611 }
1612
iwl_dbgfs_rx_queue_read(struct file * file,char __user * user_buf,size_t count,loff_t * ppos)1613 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1614 char __user *user_buf,
1615 size_t count, loff_t *ppos)
1616 {
1617 struct iwl_trans *trans = file->private_data;
1618 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1619 struct iwl_rxq *rxq = &trans_pcie->rxq;
1620 char buf[256];
1621 int pos = 0;
1622 const size_t bufsz = sizeof(buf);
1623
1624 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1625 rxq->read);
1626 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1627 rxq->write);
1628 pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
1629 rxq->write_actual);
1630 pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
1631 rxq->need_update);
1632 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1633 rxq->free_count);
1634 if (rxq->rb_stts) {
1635 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1636 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1637 } else {
1638 pos += scnprintf(buf + pos, bufsz - pos,
1639 "closed_rb_num: Not Allocated\n");
1640 }
1641 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1642 }
1643
iwl_dbgfs_interrupt_read(struct file * file,char __user * user_buf,size_t count,loff_t * ppos)1644 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1645 char __user *user_buf,
1646 size_t count, loff_t *ppos)
1647 {
1648 struct iwl_trans *trans = file->private_data;
1649 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1650 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1651
1652 int pos = 0;
1653 char *buf;
1654 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1655 ssize_t ret;
1656
1657 buf = kzalloc(bufsz, GFP_KERNEL);
1658 if (!buf)
1659 return -ENOMEM;
1660
1661 pos += scnprintf(buf + pos, bufsz - pos,
1662 "Interrupt Statistics Report:\n");
1663
1664 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1665 isr_stats->hw);
1666 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1667 isr_stats->sw);
1668 if (isr_stats->sw || isr_stats->hw) {
1669 pos += scnprintf(buf + pos, bufsz - pos,
1670 "\tLast Restarting Code: 0x%X\n",
1671 isr_stats->err_code);
1672 }
1673 #ifdef CONFIG_IWLWIFI_DEBUG
1674 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1675 isr_stats->sch);
1676 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1677 isr_stats->alive);
1678 #endif
1679 pos += scnprintf(buf + pos, bufsz - pos,
1680 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1681
1682 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1683 isr_stats->ctkill);
1684
1685 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1686 isr_stats->wakeup);
1687
1688 pos += scnprintf(buf + pos, bufsz - pos,
1689 "Rx command responses:\t\t %u\n", isr_stats->rx);
1690
1691 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1692 isr_stats->tx);
1693
1694 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1695 isr_stats->unhandled);
1696
1697 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1698 kfree(buf);
1699 return ret;
1700 }
1701
iwl_dbgfs_interrupt_write(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)1702 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1703 const char __user *user_buf,
1704 size_t count, loff_t *ppos)
1705 {
1706 struct iwl_trans *trans = file->private_data;
1707 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1708 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1709
1710 char buf[8];
1711 int buf_size;
1712 u32 reset_flag;
1713
1714 memset(buf, 0, sizeof(buf));
1715 buf_size = min(count, sizeof(buf) - 1);
1716 if (copy_from_user(buf, user_buf, buf_size))
1717 return -EFAULT;
1718 if (sscanf(buf, "%x", &reset_flag) != 1)
1719 return -EFAULT;
1720 if (reset_flag == 0)
1721 memset(isr_stats, 0, sizeof(*isr_stats));
1722
1723 return count;
1724 }
1725
iwl_dbgfs_csr_write(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)1726 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1727 const char __user *user_buf,
1728 size_t count, loff_t *ppos)
1729 {
1730 struct iwl_trans *trans = file->private_data;
1731 char buf[8];
1732 int buf_size;
1733 int csr;
1734
1735 memset(buf, 0, sizeof(buf));
1736 buf_size = min(count, sizeof(buf) - 1);
1737 if (copy_from_user(buf, user_buf, buf_size))
1738 return -EFAULT;
1739 if (sscanf(buf, "%d", &csr) != 1)
1740 return -EFAULT;
1741
1742 iwl_pcie_dump_csr(trans);
1743
1744 return count;
1745 }
1746
iwl_dbgfs_fh_reg_read(struct file * file,char __user * user_buf,size_t count,loff_t * ppos)1747 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1748 char __user *user_buf,
1749 size_t count, loff_t *ppos)
1750 {
1751 struct iwl_trans *trans = file->private_data;
1752 char *buf = NULL;
1753 ssize_t ret;
1754
1755 ret = iwl_dump_fh(trans, &buf);
1756 if (ret < 0)
1757 return ret;
1758 if (!buf)
1759 return -EINVAL;
1760 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
1761 kfree(buf);
1762 return ret;
1763 }
1764
1765 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1766 DEBUGFS_READ_FILE_OPS(fh_reg);
1767 DEBUGFS_READ_FILE_OPS(rx_queue);
1768 DEBUGFS_READ_FILE_OPS(tx_queue);
1769 DEBUGFS_WRITE_FILE_OPS(csr);
1770
1771 /*
1772 * Create the debugfs files and directories
1773 *
1774 */
iwl_trans_pcie_dbgfs_register(struct iwl_trans * trans,struct dentry * dir)1775 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1776 struct dentry *dir)
1777 {
1778 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1779 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1780 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1781 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1782 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1783 return 0;
1784
1785 err:
1786 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1787 return -ENOMEM;
1788 }
1789
iwl_trans_pcie_get_cmdlen(struct iwl_tfd * tfd)1790 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
1791 {
1792 u32 cmdlen = 0;
1793 int i;
1794
1795 for (i = 0; i < IWL_NUM_OF_TBS; i++)
1796 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
1797
1798 return cmdlen;
1799 }
1800
1801 static const struct {
1802 u32 start, end;
1803 } iwl_prph_dump_addr[] = {
1804 { .start = 0x00a00000, .end = 0x00a00000 },
1805 { .start = 0x00a0000c, .end = 0x00a00024 },
1806 { .start = 0x00a0002c, .end = 0x00a0003c },
1807 { .start = 0x00a00410, .end = 0x00a00418 },
1808 { .start = 0x00a00420, .end = 0x00a00420 },
1809 { .start = 0x00a00428, .end = 0x00a00428 },
1810 { .start = 0x00a00430, .end = 0x00a0043c },
1811 { .start = 0x00a00444, .end = 0x00a00444 },
1812 { .start = 0x00a004c0, .end = 0x00a004cc },
1813 { .start = 0x00a004d8, .end = 0x00a004d8 },
1814 { .start = 0x00a004e0, .end = 0x00a004f0 },
1815 { .start = 0x00a00840, .end = 0x00a00840 },
1816 { .start = 0x00a00850, .end = 0x00a00858 },
1817 { .start = 0x00a01004, .end = 0x00a01008 },
1818 { .start = 0x00a01010, .end = 0x00a01010 },
1819 { .start = 0x00a01018, .end = 0x00a01018 },
1820 { .start = 0x00a01024, .end = 0x00a01024 },
1821 { .start = 0x00a0102c, .end = 0x00a01034 },
1822 { .start = 0x00a0103c, .end = 0x00a01040 },
1823 { .start = 0x00a01048, .end = 0x00a01094 },
1824 { .start = 0x00a01c00, .end = 0x00a01c20 },
1825 { .start = 0x00a01c58, .end = 0x00a01c58 },
1826 { .start = 0x00a01c7c, .end = 0x00a01c7c },
1827 { .start = 0x00a01c28, .end = 0x00a01c54 },
1828 { .start = 0x00a01c5c, .end = 0x00a01c5c },
1829 { .start = 0x00a01c84, .end = 0x00a01c84 },
1830 { .start = 0x00a01ce0, .end = 0x00a01d0c },
1831 { .start = 0x00a01d18, .end = 0x00a01d20 },
1832 { .start = 0x00a01d2c, .end = 0x00a01d30 },
1833 { .start = 0x00a01d40, .end = 0x00a01d5c },
1834 { .start = 0x00a01d80, .end = 0x00a01d80 },
1835 { .start = 0x00a01d98, .end = 0x00a01d98 },
1836 { .start = 0x00a01dc0, .end = 0x00a01dfc },
1837 { .start = 0x00a01e00, .end = 0x00a01e2c },
1838 { .start = 0x00a01e40, .end = 0x00a01e60 },
1839 { .start = 0x00a01e84, .end = 0x00a01e90 },
1840 { .start = 0x00a01e9c, .end = 0x00a01ec4 },
1841 { .start = 0x00a01ed0, .end = 0x00a01ed0 },
1842 { .start = 0x00a01f00, .end = 0x00a01f14 },
1843 { .start = 0x00a01f44, .end = 0x00a01f58 },
1844 { .start = 0x00a01f80, .end = 0x00a01fa8 },
1845 { .start = 0x00a01fb0, .end = 0x00a01fbc },
1846 { .start = 0x00a01ff8, .end = 0x00a01ffc },
1847 { .start = 0x00a02000, .end = 0x00a02048 },
1848 { .start = 0x00a02068, .end = 0x00a020f0 },
1849 { .start = 0x00a02100, .end = 0x00a02118 },
1850 { .start = 0x00a02140, .end = 0x00a0214c },
1851 { .start = 0x00a02168, .end = 0x00a0218c },
1852 { .start = 0x00a021c0, .end = 0x00a021c0 },
1853 { .start = 0x00a02400, .end = 0x00a02410 },
1854 { .start = 0x00a02418, .end = 0x00a02420 },
1855 { .start = 0x00a02428, .end = 0x00a0242c },
1856 { .start = 0x00a02434, .end = 0x00a02434 },
1857 { .start = 0x00a02440, .end = 0x00a02460 },
1858 { .start = 0x00a02468, .end = 0x00a024b0 },
1859 { .start = 0x00a024c8, .end = 0x00a024cc },
1860 { .start = 0x00a02500, .end = 0x00a02504 },
1861 { .start = 0x00a0250c, .end = 0x00a02510 },
1862 { .start = 0x00a02540, .end = 0x00a02554 },
1863 { .start = 0x00a02580, .end = 0x00a025f4 },
1864 { .start = 0x00a02600, .end = 0x00a0260c },
1865 { .start = 0x00a02648, .end = 0x00a02650 },
1866 { .start = 0x00a02680, .end = 0x00a02680 },
1867 { .start = 0x00a026c0, .end = 0x00a026d0 },
1868 { .start = 0x00a02700, .end = 0x00a0270c },
1869 { .start = 0x00a02804, .end = 0x00a02804 },
1870 { .start = 0x00a02818, .end = 0x00a0281c },
1871 { .start = 0x00a02c00, .end = 0x00a02db4 },
1872 { .start = 0x00a02df4, .end = 0x00a02fb0 },
1873 { .start = 0x00a03000, .end = 0x00a03014 },
1874 { .start = 0x00a0301c, .end = 0x00a0302c },
1875 { .start = 0x00a03034, .end = 0x00a03038 },
1876 { .start = 0x00a03040, .end = 0x00a03048 },
1877 { .start = 0x00a03060, .end = 0x00a03068 },
1878 { .start = 0x00a03070, .end = 0x00a03074 },
1879 { .start = 0x00a0307c, .end = 0x00a0307c },
1880 { .start = 0x00a03080, .end = 0x00a03084 },
1881 { .start = 0x00a0308c, .end = 0x00a03090 },
1882 { .start = 0x00a03098, .end = 0x00a03098 },
1883 { .start = 0x00a030a0, .end = 0x00a030a0 },
1884 { .start = 0x00a030a8, .end = 0x00a030b4 },
1885 { .start = 0x00a030bc, .end = 0x00a030bc },
1886 { .start = 0x00a030c0, .end = 0x00a0312c },
1887 { .start = 0x00a03c00, .end = 0x00a03c5c },
1888 { .start = 0x00a04400, .end = 0x00a04454 },
1889 { .start = 0x00a04460, .end = 0x00a04474 },
1890 { .start = 0x00a044c0, .end = 0x00a044ec },
1891 { .start = 0x00a04500, .end = 0x00a04504 },
1892 { .start = 0x00a04510, .end = 0x00a04538 },
1893 { .start = 0x00a04540, .end = 0x00a04548 },
1894 { .start = 0x00a04560, .end = 0x00a0457c },
1895 { .start = 0x00a04590, .end = 0x00a04598 },
1896 { .start = 0x00a045c0, .end = 0x00a045f4 },
1897 };
1898
iwl_trans_pcie_dump_prph(struct iwl_trans * trans,struct iwl_fw_error_dump_data ** data)1899 static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans,
1900 struct iwl_fw_error_dump_data **data)
1901 {
1902 struct iwl_fw_error_dump_prph *prph;
1903 unsigned long flags;
1904 u32 prph_len = 0, i;
1905
1906 if (!iwl_trans_grab_nic_access(trans, false, &flags))
1907 return 0;
1908
1909 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
1910 /* The range includes both boundaries */
1911 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
1912 iwl_prph_dump_addr[i].start + 4;
1913 int reg;
1914 __le32 *val;
1915
1916 prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
1917
1918 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
1919 (*data)->len = cpu_to_le32(sizeof(*prph) +
1920 num_bytes_in_chunk);
1921 prph = (void *)(*data)->data;
1922 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
1923 val = (void *)prph->data;
1924
1925 for (reg = iwl_prph_dump_addr[i].start;
1926 reg <= iwl_prph_dump_addr[i].end;
1927 reg += 4)
1928 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
1929 reg));
1930 *data = iwl_fw_error_next_data(*data);
1931 }
1932
1933 iwl_trans_release_nic_access(trans, &flags);
1934
1935 return prph_len;
1936 }
1937
1938 #define IWL_CSR_TO_DUMP (0x250)
1939
iwl_trans_pcie_dump_csr(struct iwl_trans * trans,struct iwl_fw_error_dump_data ** data)1940 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
1941 struct iwl_fw_error_dump_data **data)
1942 {
1943 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
1944 __le32 *val;
1945 int i;
1946
1947 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
1948 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
1949 val = (void *)(*data)->data;
1950
1951 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
1952 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
1953
1954 *data = iwl_fw_error_next_data(*data);
1955
1956 return csr_len;
1957 }
1958
1959 static
iwl_trans_pcie_dump_data(struct iwl_trans * trans)1960 struct iwl_trans_dump_data *iwl_trans_pcie_dump_data(struct iwl_trans *trans)
1961 {
1962 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1963 struct iwl_fw_error_dump_data *data;
1964 struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
1965 struct iwl_fw_error_dump_txcmd *txcmd;
1966 struct iwl_trans_dump_data *dump_data;
1967 u32 len;
1968 int i, ptr;
1969
1970 /* transport dump header */
1971 len = sizeof(*dump_data);
1972
1973 /* host commands */
1974 len += sizeof(*data) +
1975 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
1976
1977 /* CSR registers */
1978 len += sizeof(*data) + IWL_CSR_TO_DUMP;
1979
1980 /* PRPH registers */
1981 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
1982 /* The range includes both boundaries */
1983 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
1984 iwl_prph_dump_addr[i].start + 4;
1985
1986 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) +
1987 num_bytes_in_chunk;
1988 }
1989
1990 /* FW monitor */
1991 if (trans_pcie->fw_mon_page)
1992 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
1993 trans_pcie->fw_mon_size;
1994
1995 dump_data = vzalloc(len);
1996 if (!dump_data)
1997 return NULL;
1998
1999 len = 0;
2000 data = (void *)dump_data->data;
2001 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2002 txcmd = (void *)data->data;
2003 spin_lock_bh(&cmdq->lock);
2004 ptr = cmdq->q.write_ptr;
2005 for (i = 0; i < cmdq->q.n_window; i++) {
2006 u8 idx = get_cmd_index(&cmdq->q, ptr);
2007 u32 caplen, cmdlen;
2008
2009 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2010 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2011
2012 if (cmdlen) {
2013 len += sizeof(*txcmd) + caplen;
2014 txcmd->cmdlen = cpu_to_le32(cmdlen);
2015 txcmd->caplen = cpu_to_le32(caplen);
2016 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2017 txcmd = (void *)((u8 *)txcmd->data + caplen);
2018 }
2019
2020 ptr = iwl_queue_dec_wrap(ptr);
2021 }
2022 spin_unlock_bh(&cmdq->lock);
2023
2024 data->len = cpu_to_le32(len);
2025 len += sizeof(*data);
2026 data = iwl_fw_error_next_data(data);
2027
2028 len += iwl_trans_pcie_dump_prph(trans, &data);
2029 len += iwl_trans_pcie_dump_csr(trans, &data);
2030 /* data is already pointing to the next section */
2031
2032 if (trans_pcie->fw_mon_page) {
2033 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2034
2035 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2036 data->len = cpu_to_le32(trans_pcie->fw_mon_size +
2037 sizeof(*fw_mon_data));
2038 fw_mon_data = (void *)data->data;
2039 fw_mon_data->fw_mon_wr_ptr =
2040 cpu_to_le32(iwl_read_prph(trans, MON_BUFF_WRPTR));
2041 fw_mon_data->fw_mon_cycle_cnt =
2042 cpu_to_le32(iwl_read_prph(trans, MON_BUFF_CYCLE_CNT));
2043 fw_mon_data->fw_mon_base_ptr =
2044 cpu_to_le32(iwl_read_prph(trans, MON_BUFF_BASE_ADDR));
2045
2046 /*
2047 * The firmware is now asserted, it won't write anything to
2048 * the buffer. CPU can take ownership to fetch the data.
2049 * The buffer will be handed back to the device before the
2050 * firmware will be restarted.
2051 */
2052 dma_sync_single_for_cpu(trans->dev, trans_pcie->fw_mon_phys,
2053 trans_pcie->fw_mon_size,
2054 DMA_FROM_DEVICE);
2055 memcpy(fw_mon_data->data, page_address(trans_pcie->fw_mon_page),
2056 trans_pcie->fw_mon_size);
2057
2058 len += sizeof(*data) + sizeof(*fw_mon_data) +
2059 trans_pcie->fw_mon_size;
2060 }
2061
2062 dump_data->len = len;
2063
2064 return dump_data;
2065 }
2066 #else
iwl_trans_pcie_dbgfs_register(struct iwl_trans * trans,struct dentry * dir)2067 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2068 struct dentry *dir)
2069 {
2070 return 0;
2071 }
2072 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2073
2074 static const struct iwl_trans_ops trans_ops_pcie = {
2075 .start_hw = iwl_trans_pcie_start_hw,
2076 .op_mode_leave = iwl_trans_pcie_op_mode_leave,
2077 .fw_alive = iwl_trans_pcie_fw_alive,
2078 .start_fw = iwl_trans_pcie_start_fw,
2079 .stop_device = iwl_trans_pcie_stop_device,
2080
2081 .d3_suspend = iwl_trans_pcie_d3_suspend,
2082 .d3_resume = iwl_trans_pcie_d3_resume,
2083
2084 .send_cmd = iwl_trans_pcie_send_hcmd,
2085
2086 .tx = iwl_trans_pcie_tx,
2087 .reclaim = iwl_trans_pcie_reclaim,
2088
2089 .txq_disable = iwl_trans_pcie_txq_disable,
2090 .txq_enable = iwl_trans_pcie_txq_enable,
2091
2092 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2093
2094 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2095
2096 .write8 = iwl_trans_pcie_write8,
2097 .write32 = iwl_trans_pcie_write32,
2098 .read32 = iwl_trans_pcie_read32,
2099 .read_prph = iwl_trans_pcie_read_prph,
2100 .write_prph = iwl_trans_pcie_write_prph,
2101 .read_mem = iwl_trans_pcie_read_mem,
2102 .write_mem = iwl_trans_pcie_write_mem,
2103 .configure = iwl_trans_pcie_configure,
2104 .set_pmi = iwl_trans_pcie_set_pmi,
2105 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
2106 .release_nic_access = iwl_trans_pcie_release_nic_access,
2107 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
2108
2109 #ifdef CONFIG_IWLWIFI_DEBUGFS
2110 .dump_data = iwl_trans_pcie_dump_data,
2111 #endif
2112 };
2113
iwl_trans_pcie_alloc(struct pci_dev * pdev,const struct pci_device_id * ent,const struct iwl_cfg * cfg)2114 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2115 const struct pci_device_id *ent,
2116 const struct iwl_cfg *cfg)
2117 {
2118 struct iwl_trans_pcie *trans_pcie;
2119 struct iwl_trans *trans;
2120 u16 pci_cmd;
2121 int err;
2122
2123 trans = kzalloc(sizeof(struct iwl_trans) +
2124 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2125 if (!trans) {
2126 err = -ENOMEM;
2127 goto out;
2128 }
2129
2130 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2131
2132 trans->ops = &trans_ops_pcie;
2133 trans->cfg = cfg;
2134 trans_lockdep_init(trans);
2135 trans_pcie->trans = trans;
2136 spin_lock_init(&trans_pcie->irq_lock);
2137 spin_lock_init(&trans_pcie->reg_lock);
2138 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2139
2140 err = pci_enable_device(pdev);
2141 if (err)
2142 goto out_no_pci;
2143
2144 if (!cfg->base_params->pcie_l1_allowed) {
2145 /*
2146 * W/A - seems to solve weird behavior. We need to remove this
2147 * if we don't want to stay in L1 all the time. This wastes a
2148 * lot of power.
2149 */
2150 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2151 PCIE_LINK_STATE_L1 |
2152 PCIE_LINK_STATE_CLKPM);
2153 }
2154
2155 pci_set_master(pdev);
2156
2157 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2158 if (!err)
2159 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2160 if (err) {
2161 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2162 if (!err)
2163 err = pci_set_consistent_dma_mask(pdev,
2164 DMA_BIT_MASK(32));
2165 /* both attempts failed: */
2166 if (err) {
2167 dev_err(&pdev->dev, "No suitable DMA available\n");
2168 goto out_pci_disable_device;
2169 }
2170 }
2171
2172 err = pci_request_regions(pdev, DRV_NAME);
2173 if (err) {
2174 dev_err(&pdev->dev, "pci_request_regions failed\n");
2175 goto out_pci_disable_device;
2176 }
2177
2178 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2179 if (!trans_pcie->hw_base) {
2180 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
2181 err = -ENODEV;
2182 goto out_pci_release_regions;
2183 }
2184
2185 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2186 * PCI Tx retries from interfering with C3 CPU state */
2187 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2188
2189 trans->dev = &pdev->dev;
2190 trans_pcie->pci_dev = pdev;
2191 iwl_disable_interrupts(trans);
2192
2193 err = pci_enable_msi(pdev);
2194 if (err) {
2195 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
2196 /* enable rfkill interrupt: hw bug w/a */
2197 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2198 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2199 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2200 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2201 }
2202 }
2203
2204 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2205 /*
2206 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2207 * changed, and now the revision step also includes bit 0-1 (no more
2208 * "dash" value). To keep hw_rev backwards compatible - we'll store it
2209 * in the old format.
2210 */
2211 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
2212 trans->hw_rev = (trans->hw_rev & 0xfff0) |
2213 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
2214
2215 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2216 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2217 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2218
2219 /* Initialize the wait queue for commands */
2220 init_waitqueue_head(&trans_pcie->wait_command_queue);
2221
2222 snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
2223 "iwl_cmd_pool:%s", dev_name(trans->dev));
2224
2225 trans->dev_cmd_headroom = 0;
2226 trans->dev_cmd_pool =
2227 kmem_cache_create(trans->dev_cmd_pool_name,
2228 sizeof(struct iwl_device_cmd)
2229 + trans->dev_cmd_headroom,
2230 sizeof(void *),
2231 SLAB_HWCACHE_ALIGN,
2232 NULL);
2233
2234 if (!trans->dev_cmd_pool) {
2235 err = -ENOMEM;
2236 goto out_pci_disable_msi;
2237 }
2238
2239 if (iwl_pcie_alloc_ict(trans))
2240 goto out_free_cmd_pool;
2241
2242 err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
2243 iwl_pcie_irq_handler,
2244 IRQF_SHARED, DRV_NAME, trans);
2245 if (err) {
2246 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2247 goto out_free_ict;
2248 }
2249
2250 trans_pcie->inta_mask = CSR_INI_SET_MASK;
2251
2252 return trans;
2253
2254 out_free_ict:
2255 iwl_pcie_free_ict(trans);
2256 out_free_cmd_pool:
2257 kmem_cache_destroy(trans->dev_cmd_pool);
2258 out_pci_disable_msi:
2259 pci_disable_msi(pdev);
2260 out_pci_release_regions:
2261 pci_release_regions(pdev);
2262 out_pci_disable_device:
2263 pci_disable_device(pdev);
2264 out_no_pci:
2265 kfree(trans);
2266 out:
2267 return ERR_PTR(err);
2268 }
2269