1 /*
2 * This file is part of wl1271
3 *
4 * Copyright (C) 2008-2010 Nokia Corporation
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24
25 #include <linux/err.h>
26
27 #include "../wlcore/wlcore.h"
28 #include "../wlcore/debug.h"
29 #include "../wlcore/io.h"
30 #include "../wlcore/acx.h"
31 #include "../wlcore/tx.h"
32 #include "../wlcore/rx.h"
33 #include "../wlcore/boot.h"
34
35 #include "wl12xx.h"
36 #include "reg.h"
37 #include "cmd.h"
38 #include "acx.h"
39 #include "scan.h"
40 #include "event.h"
41 #include "debugfs.h"
42
43 static char *fref_param;
44 static char *tcxo_param;
45
46 static struct wlcore_conf wl12xx_conf = {
47 .sg = {
48 .params = {
49 [CONF_SG_ACL_BT_MASTER_MIN_BR] = 10,
50 [CONF_SG_ACL_BT_MASTER_MAX_BR] = 180,
51 [CONF_SG_ACL_BT_SLAVE_MIN_BR] = 10,
52 [CONF_SG_ACL_BT_SLAVE_MAX_BR] = 180,
53 [CONF_SG_ACL_BT_MASTER_MIN_EDR] = 10,
54 [CONF_SG_ACL_BT_MASTER_MAX_EDR] = 80,
55 [CONF_SG_ACL_BT_SLAVE_MIN_EDR] = 10,
56 [CONF_SG_ACL_BT_SLAVE_MAX_EDR] = 80,
57 [CONF_SG_ACL_WLAN_PS_MASTER_BR] = 8,
58 [CONF_SG_ACL_WLAN_PS_SLAVE_BR] = 8,
59 [CONF_SG_ACL_WLAN_PS_MASTER_EDR] = 20,
60 [CONF_SG_ACL_WLAN_PS_SLAVE_EDR] = 20,
61 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR] = 20,
62 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR] = 35,
63 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR] = 16,
64 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR] = 35,
65 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR] = 32,
66 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR] = 50,
67 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR] = 28,
68 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR] = 50,
69 [CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR] = 10,
70 [CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR] = 20,
71 [CONF_SG_ACL_PASSIVE_SCAN_BT_BR] = 75,
72 [CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR] = 15,
73 [CONF_SG_ACL_PASSIVE_SCAN_BT_EDR] = 27,
74 [CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR] = 17,
75 /* active scan params */
76 [CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
77 [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
78 [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP] = 100,
79 /* passive scan params */
80 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_BR] = 800,
81 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_EDR] = 200,
82 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3] = 200,
83 /* passive scan in dual antenna params */
84 [CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
85 [CONF_SG_BCN_HV3_COLLISION_THRESH_IN_PASSIVE_SCAN] = 0,
86 [CONF_SG_TX_RX_PROTECTION_BWIDTH_IN_PASSIVE_SCAN] = 0,
87 /* general params */
88 [CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
89 [CONF_SG_ANTENNA_CONFIGURATION] = 0,
90 [CONF_SG_BEACON_MISS_PERCENT] = 60,
91 [CONF_SG_DHCP_TIME] = 5000,
92 [CONF_SG_RXT] = 1200,
93 [CONF_SG_TXT] = 1000,
94 [CONF_SG_ADAPTIVE_RXT_TXT] = 1,
95 [CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
96 [CONF_SG_HV3_MAX_SERVED] = 6,
97 [CONF_SG_PS_POLL_TIMEOUT] = 10,
98 [CONF_SG_UPSD_TIMEOUT] = 10,
99 [CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
100 [CONF_SG_STA_RX_WINDOW_AFTER_DTIM] = 5,
101 [CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 30,
102 /* AP params */
103 [CONF_AP_BEACON_MISS_TX] = 3,
104 [CONF_AP_RX_WINDOW_AFTER_BEACON] = 10,
105 [CONF_AP_BEACON_WINDOW_INTERVAL] = 2,
106 [CONF_AP_CONNECTION_PROTECTION_TIME] = 0,
107 [CONF_AP_BT_ACL_VAL_BT_SERVE_TIME] = 25,
108 [CONF_AP_BT_ACL_VAL_WL_SERVE_TIME] = 25,
109 /* CTS Diluting params */
110 [CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
111 [CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
112 },
113 .state = CONF_SG_PROTECTIVE,
114 },
115 .rx = {
116 .rx_msdu_life_time = 512000,
117 .packet_detection_threshold = 0,
118 .ps_poll_timeout = 15,
119 .upsd_timeout = 15,
120 .rts_threshold = IEEE80211_MAX_RTS_THRESHOLD,
121 .rx_cca_threshold = 0,
122 .irq_blk_threshold = 0xFFFF,
123 .irq_pkt_threshold = 0,
124 .irq_timeout = 600,
125 .queue_type = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
126 },
127 .tx = {
128 .tx_energy_detection = 0,
129 .sta_rc_conf = {
130 .enabled_rates = 0,
131 .short_retry_limit = 10,
132 .long_retry_limit = 10,
133 .aflags = 0,
134 },
135 .ac_conf_count = 4,
136 .ac_conf = {
137 [CONF_TX_AC_BE] = {
138 .ac = CONF_TX_AC_BE,
139 .cw_min = 15,
140 .cw_max = 63,
141 .aifsn = 3,
142 .tx_op_limit = 0,
143 },
144 [CONF_TX_AC_BK] = {
145 .ac = CONF_TX_AC_BK,
146 .cw_min = 15,
147 .cw_max = 63,
148 .aifsn = 7,
149 .tx_op_limit = 0,
150 },
151 [CONF_TX_AC_VI] = {
152 .ac = CONF_TX_AC_VI,
153 .cw_min = 15,
154 .cw_max = 63,
155 .aifsn = CONF_TX_AIFS_PIFS,
156 .tx_op_limit = 3008,
157 },
158 [CONF_TX_AC_VO] = {
159 .ac = CONF_TX_AC_VO,
160 .cw_min = 15,
161 .cw_max = 63,
162 .aifsn = CONF_TX_AIFS_PIFS,
163 .tx_op_limit = 1504,
164 },
165 },
166 .max_tx_retries = 100,
167 .ap_aging_period = 300,
168 .tid_conf_count = 4,
169 .tid_conf = {
170 [CONF_TX_AC_BE] = {
171 .queue_id = CONF_TX_AC_BE,
172 .channel_type = CONF_CHANNEL_TYPE_EDCF,
173 .tsid = CONF_TX_AC_BE,
174 .ps_scheme = CONF_PS_SCHEME_LEGACY,
175 .ack_policy = CONF_ACK_POLICY_LEGACY,
176 .apsd_conf = {0, 0},
177 },
178 [CONF_TX_AC_BK] = {
179 .queue_id = CONF_TX_AC_BK,
180 .channel_type = CONF_CHANNEL_TYPE_EDCF,
181 .tsid = CONF_TX_AC_BK,
182 .ps_scheme = CONF_PS_SCHEME_LEGACY,
183 .ack_policy = CONF_ACK_POLICY_LEGACY,
184 .apsd_conf = {0, 0},
185 },
186 [CONF_TX_AC_VI] = {
187 .queue_id = CONF_TX_AC_VI,
188 .channel_type = CONF_CHANNEL_TYPE_EDCF,
189 .tsid = CONF_TX_AC_VI,
190 .ps_scheme = CONF_PS_SCHEME_LEGACY,
191 .ack_policy = CONF_ACK_POLICY_LEGACY,
192 .apsd_conf = {0, 0},
193 },
194 [CONF_TX_AC_VO] = {
195 .queue_id = CONF_TX_AC_VO,
196 .channel_type = CONF_CHANNEL_TYPE_EDCF,
197 .tsid = CONF_TX_AC_VO,
198 .ps_scheme = CONF_PS_SCHEME_LEGACY,
199 .ack_policy = CONF_ACK_POLICY_LEGACY,
200 .apsd_conf = {0, 0},
201 },
202 },
203 .frag_threshold = IEEE80211_MAX_FRAG_THRESHOLD,
204 .tx_compl_timeout = 700,
205 .tx_compl_threshold = 4,
206 .basic_rate = CONF_HW_BIT_RATE_1MBPS,
207 .basic_rate_5 = CONF_HW_BIT_RATE_6MBPS,
208 .tmpl_short_retry_limit = 10,
209 .tmpl_long_retry_limit = 10,
210 .tx_watchdog_timeout = 5000,
211 .slow_link_thold = 3,
212 .fast_link_thold = 10,
213 },
214 .conn = {
215 .wake_up_event = CONF_WAKE_UP_EVENT_DTIM,
216 .listen_interval = 1,
217 .suspend_wake_up_event = CONF_WAKE_UP_EVENT_N_DTIM,
218 .suspend_listen_interval = 3,
219 .bcn_filt_mode = CONF_BCN_FILT_MODE_ENABLED,
220 .bcn_filt_ie_count = 3,
221 .bcn_filt_ie = {
222 [0] = {
223 .ie = WLAN_EID_CHANNEL_SWITCH,
224 .rule = CONF_BCN_RULE_PASS_ON_APPEARANCE,
225 },
226 [1] = {
227 .ie = WLAN_EID_HT_OPERATION,
228 .rule = CONF_BCN_RULE_PASS_ON_CHANGE,
229 },
230 [2] = {
231 .ie = WLAN_EID_ERP_INFO,
232 .rule = CONF_BCN_RULE_PASS_ON_CHANGE,
233 },
234 },
235 .synch_fail_thold = 12,
236 .bss_lose_timeout = 400,
237 .beacon_rx_timeout = 10000,
238 .broadcast_timeout = 20000,
239 .rx_broadcast_in_ps = 1,
240 .ps_poll_threshold = 10,
241 .bet_enable = CONF_BET_MODE_ENABLE,
242 .bet_max_consecutive = 50,
243 .psm_entry_retries = 8,
244 .psm_exit_retries = 16,
245 .psm_entry_nullfunc_retries = 3,
246 .dynamic_ps_timeout = 1500,
247 .forced_ps = false,
248 .keep_alive_interval = 55000,
249 .max_listen_interval = 20,
250 .sta_sleep_auth = WL1271_PSM_ILLEGAL,
251 },
252 .itrim = {
253 .enable = false,
254 .timeout = 50000,
255 },
256 .pm_config = {
257 .host_clk_settling_time = 5000,
258 .host_fast_wakeup_support = CONF_FAST_WAKEUP_DISABLE,
259 },
260 .roam_trigger = {
261 .trigger_pacing = 1,
262 .avg_weight_rssi_beacon = 20,
263 .avg_weight_rssi_data = 10,
264 .avg_weight_snr_beacon = 20,
265 .avg_weight_snr_data = 10,
266 },
267 .scan = {
268 .min_dwell_time_active = 7500,
269 .max_dwell_time_active = 30000,
270 .min_dwell_time_active_long = 25000,
271 .max_dwell_time_active_long = 50000,
272 .dwell_time_passive = 100000,
273 .dwell_time_dfs = 150000,
274 .num_probe_reqs = 2,
275 .split_scan_timeout = 50000,
276 },
277 .sched_scan = {
278 /*
279 * Values are in TU/1000 but since sched scan FW command
280 * params are in TUs rounding up may occur.
281 */
282 .base_dwell_time = 7500,
283 .max_dwell_time_delta = 22500,
284 /* based on 250bits per probe @1Mbps */
285 .dwell_time_delta_per_probe = 2000,
286 /* based on 250bits per probe @6Mbps (plus a bit more) */
287 .dwell_time_delta_per_probe_5 = 350,
288 .dwell_time_passive = 100000,
289 .dwell_time_dfs = 150000,
290 .num_probe_reqs = 2,
291 .rssi_threshold = -90,
292 .snr_threshold = 0,
293 },
294 .ht = {
295 .rx_ba_win_size = 8,
296 .tx_ba_win_size = 64,
297 .inactivity_timeout = 10000,
298 .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
299 },
300 /*
301 * Memory config for wl127x chips is given in the
302 * wl12xx_default_priv_conf struct. The below configuration is
303 * for wl128x chips.
304 */
305 .mem = {
306 .num_stations = 1,
307 .ssid_profiles = 1,
308 .rx_block_num = 40,
309 .tx_min_block_num = 40,
310 .dynamic_memory = 1,
311 .min_req_tx_blocks = 45,
312 .min_req_rx_blocks = 22,
313 .tx_min = 27,
314 },
315 .fm_coex = {
316 .enable = true,
317 .swallow_period = 5,
318 .n_divider_fref_set_1 = 0xff, /* default */
319 .n_divider_fref_set_2 = 12,
320 .m_divider_fref_set_1 = 0xffff,
321 .m_divider_fref_set_2 = 148, /* default */
322 .coex_pll_stabilization_time = 0xffffffff, /* default */
323 .ldo_stabilization_time = 0xffff, /* default */
324 .fm_disturbed_band_margin = 0xff, /* default */
325 .swallow_clk_diff = 0xff, /* default */
326 },
327 .rx_streaming = {
328 .duration = 150,
329 .queues = 0x1,
330 .interval = 20,
331 .always = 0,
332 },
333 .fwlog = {
334 .mode = WL12XX_FWLOG_CONTINUOUS,
335 .mem_blocks = 2,
336 .severity = 0,
337 .timestamp = WL12XX_FWLOG_TIMESTAMP_DISABLED,
338 .output = WL12XX_FWLOG_OUTPUT_DBG_PINS,
339 .threshold = 0,
340 },
341 .rate = {
342 .rate_retry_score = 32000,
343 .per_add = 8192,
344 .per_th1 = 2048,
345 .per_th2 = 4096,
346 .max_per = 8100,
347 .inverse_curiosity_factor = 5,
348 .tx_fail_low_th = 4,
349 .tx_fail_high_th = 10,
350 .per_alpha_shift = 4,
351 .per_add_shift = 13,
352 .per_beta1_shift = 10,
353 .per_beta2_shift = 8,
354 .rate_check_up = 2,
355 .rate_check_down = 12,
356 .rate_retry_policy = {
357 0x00, 0x00, 0x00, 0x00, 0x00,
358 0x00, 0x00, 0x00, 0x00, 0x00,
359 0x00, 0x00, 0x00,
360 },
361 },
362 .hangover = {
363 .recover_time = 0,
364 .hangover_period = 20,
365 .dynamic_mode = 1,
366 .early_termination_mode = 1,
367 .max_period = 20,
368 .min_period = 1,
369 .increase_delta = 1,
370 .decrease_delta = 2,
371 .quiet_time = 4,
372 .increase_time = 1,
373 .window_size = 16,
374 },
375 .recovery = {
376 .bug_on_recovery = 0,
377 .no_recovery = 0,
378 },
379 };
380
381 static struct wl12xx_priv_conf wl12xx_default_priv_conf = {
382 .rf = {
383 .tx_per_channel_power_compensation_2 = {
384 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
385 },
386 .tx_per_channel_power_compensation_5 = {
387 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
388 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
389 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
390 },
391 },
392 .mem_wl127x = {
393 .num_stations = 1,
394 .ssid_profiles = 1,
395 .rx_block_num = 70,
396 .tx_min_block_num = 40,
397 .dynamic_memory = 1,
398 .min_req_tx_blocks = 100,
399 .min_req_rx_blocks = 22,
400 .tx_min = 27,
401 },
402
403 };
404
405 #define WL12XX_TX_HW_BLOCK_SPARE_DEFAULT 1
406 #define WL12XX_TX_HW_BLOCK_GEM_SPARE 2
407 #define WL12XX_TX_HW_BLOCK_SIZE 252
408
409 static const u8 wl12xx_rate_to_idx_2ghz[] = {
410 /* MCS rates are used only with 11n */
411 7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI */
412 7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7 */
413 6, /* WL12XX_CONF_HW_RXTX_RATE_MCS6 */
414 5, /* WL12XX_CONF_HW_RXTX_RATE_MCS5 */
415 4, /* WL12XX_CONF_HW_RXTX_RATE_MCS4 */
416 3, /* WL12XX_CONF_HW_RXTX_RATE_MCS3 */
417 2, /* WL12XX_CONF_HW_RXTX_RATE_MCS2 */
418 1, /* WL12XX_CONF_HW_RXTX_RATE_MCS1 */
419 0, /* WL12XX_CONF_HW_RXTX_RATE_MCS0 */
420
421 11, /* WL12XX_CONF_HW_RXTX_RATE_54 */
422 10, /* WL12XX_CONF_HW_RXTX_RATE_48 */
423 9, /* WL12XX_CONF_HW_RXTX_RATE_36 */
424 8, /* WL12XX_CONF_HW_RXTX_RATE_24 */
425
426 /* TI-specific rate */
427 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_22 */
428
429 7, /* WL12XX_CONF_HW_RXTX_RATE_18 */
430 6, /* WL12XX_CONF_HW_RXTX_RATE_12 */
431 3, /* WL12XX_CONF_HW_RXTX_RATE_11 */
432 5, /* WL12XX_CONF_HW_RXTX_RATE_9 */
433 4, /* WL12XX_CONF_HW_RXTX_RATE_6 */
434 2, /* WL12XX_CONF_HW_RXTX_RATE_5_5 */
435 1, /* WL12XX_CONF_HW_RXTX_RATE_2 */
436 0 /* WL12XX_CONF_HW_RXTX_RATE_1 */
437 };
438
439 static const u8 wl12xx_rate_to_idx_5ghz[] = {
440 /* MCS rates are used only with 11n */
441 7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI */
442 7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7 */
443 6, /* WL12XX_CONF_HW_RXTX_RATE_MCS6 */
444 5, /* WL12XX_CONF_HW_RXTX_RATE_MCS5 */
445 4, /* WL12XX_CONF_HW_RXTX_RATE_MCS4 */
446 3, /* WL12XX_CONF_HW_RXTX_RATE_MCS3 */
447 2, /* WL12XX_CONF_HW_RXTX_RATE_MCS2 */
448 1, /* WL12XX_CONF_HW_RXTX_RATE_MCS1 */
449 0, /* WL12XX_CONF_HW_RXTX_RATE_MCS0 */
450
451 7, /* WL12XX_CONF_HW_RXTX_RATE_54 */
452 6, /* WL12XX_CONF_HW_RXTX_RATE_48 */
453 5, /* WL12XX_CONF_HW_RXTX_RATE_36 */
454 4, /* WL12XX_CONF_HW_RXTX_RATE_24 */
455
456 /* TI-specific rate */
457 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_22 */
458
459 3, /* WL12XX_CONF_HW_RXTX_RATE_18 */
460 2, /* WL12XX_CONF_HW_RXTX_RATE_12 */
461 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_11 */
462 1, /* WL12XX_CONF_HW_RXTX_RATE_9 */
463 0, /* WL12XX_CONF_HW_RXTX_RATE_6 */
464 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_5_5 */
465 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_2 */
466 CONF_HW_RXTX_RATE_UNSUPPORTED /* WL12XX_CONF_HW_RXTX_RATE_1 */
467 };
468
469 static const u8 *wl12xx_band_rate_to_idx[] = {
470 [IEEE80211_BAND_2GHZ] = wl12xx_rate_to_idx_2ghz,
471 [IEEE80211_BAND_5GHZ] = wl12xx_rate_to_idx_5ghz
472 };
473
474 enum wl12xx_hw_rates {
475 WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI = 0,
476 WL12XX_CONF_HW_RXTX_RATE_MCS7,
477 WL12XX_CONF_HW_RXTX_RATE_MCS6,
478 WL12XX_CONF_HW_RXTX_RATE_MCS5,
479 WL12XX_CONF_HW_RXTX_RATE_MCS4,
480 WL12XX_CONF_HW_RXTX_RATE_MCS3,
481 WL12XX_CONF_HW_RXTX_RATE_MCS2,
482 WL12XX_CONF_HW_RXTX_RATE_MCS1,
483 WL12XX_CONF_HW_RXTX_RATE_MCS0,
484 WL12XX_CONF_HW_RXTX_RATE_54,
485 WL12XX_CONF_HW_RXTX_RATE_48,
486 WL12XX_CONF_HW_RXTX_RATE_36,
487 WL12XX_CONF_HW_RXTX_RATE_24,
488 WL12XX_CONF_HW_RXTX_RATE_22,
489 WL12XX_CONF_HW_RXTX_RATE_18,
490 WL12XX_CONF_HW_RXTX_RATE_12,
491 WL12XX_CONF_HW_RXTX_RATE_11,
492 WL12XX_CONF_HW_RXTX_RATE_9,
493 WL12XX_CONF_HW_RXTX_RATE_6,
494 WL12XX_CONF_HW_RXTX_RATE_5_5,
495 WL12XX_CONF_HW_RXTX_RATE_2,
496 WL12XX_CONF_HW_RXTX_RATE_1,
497 WL12XX_CONF_HW_RXTX_RATE_MAX,
498 };
499
500 static struct wlcore_partition_set wl12xx_ptable[PART_TABLE_LEN] = {
501 [PART_DOWN] = {
502 .mem = {
503 .start = 0x00000000,
504 .size = 0x000177c0
505 },
506 .reg = {
507 .start = REGISTERS_BASE,
508 .size = 0x00008800
509 },
510 .mem2 = {
511 .start = 0x00000000,
512 .size = 0x00000000
513 },
514 .mem3 = {
515 .start = 0x00000000,
516 .size = 0x00000000
517 },
518 },
519
520 [PART_BOOT] = { /* in wl12xx we can use a mix of work and down
521 * partition here */
522 .mem = {
523 .start = 0x00040000,
524 .size = 0x00014fc0
525 },
526 .reg = {
527 .start = REGISTERS_BASE,
528 .size = 0x00008800
529 },
530 .mem2 = {
531 .start = 0x00000000,
532 .size = 0x00000000
533 },
534 .mem3 = {
535 .start = 0x00000000,
536 .size = 0x00000000
537 },
538 },
539
540 [PART_WORK] = {
541 .mem = {
542 .start = 0x00040000,
543 .size = 0x00014fc0
544 },
545 .reg = {
546 .start = REGISTERS_BASE,
547 .size = 0x0000a000
548 },
549 .mem2 = {
550 .start = 0x003004f8,
551 .size = 0x00000004
552 },
553 .mem3 = {
554 .start = 0x00040404,
555 .size = 0x00000000
556 },
557 },
558
559 [PART_DRPW] = {
560 .mem = {
561 .start = 0x00040000,
562 .size = 0x00014fc0
563 },
564 .reg = {
565 .start = DRPW_BASE,
566 .size = 0x00006000
567 },
568 .mem2 = {
569 .start = 0x00000000,
570 .size = 0x00000000
571 },
572 .mem3 = {
573 .start = 0x00000000,
574 .size = 0x00000000
575 }
576 }
577 };
578
579 static const int wl12xx_rtable[REG_TABLE_LEN] = {
580 [REG_ECPU_CONTROL] = WL12XX_REG_ECPU_CONTROL,
581 [REG_INTERRUPT_NO_CLEAR] = WL12XX_REG_INTERRUPT_NO_CLEAR,
582 [REG_INTERRUPT_ACK] = WL12XX_REG_INTERRUPT_ACK,
583 [REG_COMMAND_MAILBOX_PTR] = WL12XX_REG_COMMAND_MAILBOX_PTR,
584 [REG_EVENT_MAILBOX_PTR] = WL12XX_REG_EVENT_MAILBOX_PTR,
585 [REG_INTERRUPT_TRIG] = WL12XX_REG_INTERRUPT_TRIG,
586 [REG_INTERRUPT_MASK] = WL12XX_REG_INTERRUPT_MASK,
587 [REG_PC_ON_RECOVERY] = WL12XX_SCR_PAD4,
588 [REG_CHIP_ID_B] = WL12XX_CHIP_ID_B,
589 [REG_CMD_MBOX_ADDRESS] = WL12XX_CMD_MBOX_ADDRESS,
590
591 /* data access memory addresses, used with partition translation */
592 [REG_SLV_MEM_DATA] = WL1271_SLV_MEM_DATA,
593 [REG_SLV_REG_DATA] = WL1271_SLV_REG_DATA,
594
595 /* raw data access memory addresses */
596 [REG_RAW_FW_STATUS_ADDR] = FW_STATUS_ADDR,
597 };
598
599 /* TODO: maybe move to a new header file? */
600 #define WL127X_FW_NAME_MULTI "ti-connectivity/wl127x-fw-5-mr.bin"
601 #define WL127X_FW_NAME_SINGLE "ti-connectivity/wl127x-fw-5-sr.bin"
602 #define WL127X_PLT_FW_NAME "ti-connectivity/wl127x-fw-5-plt.bin"
603
604 #define WL128X_FW_NAME_MULTI "ti-connectivity/wl128x-fw-5-mr.bin"
605 #define WL128X_FW_NAME_SINGLE "ti-connectivity/wl128x-fw-5-sr.bin"
606 #define WL128X_PLT_FW_NAME "ti-connectivity/wl128x-fw-5-plt.bin"
607
wl127x_prepare_read(struct wl1271 * wl,u32 rx_desc,u32 len)608 static int wl127x_prepare_read(struct wl1271 *wl, u32 rx_desc, u32 len)
609 {
610 int ret;
611
612 if (wl->chip.id != CHIP_ID_128X_PG20) {
613 struct wl1271_acx_mem_map *wl_mem_map = wl->target_mem_map;
614 struct wl12xx_priv *priv = wl->priv;
615
616 /*
617 * Choose the block we want to read
618 * For aggregated packets, only the first memory block
619 * should be retrieved. The FW takes care of the rest.
620 */
621 u32 mem_block = rx_desc & RX_MEM_BLOCK_MASK;
622
623 priv->rx_mem_addr->addr = (mem_block << 8) +
624 le32_to_cpu(wl_mem_map->packet_memory_pool_start);
625
626 priv->rx_mem_addr->addr_extra = priv->rx_mem_addr->addr + 4;
627
628 ret = wlcore_write(wl, WL1271_SLV_REG_DATA, priv->rx_mem_addr,
629 sizeof(*priv->rx_mem_addr), false);
630 if (ret < 0)
631 return ret;
632 }
633
634 return 0;
635 }
636
wl12xx_identify_chip(struct wl1271 * wl)637 static int wl12xx_identify_chip(struct wl1271 *wl)
638 {
639 int ret = 0;
640
641 switch (wl->chip.id) {
642 case CHIP_ID_127X_PG10:
643 wl1271_warning("chip id 0x%x (1271 PG10) support is obsolete",
644 wl->chip.id);
645
646 wl->quirks |= WLCORE_QUIRK_LEGACY_NVS |
647 WLCORE_QUIRK_DUAL_PROBE_TMPL |
648 WLCORE_QUIRK_TKIP_HEADER_SPACE |
649 WLCORE_QUIRK_START_STA_FAILS |
650 WLCORE_QUIRK_AP_ZERO_SESSION_ID;
651 wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
652 wl->mr_fw_name = WL127X_FW_NAME_MULTI;
653 memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x,
654 sizeof(wl->conf.mem));
655
656 /* read data preparation is only needed by wl127x */
657 wl->ops->prepare_read = wl127x_prepare_read;
658
659 wlcore_set_min_fw_ver(wl, WL127X_CHIP_VER,
660 WL127X_IFTYPE_SR_VER, WL127X_MAJOR_SR_VER,
661 WL127X_SUBTYPE_SR_VER, WL127X_MINOR_SR_VER,
662 WL127X_IFTYPE_MR_VER, WL127X_MAJOR_MR_VER,
663 WL127X_SUBTYPE_MR_VER, WL127X_MINOR_MR_VER);
664 break;
665
666 case CHIP_ID_127X_PG20:
667 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1271 PG20)",
668 wl->chip.id);
669
670 wl->quirks |= WLCORE_QUIRK_LEGACY_NVS |
671 WLCORE_QUIRK_DUAL_PROBE_TMPL |
672 WLCORE_QUIRK_TKIP_HEADER_SPACE |
673 WLCORE_QUIRK_START_STA_FAILS |
674 WLCORE_QUIRK_AP_ZERO_SESSION_ID;
675 wl->plt_fw_name = WL127X_PLT_FW_NAME;
676 wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
677 wl->mr_fw_name = WL127X_FW_NAME_MULTI;
678 memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x,
679 sizeof(wl->conf.mem));
680
681 /* read data preparation is only needed by wl127x */
682 wl->ops->prepare_read = wl127x_prepare_read;
683
684 wlcore_set_min_fw_ver(wl, WL127X_CHIP_VER,
685 WL127X_IFTYPE_SR_VER, WL127X_MAJOR_SR_VER,
686 WL127X_SUBTYPE_SR_VER, WL127X_MINOR_SR_VER,
687 WL127X_IFTYPE_MR_VER, WL127X_MAJOR_MR_VER,
688 WL127X_SUBTYPE_MR_VER, WL127X_MINOR_MR_VER);
689 break;
690
691 case CHIP_ID_128X_PG20:
692 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1283 PG20)",
693 wl->chip.id);
694 wl->plt_fw_name = WL128X_PLT_FW_NAME;
695 wl->sr_fw_name = WL128X_FW_NAME_SINGLE;
696 wl->mr_fw_name = WL128X_FW_NAME_MULTI;
697
698 /* wl128x requires TX blocksize alignment */
699 wl->quirks |= WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN |
700 WLCORE_QUIRK_DUAL_PROBE_TMPL |
701 WLCORE_QUIRK_TKIP_HEADER_SPACE |
702 WLCORE_QUIRK_START_STA_FAILS |
703 WLCORE_QUIRK_AP_ZERO_SESSION_ID;
704
705 wlcore_set_min_fw_ver(wl, WL128X_CHIP_VER,
706 WL128X_IFTYPE_SR_VER, WL128X_MAJOR_SR_VER,
707 WL128X_SUBTYPE_SR_VER, WL128X_MINOR_SR_VER,
708 WL128X_IFTYPE_MR_VER, WL128X_MAJOR_MR_VER,
709 WL128X_SUBTYPE_MR_VER, WL128X_MINOR_MR_VER);
710 break;
711 case CHIP_ID_128X_PG10:
712 default:
713 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
714 ret = -ENODEV;
715 goto out;
716 }
717
718 wl->fw_mem_block_size = 256;
719 wl->fwlog_end = 0x2000000;
720
721 /* common settings */
722 wl->scan_templ_id_2_4 = CMD_TEMPL_APP_PROBE_REQ_2_4_LEGACY;
723 wl->scan_templ_id_5 = CMD_TEMPL_APP_PROBE_REQ_5_LEGACY;
724 wl->sched_scan_templ_id_2_4 = CMD_TEMPL_CFG_PROBE_REQ_2_4;
725 wl->sched_scan_templ_id_5 = CMD_TEMPL_CFG_PROBE_REQ_5;
726 wl->max_channels_5 = WL12XX_MAX_CHANNELS_5GHZ;
727 wl->ba_rx_session_count_max = WL12XX_RX_BA_MAX_SESSIONS;
728 out:
729 return ret;
730 }
731
wl12xx_top_reg_write(struct wl1271 * wl,int addr,u16 val)732 static int __must_check wl12xx_top_reg_write(struct wl1271 *wl, int addr,
733 u16 val)
734 {
735 int ret;
736
737 /* write address >> 1 + 0x30000 to OCP_POR_CTR */
738 addr = (addr >> 1) + 0x30000;
739 ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr);
740 if (ret < 0)
741 goto out;
742
743 /* write value to OCP_POR_WDATA */
744 ret = wlcore_write32(wl, WL12XX_OCP_DATA_WRITE, val);
745 if (ret < 0)
746 goto out;
747
748 /* write 1 to OCP_CMD */
749 ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_WRITE);
750 if (ret < 0)
751 goto out;
752
753 out:
754 return ret;
755 }
756
wl12xx_top_reg_read(struct wl1271 * wl,int addr,u16 * out)757 static int __must_check wl12xx_top_reg_read(struct wl1271 *wl, int addr,
758 u16 *out)
759 {
760 u32 val;
761 int timeout = OCP_CMD_LOOP;
762 int ret;
763
764 /* write address >> 1 + 0x30000 to OCP_POR_CTR */
765 addr = (addr >> 1) + 0x30000;
766 ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr);
767 if (ret < 0)
768 return ret;
769
770 /* write 2 to OCP_CMD */
771 ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_READ);
772 if (ret < 0)
773 return ret;
774
775 /* poll for data ready */
776 do {
777 ret = wlcore_read32(wl, WL12XX_OCP_DATA_READ, &val);
778 if (ret < 0)
779 return ret;
780 } while (!(val & OCP_READY_MASK) && --timeout);
781
782 if (!timeout) {
783 wl1271_warning("Top register access timed out.");
784 return -ETIMEDOUT;
785 }
786
787 /* check data status and return if OK */
788 if ((val & OCP_STATUS_MASK) != OCP_STATUS_OK) {
789 wl1271_warning("Top register access returned error.");
790 return -EIO;
791 }
792
793 if (out)
794 *out = val & 0xffff;
795
796 return 0;
797 }
798
wl128x_switch_tcxo_to_fref(struct wl1271 * wl)799 static int wl128x_switch_tcxo_to_fref(struct wl1271 *wl)
800 {
801 u16 spare_reg;
802 int ret;
803
804 /* Mask bits [2] & [8:4] in the sys_clk_cfg register */
805 ret = wl12xx_top_reg_read(wl, WL_SPARE_REG, &spare_reg);
806 if (ret < 0)
807 return ret;
808
809 if (spare_reg == 0xFFFF)
810 return -EFAULT;
811 spare_reg |= (BIT(3) | BIT(5) | BIT(6));
812 ret = wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
813 if (ret < 0)
814 return ret;
815
816 /* Enable FREF_CLK_REQ & mux MCS and coex PLLs to FREF */
817 ret = wl12xx_top_reg_write(wl, SYS_CLK_CFG_REG,
818 WL_CLK_REQ_TYPE_PG2 | MCS_PLL_CLK_SEL_FREF);
819 if (ret < 0)
820 return ret;
821
822 /* Delay execution for 15msec, to let the HW settle */
823 mdelay(15);
824
825 return 0;
826 }
827
wl128x_is_tcxo_valid(struct wl1271 * wl)828 static bool wl128x_is_tcxo_valid(struct wl1271 *wl)
829 {
830 u16 tcxo_detection;
831 int ret;
832
833 ret = wl12xx_top_reg_read(wl, TCXO_CLK_DETECT_REG, &tcxo_detection);
834 if (ret < 0)
835 return false;
836
837 if (tcxo_detection & TCXO_DET_FAILED)
838 return false;
839
840 return true;
841 }
842
wl128x_is_fref_valid(struct wl1271 * wl)843 static bool wl128x_is_fref_valid(struct wl1271 *wl)
844 {
845 u16 fref_detection;
846 int ret;
847
848 ret = wl12xx_top_reg_read(wl, FREF_CLK_DETECT_REG, &fref_detection);
849 if (ret < 0)
850 return false;
851
852 if (fref_detection & FREF_CLK_DETECT_FAIL)
853 return false;
854
855 return true;
856 }
857
wl128x_manually_configure_mcs_pll(struct wl1271 * wl)858 static int wl128x_manually_configure_mcs_pll(struct wl1271 *wl)
859 {
860 int ret;
861
862 ret = wl12xx_top_reg_write(wl, MCS_PLL_M_REG, MCS_PLL_M_REG_VAL);
863 if (ret < 0)
864 goto out;
865
866 ret = wl12xx_top_reg_write(wl, MCS_PLL_N_REG, MCS_PLL_N_REG_VAL);
867 if (ret < 0)
868 goto out;
869
870 ret = wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG,
871 MCS_PLL_CONFIG_REG_VAL);
872
873 out:
874 return ret;
875 }
876
wl128x_configure_mcs_pll(struct wl1271 * wl,int clk)877 static int wl128x_configure_mcs_pll(struct wl1271 *wl, int clk)
878 {
879 u16 spare_reg;
880 u16 pll_config;
881 u8 input_freq;
882 struct wl12xx_priv *priv = wl->priv;
883 int ret;
884
885 /* Mask bits [3:1] in the sys_clk_cfg register */
886 ret = wl12xx_top_reg_read(wl, WL_SPARE_REG, &spare_reg);
887 if (ret < 0)
888 return ret;
889
890 if (spare_reg == 0xFFFF)
891 return -EFAULT;
892 spare_reg |= BIT(2);
893 ret = wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
894 if (ret < 0)
895 return ret;
896
897 /* Handle special cases of the TCXO clock */
898 if (priv->tcxo_clock == WL12XX_TCXOCLOCK_16_8 ||
899 priv->tcxo_clock == WL12XX_TCXOCLOCK_33_6)
900 return wl128x_manually_configure_mcs_pll(wl);
901
902 /* Set the input frequency according to the selected clock source */
903 input_freq = (clk & 1) + 1;
904
905 ret = wl12xx_top_reg_read(wl, MCS_PLL_CONFIG_REG, &pll_config);
906 if (ret < 0)
907 return ret;
908
909 if (pll_config == 0xFFFF)
910 return -EFAULT;
911 pll_config |= (input_freq << MCS_SEL_IN_FREQ_SHIFT);
912 pll_config |= MCS_PLL_ENABLE_HP;
913 ret = wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG, pll_config);
914
915 return ret;
916 }
917
918 /*
919 * WL128x has two clocks input - TCXO and FREF.
920 * TCXO is the main clock of the device, while FREF is used to sync
921 * between the GPS and the cellular modem.
922 * In cases where TCXO is 32.736MHz or 16.368MHz, the FREF will be used
923 * as the WLAN/BT main clock.
924 */
wl128x_boot_clk(struct wl1271 * wl,int * selected_clock)925 static int wl128x_boot_clk(struct wl1271 *wl, int *selected_clock)
926 {
927 struct wl12xx_priv *priv = wl->priv;
928 u16 sys_clk_cfg;
929 int ret;
930
931 /* For XTAL-only modes, FREF will be used after switching from TCXO */
932 if (priv->ref_clock == WL12XX_REFCLOCK_26_XTAL ||
933 priv->ref_clock == WL12XX_REFCLOCK_38_XTAL) {
934 if (!wl128x_switch_tcxo_to_fref(wl))
935 return -EINVAL;
936 goto fref_clk;
937 }
938
939 /* Query the HW, to determine which clock source we should use */
940 ret = wl12xx_top_reg_read(wl, SYS_CLK_CFG_REG, &sys_clk_cfg);
941 if (ret < 0)
942 return ret;
943
944 if (sys_clk_cfg == 0xFFFF)
945 return -EINVAL;
946 if (sys_clk_cfg & PRCM_CM_EN_MUX_WLAN_FREF)
947 goto fref_clk;
948
949 /* If TCXO is either 32.736MHz or 16.368MHz, switch to FREF */
950 if (priv->tcxo_clock == WL12XX_TCXOCLOCK_16_368 ||
951 priv->tcxo_clock == WL12XX_TCXOCLOCK_32_736) {
952 if (!wl128x_switch_tcxo_to_fref(wl))
953 return -EINVAL;
954 goto fref_clk;
955 }
956
957 /* TCXO clock is selected */
958 if (!wl128x_is_tcxo_valid(wl))
959 return -EINVAL;
960 *selected_clock = priv->tcxo_clock;
961 goto config_mcs_pll;
962
963 fref_clk:
964 /* FREF clock is selected */
965 if (!wl128x_is_fref_valid(wl))
966 return -EINVAL;
967 *selected_clock = priv->ref_clock;
968
969 config_mcs_pll:
970 return wl128x_configure_mcs_pll(wl, *selected_clock);
971 }
972
wl127x_boot_clk(struct wl1271 * wl)973 static int wl127x_boot_clk(struct wl1271 *wl)
974 {
975 struct wl12xx_priv *priv = wl->priv;
976 u32 pause;
977 u32 clk;
978 int ret;
979
980 if (WL127X_PG_GET_MAJOR(wl->hw_pg_ver) < 3)
981 wl->quirks |= WLCORE_QUIRK_END_OF_TRANSACTION;
982
983 if (priv->ref_clock == CONF_REF_CLK_19_2_E ||
984 priv->ref_clock == CONF_REF_CLK_38_4_E ||
985 priv->ref_clock == CONF_REF_CLK_38_4_M_XTAL)
986 /* ref clk: 19.2/38.4/38.4-XTAL */
987 clk = 0x3;
988 else if (priv->ref_clock == CONF_REF_CLK_26_E ||
989 priv->ref_clock == CONF_REF_CLK_26_M_XTAL ||
990 priv->ref_clock == CONF_REF_CLK_52_E)
991 /* ref clk: 26/52 */
992 clk = 0x5;
993 else
994 return -EINVAL;
995
996 if (priv->ref_clock != CONF_REF_CLK_19_2_E) {
997 u16 val;
998 /* Set clock type (open drain) */
999 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_TYPE, &val);
1000 if (ret < 0)
1001 goto out;
1002
1003 val &= FREF_CLK_TYPE_BITS;
1004 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
1005 if (ret < 0)
1006 goto out;
1007
1008 /* Set clock pull mode (no pull) */
1009 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_PULL, &val);
1010 if (ret < 0)
1011 goto out;
1012
1013 val |= NO_PULL;
1014 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_PULL, val);
1015 if (ret < 0)
1016 goto out;
1017 } else {
1018 u16 val;
1019 /* Set clock polarity */
1020 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_POLARITY, &val);
1021 if (ret < 0)
1022 goto out;
1023
1024 val &= FREF_CLK_POLARITY_BITS;
1025 val |= CLK_REQ_OUTN_SEL;
1026 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
1027 if (ret < 0)
1028 goto out;
1029 }
1030
1031 ret = wlcore_write32(wl, WL12XX_PLL_PARAMETERS, clk);
1032 if (ret < 0)
1033 goto out;
1034
1035 ret = wlcore_read32(wl, WL12XX_PLL_PARAMETERS, &pause);
1036 if (ret < 0)
1037 goto out;
1038
1039 wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
1040
1041 pause &= ~(WU_COUNTER_PAUSE_VAL);
1042 pause |= WU_COUNTER_PAUSE_VAL;
1043 ret = wlcore_write32(wl, WL12XX_WU_COUNTER_PAUSE, pause);
1044
1045 out:
1046 return ret;
1047 }
1048
wl1271_boot_soft_reset(struct wl1271 * wl)1049 static int wl1271_boot_soft_reset(struct wl1271 *wl)
1050 {
1051 unsigned long timeout;
1052 u32 boot_data;
1053 int ret = 0;
1054
1055 /* perform soft reset */
1056 ret = wlcore_write32(wl, WL12XX_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
1057 if (ret < 0)
1058 goto out;
1059
1060 /* SOFT_RESET is self clearing */
1061 timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
1062 while (1) {
1063 ret = wlcore_read32(wl, WL12XX_SLV_SOFT_RESET, &boot_data);
1064 if (ret < 0)
1065 goto out;
1066
1067 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
1068 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
1069 break;
1070
1071 if (time_after(jiffies, timeout)) {
1072 /* 1.2 check pWhalBus->uSelfClearTime if the
1073 * timeout was reached */
1074 wl1271_error("soft reset timeout");
1075 return -1;
1076 }
1077
1078 udelay(SOFT_RESET_STALL_TIME);
1079 }
1080
1081 /* disable Rx/Tx */
1082 ret = wlcore_write32(wl, WL12XX_ENABLE, 0x0);
1083 if (ret < 0)
1084 goto out;
1085
1086 /* disable auto calibration on start*/
1087 ret = wlcore_write32(wl, WL12XX_SPARE_A2, 0xffff);
1088
1089 out:
1090 return ret;
1091 }
1092
wl12xx_pre_boot(struct wl1271 * wl)1093 static int wl12xx_pre_boot(struct wl1271 *wl)
1094 {
1095 struct wl12xx_priv *priv = wl->priv;
1096 int ret = 0;
1097 u32 clk;
1098 int selected_clock = -1;
1099
1100 if (wl->chip.id == CHIP_ID_128X_PG20) {
1101 ret = wl128x_boot_clk(wl, &selected_clock);
1102 if (ret < 0)
1103 goto out;
1104 } else {
1105 ret = wl127x_boot_clk(wl);
1106 if (ret < 0)
1107 goto out;
1108 }
1109
1110 /* Continue the ELP wake up sequence */
1111 ret = wlcore_write32(wl, WL12XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
1112 if (ret < 0)
1113 goto out;
1114
1115 udelay(500);
1116
1117 ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
1118 if (ret < 0)
1119 goto out;
1120
1121 /* Read-modify-write DRPW_SCRATCH_START register (see next state)
1122 to be used by DRPw FW. The RTRIM value will be added by the FW
1123 before taking DRPw out of reset */
1124
1125 ret = wlcore_read32(wl, WL12XX_DRPW_SCRATCH_START, &clk);
1126 if (ret < 0)
1127 goto out;
1128
1129 wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
1130
1131 if (wl->chip.id == CHIP_ID_128X_PG20)
1132 clk |= ((selected_clock & 0x3) << 1) << 4;
1133 else
1134 clk |= (priv->ref_clock << 1) << 4;
1135
1136 ret = wlcore_write32(wl, WL12XX_DRPW_SCRATCH_START, clk);
1137 if (ret < 0)
1138 goto out;
1139
1140 ret = wlcore_set_partition(wl, &wl->ptable[PART_WORK]);
1141 if (ret < 0)
1142 goto out;
1143
1144 /* Disable interrupts */
1145 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
1146 if (ret < 0)
1147 goto out;
1148
1149 ret = wl1271_boot_soft_reset(wl);
1150 if (ret < 0)
1151 goto out;
1152
1153 out:
1154 return ret;
1155 }
1156
wl12xx_pre_upload(struct wl1271 * wl)1157 static int wl12xx_pre_upload(struct wl1271 *wl)
1158 {
1159 u32 tmp;
1160 u16 polarity;
1161 int ret;
1162
1163 /* write firmware's last address (ie. it's length) to
1164 * ACX_EEPROMLESS_IND_REG */
1165 wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
1166
1167 ret = wlcore_write32(wl, WL12XX_EEPROMLESS_IND, WL12XX_EEPROMLESS_IND);
1168 if (ret < 0)
1169 goto out;
1170
1171 ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &tmp);
1172 if (ret < 0)
1173 goto out;
1174
1175 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
1176
1177 /* 6. read the EEPROM parameters */
1178 ret = wlcore_read32(wl, WL12XX_SCR_PAD2, &tmp);
1179 if (ret < 0)
1180 goto out;
1181
1182 /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
1183 * to upload_fw) */
1184
1185 if (wl->chip.id == CHIP_ID_128X_PG20) {
1186 ret = wl12xx_top_reg_write(wl, SDIO_IO_DS, HCI_IO_DS_6MA);
1187 if (ret < 0)
1188 goto out;
1189 }
1190
1191 /* polarity must be set before the firmware is loaded */
1192 ret = wl12xx_top_reg_read(wl, OCP_REG_POLARITY, &polarity);
1193 if (ret < 0)
1194 goto out;
1195
1196 /* We use HIGH polarity, so unset the LOW bit */
1197 polarity &= ~POLARITY_LOW;
1198 ret = wl12xx_top_reg_write(wl, OCP_REG_POLARITY, polarity);
1199
1200 out:
1201 return ret;
1202 }
1203
wl12xx_enable_interrupts(struct wl1271 * wl)1204 static int wl12xx_enable_interrupts(struct wl1271 *wl)
1205 {
1206 int ret;
1207
1208 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
1209 WL12XX_ACX_ALL_EVENTS_VECTOR);
1210 if (ret < 0)
1211 goto out;
1212
1213 wlcore_enable_interrupts(wl);
1214 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
1215 WL1271_ACX_INTR_ALL & ~(WL12XX_INTR_MASK));
1216 if (ret < 0)
1217 goto disable_interrupts;
1218
1219 ret = wlcore_write32(wl, WL12XX_HI_CFG, HI_CFG_DEF_VAL);
1220 if (ret < 0)
1221 goto disable_interrupts;
1222
1223 return ret;
1224
1225 disable_interrupts:
1226 wlcore_disable_interrupts(wl);
1227
1228 out:
1229 return ret;
1230 }
1231
wl12xx_boot(struct wl1271 * wl)1232 static int wl12xx_boot(struct wl1271 *wl)
1233 {
1234 int ret;
1235
1236 ret = wl12xx_pre_boot(wl);
1237 if (ret < 0)
1238 goto out;
1239
1240 ret = wlcore_boot_upload_nvs(wl);
1241 if (ret < 0)
1242 goto out;
1243
1244 ret = wl12xx_pre_upload(wl);
1245 if (ret < 0)
1246 goto out;
1247
1248 ret = wlcore_boot_upload_firmware(wl);
1249 if (ret < 0)
1250 goto out;
1251
1252 wl->event_mask = BSS_LOSE_EVENT_ID |
1253 REGAINED_BSS_EVENT_ID |
1254 SCAN_COMPLETE_EVENT_ID |
1255 ROLE_STOP_COMPLETE_EVENT_ID |
1256 RSSI_SNR_TRIGGER_0_EVENT_ID |
1257 PSPOLL_DELIVERY_FAILURE_EVENT_ID |
1258 SOFT_GEMINI_SENSE_EVENT_ID |
1259 PERIODIC_SCAN_REPORT_EVENT_ID |
1260 PERIODIC_SCAN_COMPLETE_EVENT_ID |
1261 DUMMY_PACKET_EVENT_ID |
1262 PEER_REMOVE_COMPLETE_EVENT_ID |
1263 BA_SESSION_RX_CONSTRAINT_EVENT_ID |
1264 REMAIN_ON_CHANNEL_COMPLETE_EVENT_ID |
1265 INACTIVE_STA_EVENT_ID |
1266 CHANNEL_SWITCH_COMPLETE_EVENT_ID;
1267
1268 wl->ap_event_mask = MAX_TX_RETRY_EVENT_ID;
1269
1270 ret = wlcore_boot_run_firmware(wl);
1271 if (ret < 0)
1272 goto out;
1273
1274 ret = wl12xx_enable_interrupts(wl);
1275
1276 out:
1277 return ret;
1278 }
1279
wl12xx_trigger_cmd(struct wl1271 * wl,int cmd_box_addr,void * buf,size_t len)1280 static int wl12xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
1281 void *buf, size_t len)
1282 {
1283 int ret;
1284
1285 ret = wlcore_write(wl, cmd_box_addr, buf, len, false);
1286 if (ret < 0)
1287 return ret;
1288
1289 ret = wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL12XX_INTR_TRIG_CMD);
1290
1291 return ret;
1292 }
1293
wl12xx_ack_event(struct wl1271 * wl)1294 static int wl12xx_ack_event(struct wl1271 *wl)
1295 {
1296 return wlcore_write_reg(wl, REG_INTERRUPT_TRIG,
1297 WL12XX_INTR_TRIG_EVENT_ACK);
1298 }
1299
wl12xx_calc_tx_blocks(struct wl1271 * wl,u32 len,u32 spare_blks)1300 static u32 wl12xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
1301 {
1302 u32 blk_size = WL12XX_TX_HW_BLOCK_SIZE;
1303 u32 align_len = wlcore_calc_packet_alignment(wl, len);
1304
1305 return (align_len + blk_size - 1) / blk_size + spare_blks;
1306 }
1307
1308 static void
wl12xx_set_tx_desc_blocks(struct wl1271 * wl,struct wl1271_tx_hw_descr * desc,u32 blks,u32 spare_blks)1309 wl12xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1310 u32 blks, u32 spare_blks)
1311 {
1312 if (wl->chip.id == CHIP_ID_128X_PG20) {
1313 desc->wl128x_mem.total_mem_blocks = blks;
1314 } else {
1315 desc->wl127x_mem.extra_blocks = spare_blks;
1316 desc->wl127x_mem.total_mem_blocks = blks;
1317 }
1318 }
1319
1320 static void
wl12xx_set_tx_desc_data_len(struct wl1271 * wl,struct wl1271_tx_hw_descr * desc,struct sk_buff * skb)1321 wl12xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1322 struct sk_buff *skb)
1323 {
1324 u32 aligned_len = wlcore_calc_packet_alignment(wl, skb->len);
1325
1326 if (wl->chip.id == CHIP_ID_128X_PG20) {
1327 desc->wl128x_mem.extra_bytes = aligned_len - skb->len;
1328 desc->length = cpu_to_le16(aligned_len >> 2);
1329
1330 wl1271_debug(DEBUG_TX,
1331 "tx_fill_hdr: hlid: %d len: %d life: %d mem: %d extra: %d",
1332 desc->hlid,
1333 le16_to_cpu(desc->length),
1334 le16_to_cpu(desc->life_time),
1335 desc->wl128x_mem.total_mem_blocks,
1336 desc->wl128x_mem.extra_bytes);
1337 } else {
1338 /* calculate number of padding bytes */
1339 int pad = aligned_len - skb->len;
1340 desc->tx_attr |=
1341 cpu_to_le16(pad << TX_HW_ATTR_OFST_LAST_WORD_PAD);
1342
1343 /* Store the aligned length in terms of words */
1344 desc->length = cpu_to_le16(aligned_len >> 2);
1345
1346 wl1271_debug(DEBUG_TX,
1347 "tx_fill_hdr: pad: %d hlid: %d len: %d life: %d mem: %d",
1348 pad, desc->hlid,
1349 le16_to_cpu(desc->length),
1350 le16_to_cpu(desc->life_time),
1351 desc->wl127x_mem.total_mem_blocks);
1352 }
1353 }
1354
1355 static enum wl_rx_buf_align
wl12xx_get_rx_buf_align(struct wl1271 * wl,u32 rx_desc)1356 wl12xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
1357 {
1358 if (rx_desc & RX_BUF_UNALIGNED_PAYLOAD)
1359 return WLCORE_RX_BUF_UNALIGNED;
1360
1361 return WLCORE_RX_BUF_ALIGNED;
1362 }
1363
wl12xx_get_rx_packet_len(struct wl1271 * wl,void * rx_data,u32 data_len)1364 static u32 wl12xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
1365 u32 data_len)
1366 {
1367 struct wl1271_rx_descriptor *desc = rx_data;
1368
1369 /* invalid packet */
1370 if (data_len < sizeof(*desc) ||
1371 data_len < sizeof(*desc) + desc->pad_len)
1372 return 0;
1373
1374 return data_len - sizeof(*desc) - desc->pad_len;
1375 }
1376
wl12xx_tx_delayed_compl(struct wl1271 * wl)1377 static int wl12xx_tx_delayed_compl(struct wl1271 *wl)
1378 {
1379 if (wl->fw_status->tx_results_counter ==
1380 (wl->tx_results_count & 0xff))
1381 return 0;
1382
1383 return wlcore_tx_complete(wl);
1384 }
1385
wl12xx_hw_init(struct wl1271 * wl)1386 static int wl12xx_hw_init(struct wl1271 *wl)
1387 {
1388 int ret;
1389
1390 if (wl->chip.id == CHIP_ID_128X_PG20) {
1391 u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE;
1392
1393 ret = wl128x_cmd_general_parms(wl);
1394 if (ret < 0)
1395 goto out;
1396
1397 /*
1398 * If we are in calibrator based auto detect then we got the FEM nr
1399 * in wl->fem_manuf. No need to continue further
1400 */
1401 if (wl->plt_mode == PLT_FEM_DETECT)
1402 goto out;
1403
1404 ret = wl128x_cmd_radio_parms(wl);
1405 if (ret < 0)
1406 goto out;
1407
1408 if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN)
1409 /* Enable SDIO padding */
1410 host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
1411
1412 /* Must be before wl1271_acx_init_mem_config() */
1413 ret = wl1271_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap);
1414 if (ret < 0)
1415 goto out;
1416 } else {
1417 ret = wl1271_cmd_general_parms(wl);
1418 if (ret < 0)
1419 goto out;
1420
1421 /*
1422 * If we are in calibrator based auto detect then we got the FEM nr
1423 * in wl->fem_manuf. No need to continue further
1424 */
1425 if (wl->plt_mode == PLT_FEM_DETECT)
1426 goto out;
1427
1428 ret = wl1271_cmd_radio_parms(wl);
1429 if (ret < 0)
1430 goto out;
1431 ret = wl1271_cmd_ext_radio_parms(wl);
1432 if (ret < 0)
1433 goto out;
1434 }
1435 out:
1436 return ret;
1437 }
1438
wl12xx_convert_fw_status(struct wl1271 * wl,void * raw_fw_status,struct wl_fw_status * fw_status)1439 static void wl12xx_convert_fw_status(struct wl1271 *wl, void *raw_fw_status,
1440 struct wl_fw_status *fw_status)
1441 {
1442 struct wl12xx_fw_status *int_fw_status = raw_fw_status;
1443
1444 fw_status->intr = le32_to_cpu(int_fw_status->intr);
1445 fw_status->fw_rx_counter = int_fw_status->fw_rx_counter;
1446 fw_status->drv_rx_counter = int_fw_status->drv_rx_counter;
1447 fw_status->tx_results_counter = int_fw_status->tx_results_counter;
1448 fw_status->rx_pkt_descs = int_fw_status->rx_pkt_descs;
1449
1450 fw_status->fw_localtime = le32_to_cpu(int_fw_status->fw_localtime);
1451 fw_status->link_ps_bitmap = le32_to_cpu(int_fw_status->link_ps_bitmap);
1452 fw_status->link_fast_bitmap =
1453 le32_to_cpu(int_fw_status->link_fast_bitmap);
1454 fw_status->total_released_blks =
1455 le32_to_cpu(int_fw_status->total_released_blks);
1456 fw_status->tx_total = le32_to_cpu(int_fw_status->tx_total);
1457
1458 fw_status->counters.tx_released_pkts =
1459 int_fw_status->counters.tx_released_pkts;
1460 fw_status->counters.tx_lnk_free_pkts =
1461 int_fw_status->counters.tx_lnk_free_pkts;
1462 fw_status->counters.tx_voice_released_blks =
1463 int_fw_status->counters.tx_voice_released_blks;
1464 fw_status->counters.tx_last_rate =
1465 int_fw_status->counters.tx_last_rate;
1466
1467 fw_status->log_start_addr = le32_to_cpu(int_fw_status->log_start_addr);
1468 }
1469
wl12xx_sta_get_ap_rate_mask(struct wl1271 * wl,struct wl12xx_vif * wlvif)1470 static u32 wl12xx_sta_get_ap_rate_mask(struct wl1271 *wl,
1471 struct wl12xx_vif *wlvif)
1472 {
1473 return wlvif->rate_set;
1474 }
1475
wl12xx_conf_init(struct wl1271 * wl)1476 static void wl12xx_conf_init(struct wl1271 *wl)
1477 {
1478 struct wl12xx_priv *priv = wl->priv;
1479
1480 /* apply driver default configuration */
1481 memcpy(&wl->conf, &wl12xx_conf, sizeof(wl12xx_conf));
1482
1483 /* apply default private configuration */
1484 memcpy(&priv->conf, &wl12xx_default_priv_conf, sizeof(priv->conf));
1485 }
1486
wl12xx_mac_in_fuse(struct wl1271 * wl)1487 static bool wl12xx_mac_in_fuse(struct wl1271 *wl)
1488 {
1489 bool supported = false;
1490 u8 major, minor;
1491
1492 if (wl->chip.id == CHIP_ID_128X_PG20) {
1493 major = WL128X_PG_GET_MAJOR(wl->hw_pg_ver);
1494 minor = WL128X_PG_GET_MINOR(wl->hw_pg_ver);
1495
1496 /* in wl128x we have the MAC address if the PG is >= (2, 1) */
1497 if (major > 2 || (major == 2 && minor >= 1))
1498 supported = true;
1499 } else {
1500 major = WL127X_PG_GET_MAJOR(wl->hw_pg_ver);
1501 minor = WL127X_PG_GET_MINOR(wl->hw_pg_ver);
1502
1503 /* in wl127x we have the MAC address if the PG is >= (3, 1) */
1504 if (major == 3 && minor >= 1)
1505 supported = true;
1506 }
1507
1508 wl1271_debug(DEBUG_PROBE,
1509 "PG Ver major = %d minor = %d, MAC %s present",
1510 major, minor, supported ? "is" : "is not");
1511
1512 return supported;
1513 }
1514
wl12xx_get_fuse_mac(struct wl1271 * wl)1515 static int wl12xx_get_fuse_mac(struct wl1271 *wl)
1516 {
1517 u32 mac1, mac2;
1518 int ret;
1519
1520 ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
1521 if (ret < 0)
1522 goto out;
1523
1524 ret = wlcore_read32(wl, WL12XX_REG_FUSE_BD_ADDR_1, &mac1);
1525 if (ret < 0)
1526 goto out;
1527
1528 ret = wlcore_read32(wl, WL12XX_REG_FUSE_BD_ADDR_2, &mac2);
1529 if (ret < 0)
1530 goto out;
1531
1532 /* these are the two parts of the BD_ADDR */
1533 wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
1534 ((mac1 & 0xff000000) >> 24);
1535 wl->fuse_nic_addr = mac1 & 0xffffff;
1536
1537 ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
1538
1539 out:
1540 return ret;
1541 }
1542
wl12xx_get_pg_ver(struct wl1271 * wl,s8 * ver)1543 static int wl12xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
1544 {
1545 u16 die_info;
1546 int ret;
1547
1548 if (wl->chip.id == CHIP_ID_128X_PG20)
1549 ret = wl12xx_top_reg_read(wl, WL128X_REG_FUSE_DATA_2_1,
1550 &die_info);
1551 else
1552 ret = wl12xx_top_reg_read(wl, WL127X_REG_FUSE_DATA_2_1,
1553 &die_info);
1554
1555 if (ret >= 0 && ver)
1556 *ver = (s8)((die_info & PG_VER_MASK) >> PG_VER_OFFSET);
1557
1558 return ret;
1559 }
1560
wl12xx_get_mac(struct wl1271 * wl)1561 static int wl12xx_get_mac(struct wl1271 *wl)
1562 {
1563 if (wl12xx_mac_in_fuse(wl))
1564 return wl12xx_get_fuse_mac(wl);
1565
1566 return 0;
1567 }
1568
wl12xx_set_tx_desc_csum(struct wl1271 * wl,struct wl1271_tx_hw_descr * desc,struct sk_buff * skb)1569 static void wl12xx_set_tx_desc_csum(struct wl1271 *wl,
1570 struct wl1271_tx_hw_descr *desc,
1571 struct sk_buff *skb)
1572 {
1573 desc->wl12xx_reserved = 0;
1574 }
1575
wl12xx_plt_init(struct wl1271 * wl)1576 static int wl12xx_plt_init(struct wl1271 *wl)
1577 {
1578 int ret;
1579
1580 ret = wl->ops->boot(wl);
1581 if (ret < 0)
1582 goto out;
1583
1584 ret = wl->ops->hw_init(wl);
1585 if (ret < 0)
1586 goto out_irq_disable;
1587
1588 /*
1589 * If we are in calibrator based auto detect then we got the FEM nr
1590 * in wl->fem_manuf. No need to continue further
1591 */
1592 if (wl->plt_mode == PLT_FEM_DETECT)
1593 goto out;
1594
1595 ret = wl1271_acx_init_mem_config(wl);
1596 if (ret < 0)
1597 goto out_irq_disable;
1598
1599 ret = wl12xx_acx_mem_cfg(wl);
1600 if (ret < 0)
1601 goto out_free_memmap;
1602
1603 /* Enable data path */
1604 ret = wl1271_cmd_data_path(wl, 1);
1605 if (ret < 0)
1606 goto out_free_memmap;
1607
1608 /* Configure for CAM power saving (ie. always active) */
1609 ret = wl1271_acx_sleep_auth(wl, WL1271_PSM_CAM);
1610 if (ret < 0)
1611 goto out_free_memmap;
1612
1613 /* configure PM */
1614 ret = wl1271_acx_pm_config(wl);
1615 if (ret < 0)
1616 goto out_free_memmap;
1617
1618 goto out;
1619
1620 out_free_memmap:
1621 kfree(wl->target_mem_map);
1622 wl->target_mem_map = NULL;
1623
1624 out_irq_disable:
1625 mutex_unlock(&wl->mutex);
1626 /* Unlocking the mutex in the middle of handling is
1627 inherently unsafe. In this case we deem it safe to do,
1628 because we need to let any possibly pending IRQ out of
1629 the system (and while we are WL1271_STATE_OFF the IRQ
1630 work function will not do anything.) Also, any other
1631 possible concurrent operations will fail due to the
1632 current state, hence the wl1271 struct should be safe. */
1633 wlcore_disable_interrupts(wl);
1634 mutex_lock(&wl->mutex);
1635 out:
1636 return ret;
1637 }
1638
wl12xx_get_spare_blocks(struct wl1271 * wl,bool is_gem)1639 static int wl12xx_get_spare_blocks(struct wl1271 *wl, bool is_gem)
1640 {
1641 if (is_gem)
1642 return WL12XX_TX_HW_BLOCK_GEM_SPARE;
1643
1644 return WL12XX_TX_HW_BLOCK_SPARE_DEFAULT;
1645 }
1646
wl12xx_set_key(struct wl1271 * wl,enum set_key_cmd cmd,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct ieee80211_key_conf * key_conf)1647 static int wl12xx_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
1648 struct ieee80211_vif *vif,
1649 struct ieee80211_sta *sta,
1650 struct ieee80211_key_conf *key_conf)
1651 {
1652 return wlcore_set_key(wl, cmd, vif, sta, key_conf);
1653 }
1654
wl12xx_set_peer_cap(struct wl1271 * wl,struct ieee80211_sta_ht_cap * ht_cap,bool allow_ht_operation,u32 rate_set,u8 hlid)1655 static int wl12xx_set_peer_cap(struct wl1271 *wl,
1656 struct ieee80211_sta_ht_cap *ht_cap,
1657 bool allow_ht_operation,
1658 u32 rate_set, u8 hlid)
1659 {
1660 return wl1271_acx_set_ht_capabilities(wl, ht_cap, allow_ht_operation,
1661 hlid);
1662 }
1663
wl12xx_lnk_high_prio(struct wl1271 * wl,u8 hlid,struct wl1271_link * lnk)1664 static bool wl12xx_lnk_high_prio(struct wl1271 *wl, u8 hlid,
1665 struct wl1271_link *lnk)
1666 {
1667 u8 thold;
1668
1669 if (test_bit(hlid, &wl->fw_fast_lnk_map))
1670 thold = wl->conf.tx.fast_link_thold;
1671 else
1672 thold = wl->conf.tx.slow_link_thold;
1673
1674 return lnk->allocated_pkts < thold;
1675 }
1676
wl12xx_lnk_low_prio(struct wl1271 * wl,u8 hlid,struct wl1271_link * lnk)1677 static bool wl12xx_lnk_low_prio(struct wl1271 *wl, u8 hlid,
1678 struct wl1271_link *lnk)
1679 {
1680 /* any link is good for low priority */
1681 return true;
1682 }
1683
wl12xx_convert_hwaddr(struct wl1271 * wl,u32 hwaddr)1684 static u32 wl12xx_convert_hwaddr(struct wl1271 *wl, u32 hwaddr)
1685 {
1686 return hwaddr << 5;
1687 }
1688
1689 static int wl12xx_setup(struct wl1271 *wl);
1690
1691 static struct wlcore_ops wl12xx_ops = {
1692 .setup = wl12xx_setup,
1693 .identify_chip = wl12xx_identify_chip,
1694 .boot = wl12xx_boot,
1695 .plt_init = wl12xx_plt_init,
1696 .trigger_cmd = wl12xx_trigger_cmd,
1697 .ack_event = wl12xx_ack_event,
1698 .wait_for_event = wl12xx_wait_for_event,
1699 .process_mailbox_events = wl12xx_process_mailbox_events,
1700 .calc_tx_blocks = wl12xx_calc_tx_blocks,
1701 .set_tx_desc_blocks = wl12xx_set_tx_desc_blocks,
1702 .set_tx_desc_data_len = wl12xx_set_tx_desc_data_len,
1703 .get_rx_buf_align = wl12xx_get_rx_buf_align,
1704 .get_rx_packet_len = wl12xx_get_rx_packet_len,
1705 .tx_immediate_compl = NULL,
1706 .tx_delayed_compl = wl12xx_tx_delayed_compl,
1707 .hw_init = wl12xx_hw_init,
1708 .init_vif = NULL,
1709 .convert_fw_status = wl12xx_convert_fw_status,
1710 .sta_get_ap_rate_mask = wl12xx_sta_get_ap_rate_mask,
1711 .get_pg_ver = wl12xx_get_pg_ver,
1712 .get_mac = wl12xx_get_mac,
1713 .set_tx_desc_csum = wl12xx_set_tx_desc_csum,
1714 .set_rx_csum = NULL,
1715 .ap_get_mimo_wide_rate_mask = NULL,
1716 .debugfs_init = wl12xx_debugfs_add_files,
1717 .scan_start = wl12xx_scan_start,
1718 .scan_stop = wl12xx_scan_stop,
1719 .sched_scan_start = wl12xx_sched_scan_start,
1720 .sched_scan_stop = wl12xx_scan_sched_scan_stop,
1721 .get_spare_blocks = wl12xx_get_spare_blocks,
1722 .set_key = wl12xx_set_key,
1723 .channel_switch = wl12xx_cmd_channel_switch,
1724 .pre_pkt_send = NULL,
1725 .set_peer_cap = wl12xx_set_peer_cap,
1726 .convert_hwaddr = wl12xx_convert_hwaddr,
1727 .lnk_high_prio = wl12xx_lnk_high_prio,
1728 .lnk_low_prio = wl12xx_lnk_low_prio,
1729 };
1730
1731 static struct ieee80211_sta_ht_cap wl12xx_ht_cap = {
1732 .cap = IEEE80211_HT_CAP_GRN_FLD | IEEE80211_HT_CAP_SGI_20 |
1733 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT),
1734 .ht_supported = true,
1735 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_8K,
1736 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_8,
1737 .mcs = {
1738 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1739 .rx_highest = cpu_to_le16(72),
1740 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1741 },
1742 };
1743
1744 static const struct ieee80211_iface_limit wl12xx_iface_limits[] = {
1745 {
1746 .max = 3,
1747 .types = BIT(NL80211_IFTYPE_STATION),
1748 },
1749 {
1750 .max = 1,
1751 .types = BIT(NL80211_IFTYPE_AP) |
1752 BIT(NL80211_IFTYPE_P2P_GO) |
1753 BIT(NL80211_IFTYPE_P2P_CLIENT),
1754 },
1755 };
1756
1757 static const struct ieee80211_iface_combination
1758 wl12xx_iface_combinations[] = {
1759 {
1760 .max_interfaces = 3,
1761 .limits = wl12xx_iface_limits,
1762 .n_limits = ARRAY_SIZE(wl12xx_iface_limits),
1763 .num_different_channels = 1,
1764 },
1765 };
1766
1767 static const struct wl12xx_clock wl12xx_refclock_table[] = {
1768 { 19200000, false, WL12XX_REFCLOCK_19 },
1769 { 26000000, false, WL12XX_REFCLOCK_26 },
1770 { 26000000, true, WL12XX_REFCLOCK_26_XTAL },
1771 { 38400000, false, WL12XX_REFCLOCK_38 },
1772 { 38400000, true, WL12XX_REFCLOCK_38_XTAL },
1773 { 52000000, false, WL12XX_REFCLOCK_52 },
1774 { 0, false, 0 }
1775 };
1776
1777 static const struct wl12xx_clock wl12xx_tcxoclock_table[] = {
1778 { 16368000, true, WL12XX_TCXOCLOCK_16_368 },
1779 { 16800000, true, WL12XX_TCXOCLOCK_16_8 },
1780 { 19200000, true, WL12XX_TCXOCLOCK_19_2 },
1781 { 26000000, true, WL12XX_TCXOCLOCK_26 },
1782 { 32736000, true, WL12XX_TCXOCLOCK_32_736 },
1783 { 33600000, true, WL12XX_TCXOCLOCK_33_6 },
1784 { 38400000, true, WL12XX_TCXOCLOCK_38_4 },
1785 { 52000000, true, WL12XX_TCXOCLOCK_52 },
1786 { 0, false, 0 }
1787 };
1788
wl12xx_get_clock_idx(const struct wl12xx_clock * table,u32 freq,bool xtal)1789 static int wl12xx_get_clock_idx(const struct wl12xx_clock *table,
1790 u32 freq, bool xtal)
1791 {
1792 int i;
1793
1794 for (i = 0; table[i].freq != 0; i++)
1795 if ((table[i].freq == freq) && (table[i].xtal == xtal))
1796 return table[i].hw_idx;
1797
1798 return -EINVAL;
1799 }
1800
wl12xx_setup(struct wl1271 * wl)1801 static int wl12xx_setup(struct wl1271 *wl)
1802 {
1803 struct wl12xx_priv *priv = wl->priv;
1804 struct wlcore_platdev_data *pdev_data = dev_get_platdata(&wl->pdev->dev);
1805
1806 BUILD_BUG_ON(WL12XX_MAX_LINKS > WLCORE_MAX_LINKS);
1807 BUILD_BUG_ON(WL12XX_MAX_AP_STATIONS > WL12XX_MAX_LINKS);
1808
1809 wl->rtable = wl12xx_rtable;
1810 wl->num_tx_desc = WL12XX_NUM_TX_DESCRIPTORS;
1811 wl->num_rx_desc = WL12XX_NUM_RX_DESCRIPTORS;
1812 wl->num_links = WL12XX_MAX_LINKS;
1813 wl->max_ap_stations = WL12XX_MAX_AP_STATIONS;
1814 wl->iface_combinations = wl12xx_iface_combinations;
1815 wl->n_iface_combinations = ARRAY_SIZE(wl12xx_iface_combinations);
1816 wl->num_mac_addr = WL12XX_NUM_MAC_ADDRESSES;
1817 wl->band_rate_to_idx = wl12xx_band_rate_to_idx;
1818 wl->hw_tx_rate_tbl_size = WL12XX_CONF_HW_RXTX_RATE_MAX;
1819 wl->hw_min_ht_rate = WL12XX_CONF_HW_RXTX_RATE_MCS0;
1820 wl->fw_status_len = sizeof(struct wl12xx_fw_status);
1821 wl->fw_status_priv_len = 0;
1822 wl->stats.fw_stats_len = sizeof(struct wl12xx_acx_statistics);
1823 wl->ofdm_only_ap = true;
1824 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ, &wl12xx_ht_cap);
1825 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ, &wl12xx_ht_cap);
1826 wl12xx_conf_init(wl);
1827
1828 if (!fref_param) {
1829 priv->ref_clock = wl12xx_get_clock_idx(wl12xx_refclock_table,
1830 pdev_data->ref_clock_freq,
1831 pdev_data->ref_clock_xtal);
1832 if (priv->ref_clock < 0) {
1833 wl1271_error("Invalid ref_clock frequency (%d Hz, %s)",
1834 pdev_data->ref_clock_freq,
1835 pdev_data->ref_clock_xtal ?
1836 "XTAL" : "not XTAL");
1837
1838 return priv->ref_clock;
1839 }
1840 } else {
1841 if (!strcmp(fref_param, "19.2"))
1842 priv->ref_clock = WL12XX_REFCLOCK_19;
1843 else if (!strcmp(fref_param, "26"))
1844 priv->ref_clock = WL12XX_REFCLOCK_26;
1845 else if (!strcmp(fref_param, "26x"))
1846 priv->ref_clock = WL12XX_REFCLOCK_26_XTAL;
1847 else if (!strcmp(fref_param, "38.4"))
1848 priv->ref_clock = WL12XX_REFCLOCK_38;
1849 else if (!strcmp(fref_param, "38.4x"))
1850 priv->ref_clock = WL12XX_REFCLOCK_38_XTAL;
1851 else if (!strcmp(fref_param, "52"))
1852 priv->ref_clock = WL12XX_REFCLOCK_52;
1853 else
1854 wl1271_error("Invalid fref parameter %s", fref_param);
1855 }
1856
1857 if (!tcxo_param && pdev_data->tcxo_clock_freq) {
1858 priv->tcxo_clock = wl12xx_get_clock_idx(wl12xx_tcxoclock_table,
1859 pdev_data->tcxo_clock_freq,
1860 true);
1861 if (priv->tcxo_clock < 0) {
1862 wl1271_error("Invalid tcxo_clock frequency (%d Hz)",
1863 pdev_data->tcxo_clock_freq);
1864
1865 return priv->tcxo_clock;
1866 }
1867 } else if (tcxo_param) {
1868 if (!strcmp(tcxo_param, "19.2"))
1869 priv->tcxo_clock = WL12XX_TCXOCLOCK_19_2;
1870 else if (!strcmp(tcxo_param, "26"))
1871 priv->tcxo_clock = WL12XX_TCXOCLOCK_26;
1872 else if (!strcmp(tcxo_param, "38.4"))
1873 priv->tcxo_clock = WL12XX_TCXOCLOCK_38_4;
1874 else if (!strcmp(tcxo_param, "52"))
1875 priv->tcxo_clock = WL12XX_TCXOCLOCK_52;
1876 else if (!strcmp(tcxo_param, "16.368"))
1877 priv->tcxo_clock = WL12XX_TCXOCLOCK_16_368;
1878 else if (!strcmp(tcxo_param, "32.736"))
1879 priv->tcxo_clock = WL12XX_TCXOCLOCK_32_736;
1880 else if (!strcmp(tcxo_param, "16.8"))
1881 priv->tcxo_clock = WL12XX_TCXOCLOCK_16_8;
1882 else if (!strcmp(tcxo_param, "33.6"))
1883 priv->tcxo_clock = WL12XX_TCXOCLOCK_33_6;
1884 else
1885 wl1271_error("Invalid tcxo parameter %s", tcxo_param);
1886 }
1887
1888 priv->rx_mem_addr = kmalloc(sizeof(*priv->rx_mem_addr), GFP_KERNEL);
1889 if (!priv->rx_mem_addr)
1890 return -ENOMEM;
1891
1892 return 0;
1893 }
1894
wl12xx_probe(struct platform_device * pdev)1895 static int wl12xx_probe(struct platform_device *pdev)
1896 {
1897 struct wl1271 *wl;
1898 struct ieee80211_hw *hw;
1899 int ret;
1900
1901 hw = wlcore_alloc_hw(sizeof(struct wl12xx_priv),
1902 WL12XX_AGGR_BUFFER_SIZE,
1903 sizeof(struct wl12xx_event_mailbox));
1904 if (IS_ERR(hw)) {
1905 wl1271_error("can't allocate hw");
1906 ret = PTR_ERR(hw);
1907 goto out;
1908 }
1909
1910 wl = hw->priv;
1911 wl->ops = &wl12xx_ops;
1912 wl->ptable = wl12xx_ptable;
1913 ret = wlcore_probe(wl, pdev);
1914 if (ret)
1915 goto out_free;
1916
1917 return ret;
1918
1919 out_free:
1920 wlcore_free_hw(wl);
1921 out:
1922 return ret;
1923 }
1924
wl12xx_remove(struct platform_device * pdev)1925 static int wl12xx_remove(struct platform_device *pdev)
1926 {
1927 struct wl1271 *wl = platform_get_drvdata(pdev);
1928 struct wl12xx_priv *priv;
1929
1930 if (!wl)
1931 goto out;
1932 priv = wl->priv;
1933
1934 kfree(priv->rx_mem_addr);
1935
1936 out:
1937 return wlcore_remove(pdev);
1938 }
1939
1940 static const struct platform_device_id wl12xx_id_table[] = {
1941 { "wl12xx", 0 },
1942 { } /* Terminating Entry */
1943 };
1944 MODULE_DEVICE_TABLE(platform, wl12xx_id_table);
1945
1946 static struct platform_driver wl12xx_driver = {
1947 .probe = wl12xx_probe,
1948 .remove = wl12xx_remove,
1949 .id_table = wl12xx_id_table,
1950 .driver = {
1951 .name = "wl12xx_driver",
1952 .owner = THIS_MODULE,
1953 }
1954 };
1955
1956 module_platform_driver(wl12xx_driver);
1957
1958 module_param_named(fref, fref_param, charp, 0);
1959 MODULE_PARM_DESC(fref, "FREF clock: 19.2, 26, 26x, 38.4, 38.4x, 52");
1960
1961 module_param_named(tcxo, tcxo_param, charp, 0);
1962 MODULE_PARM_DESC(tcxo,
1963 "TCXO clock: 19.2, 26, 38.4, 52, 16.368, 32.736, 16.8, 33.6");
1964
1965 MODULE_LICENSE("GPL v2");
1966 MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
1967 MODULE_FIRMWARE(WL127X_FW_NAME_SINGLE);
1968 MODULE_FIRMWARE(WL127X_FW_NAME_MULTI);
1969 MODULE_FIRMWARE(WL127X_PLT_FW_NAME);
1970 MODULE_FIRMWARE(WL128X_FW_NAME_SINGLE);
1971 MODULE_FIRMWARE(WL128X_FW_NAME_MULTI);
1972 MODULE_FIRMWARE(WL128X_PLT_FW_NAME);
1973