1 /*
2 * pci-rcar-gen2: internal PCI bus support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Cogent Embedded, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/delay.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/of_pci.h>
19 #include <linux/pci.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/sizes.h>
23 #include <linux/slab.h>
24
25 /* AHB-PCI Bridge PCI communication registers */
26 #define RCAR_AHBPCI_PCICOM_OFFSET 0x800
27
28 #define RCAR_PCIAHB_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x00)
29 #define RCAR_PCIAHB_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x04)
30 #define RCAR_PCIAHB_PREFETCH0 0x0
31 #define RCAR_PCIAHB_PREFETCH4 0x1
32 #define RCAR_PCIAHB_PREFETCH8 0x2
33 #define RCAR_PCIAHB_PREFETCH16 0x3
34
35 #define RCAR_AHBPCI_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x10)
36 #define RCAR_AHBPCI_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x14)
37 #define RCAR_AHBPCI_WIN_CTR_MEM (3 << 1)
38 #define RCAR_AHBPCI_WIN_CTR_CFG (5 << 1)
39 #define RCAR_AHBPCI_WIN1_HOST (1 << 30)
40 #define RCAR_AHBPCI_WIN1_DEVICE (1 << 31)
41
42 #define RCAR_PCI_INT_ENABLE_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x20)
43 #define RCAR_PCI_INT_STATUS_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x24)
44 #define RCAR_PCI_INT_SIGTABORT (1 << 0)
45 #define RCAR_PCI_INT_SIGRETABORT (1 << 1)
46 #define RCAR_PCI_INT_REMABORT (1 << 2)
47 #define RCAR_PCI_INT_PERR (1 << 3)
48 #define RCAR_PCI_INT_SIGSERR (1 << 4)
49 #define RCAR_PCI_INT_RESERR (1 << 5)
50 #define RCAR_PCI_INT_WIN1ERR (1 << 12)
51 #define RCAR_PCI_INT_WIN2ERR (1 << 13)
52 #define RCAR_PCI_INT_A (1 << 16)
53 #define RCAR_PCI_INT_B (1 << 17)
54 #define RCAR_PCI_INT_PME (1 << 19)
55 #define RCAR_PCI_INT_ALLERRORS (RCAR_PCI_INT_SIGTABORT | \
56 RCAR_PCI_INT_SIGRETABORT | \
57 RCAR_PCI_INT_SIGRETABORT | \
58 RCAR_PCI_INT_REMABORT | \
59 RCAR_PCI_INT_PERR | \
60 RCAR_PCI_INT_SIGSERR | \
61 RCAR_PCI_INT_RESERR | \
62 RCAR_PCI_INT_WIN1ERR | \
63 RCAR_PCI_INT_WIN2ERR)
64
65 #define RCAR_AHB_BUS_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x30)
66 #define RCAR_AHB_BUS_MMODE_HTRANS (1 << 0)
67 #define RCAR_AHB_BUS_MMODE_BYTE_BURST (1 << 1)
68 #define RCAR_AHB_BUS_MMODE_WR_INCR (1 << 2)
69 #define RCAR_AHB_BUS_MMODE_HBUS_REQ (1 << 7)
70 #define RCAR_AHB_BUS_SMODE_READYCTR (1 << 17)
71 #define RCAR_AHB_BUS_MODE (RCAR_AHB_BUS_MMODE_HTRANS | \
72 RCAR_AHB_BUS_MMODE_BYTE_BURST | \
73 RCAR_AHB_BUS_MMODE_WR_INCR | \
74 RCAR_AHB_BUS_MMODE_HBUS_REQ | \
75 RCAR_AHB_BUS_SMODE_READYCTR)
76
77 #define RCAR_USBCTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x34)
78 #define RCAR_USBCTR_USBH_RST (1 << 0)
79 #define RCAR_USBCTR_PCICLK_MASK (1 << 1)
80 #define RCAR_USBCTR_PLL_RST (1 << 2)
81 #define RCAR_USBCTR_DIRPD (1 << 8)
82 #define RCAR_USBCTR_PCIAHB_WIN2_EN (1 << 9)
83 #define RCAR_USBCTR_PCIAHB_WIN1_256M (0 << 10)
84 #define RCAR_USBCTR_PCIAHB_WIN1_512M (1 << 10)
85 #define RCAR_USBCTR_PCIAHB_WIN1_1G (2 << 10)
86 #define RCAR_USBCTR_PCIAHB_WIN1_2G (3 << 10)
87 #define RCAR_USBCTR_PCIAHB_WIN1_MASK (3 << 10)
88
89 #define RCAR_PCI_ARBITER_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x40)
90 #define RCAR_PCI_ARBITER_PCIREQ0 (1 << 0)
91 #define RCAR_PCI_ARBITER_PCIREQ1 (1 << 1)
92 #define RCAR_PCI_ARBITER_PCIBP_MODE (1 << 12)
93
94 #define RCAR_PCI_UNIT_REV_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x48)
95
96 struct rcar_pci_priv {
97 struct device *dev;
98 void __iomem *reg;
99 struct resource io_res;
100 struct resource mem_res;
101 struct resource *cfg_res;
102 unsigned busnr;
103 int irq;
104 unsigned long window_size;
105 };
106
107 /* PCI configuration space operations */
rcar_pci_cfg_base(struct pci_bus * bus,unsigned int devfn,int where)108 static void __iomem *rcar_pci_cfg_base(struct pci_bus *bus, unsigned int devfn,
109 int where)
110 {
111 struct pci_sys_data *sys = bus->sysdata;
112 struct rcar_pci_priv *priv = sys->private_data;
113 int slot, val;
114
115 if (sys->busnr != bus->number || PCI_FUNC(devfn))
116 return NULL;
117
118 /* Only one EHCI/OHCI device built-in */
119 slot = PCI_SLOT(devfn);
120 if (slot > 2)
121 return NULL;
122
123 /* bridge logic only has registers to 0x40 */
124 if (slot == 0x0 && where >= 0x40)
125 return NULL;
126
127 val = slot ? RCAR_AHBPCI_WIN1_DEVICE | RCAR_AHBPCI_WIN_CTR_CFG :
128 RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG;
129
130 iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG);
131 return priv->reg + (slot >> 1) * 0x100 + where;
132 }
133
rcar_pci_read_config(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * val)134 static int rcar_pci_read_config(struct pci_bus *bus, unsigned int devfn,
135 int where, int size, u32 *val)
136 {
137 void __iomem *reg = rcar_pci_cfg_base(bus, devfn, where);
138
139 if (!reg)
140 return PCIBIOS_DEVICE_NOT_FOUND;
141
142 switch (size) {
143 case 1:
144 *val = ioread8(reg);
145 break;
146 case 2:
147 *val = ioread16(reg);
148 break;
149 default:
150 *val = ioread32(reg);
151 break;
152 }
153
154 return PCIBIOS_SUCCESSFUL;
155 }
156
rcar_pci_write_config(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 val)157 static int rcar_pci_write_config(struct pci_bus *bus, unsigned int devfn,
158 int where, int size, u32 val)
159 {
160 void __iomem *reg = rcar_pci_cfg_base(bus, devfn, where);
161
162 if (!reg)
163 return PCIBIOS_DEVICE_NOT_FOUND;
164
165 switch (size) {
166 case 1:
167 iowrite8(val, reg);
168 break;
169 case 2:
170 iowrite16(val, reg);
171 break;
172 default:
173 iowrite32(val, reg);
174 break;
175 }
176
177 return PCIBIOS_SUCCESSFUL;
178 }
179
180 /* PCI interrupt mapping */
rcar_pci_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)181 static int rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
182 {
183 struct pci_sys_data *sys = dev->bus->sysdata;
184 struct rcar_pci_priv *priv = sys->private_data;
185 int irq;
186
187 irq = of_irq_parse_and_map_pci(dev, slot, pin);
188 if (!irq)
189 irq = priv->irq;
190
191 return irq;
192 }
193
194 #ifdef CONFIG_PCI_DEBUG
195 /* if debug enabled, then attach an error handler irq to the bridge */
196
rcar_pci_err_irq(int irq,void * pw)197 static irqreturn_t rcar_pci_err_irq(int irq, void *pw)
198 {
199 struct rcar_pci_priv *priv = pw;
200 u32 status = ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG);
201
202 if (status & RCAR_PCI_INT_ALLERRORS) {
203 dev_err(priv->dev, "error irq: status %08x\n", status);
204
205 /* clear the error(s) */
206 iowrite32(status & RCAR_PCI_INT_ALLERRORS,
207 priv->reg + RCAR_PCI_INT_STATUS_REG);
208 return IRQ_HANDLED;
209 }
210
211 return IRQ_NONE;
212 }
213
rcar_pci_setup_errirq(struct rcar_pci_priv * priv)214 static void rcar_pci_setup_errirq(struct rcar_pci_priv *priv)
215 {
216 int ret;
217 u32 val;
218
219 ret = devm_request_irq(priv->dev, priv->irq, rcar_pci_err_irq,
220 IRQF_SHARED, "error irq", priv);
221 if (ret) {
222 dev_err(priv->dev, "cannot claim IRQ for error handling\n");
223 return;
224 }
225
226 val = ioread32(priv->reg + RCAR_PCI_INT_ENABLE_REG);
227 val |= RCAR_PCI_INT_ALLERRORS;
228 iowrite32(val, priv->reg + RCAR_PCI_INT_ENABLE_REG);
229 }
230 #else
rcar_pci_setup_errirq(struct rcar_pci_priv * priv)231 static inline void rcar_pci_setup_errirq(struct rcar_pci_priv *priv) { }
232 #endif
233
234 /* PCI host controller setup */
rcar_pci_setup(int nr,struct pci_sys_data * sys)235 static int rcar_pci_setup(int nr, struct pci_sys_data *sys)
236 {
237 struct rcar_pci_priv *priv = sys->private_data;
238 void __iomem *reg = priv->reg;
239 u32 val;
240
241 pm_runtime_enable(priv->dev);
242 pm_runtime_get_sync(priv->dev);
243
244 val = ioread32(reg + RCAR_PCI_UNIT_REV_REG);
245 dev_info(priv->dev, "PCI: bus%u revision %x\n", sys->busnr, val);
246
247 /* Disable Direct Power Down State and assert reset */
248 val = ioread32(reg + RCAR_USBCTR_REG) & ~RCAR_USBCTR_DIRPD;
249 val |= RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST;
250 iowrite32(val, reg + RCAR_USBCTR_REG);
251 udelay(4);
252
253 /* De-assert reset and reset PCIAHB window1 size */
254 val &= ~(RCAR_USBCTR_PCIAHB_WIN1_MASK | RCAR_USBCTR_PCICLK_MASK |
255 RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST);
256
257 /* Setup PCIAHB window1 size */
258 switch (priv->window_size) {
259 case SZ_2G:
260 val |= RCAR_USBCTR_PCIAHB_WIN1_2G;
261 break;
262 case SZ_1G:
263 val |= RCAR_USBCTR_PCIAHB_WIN1_1G;
264 break;
265 case SZ_512M:
266 val |= RCAR_USBCTR_PCIAHB_WIN1_512M;
267 break;
268 default:
269 pr_warn("unknown window size %ld - defaulting to 256M\n",
270 priv->window_size);
271 priv->window_size = SZ_256M;
272 /* fall-through */
273 case SZ_256M:
274 val |= RCAR_USBCTR_PCIAHB_WIN1_256M;
275 break;
276 }
277 iowrite32(val, reg + RCAR_USBCTR_REG);
278
279 /* Configure AHB master and slave modes */
280 iowrite32(RCAR_AHB_BUS_MODE, reg + RCAR_AHB_BUS_CTR_REG);
281
282 /* Configure PCI arbiter */
283 val = ioread32(reg + RCAR_PCI_ARBITER_CTR_REG);
284 val |= RCAR_PCI_ARBITER_PCIREQ0 | RCAR_PCI_ARBITER_PCIREQ1 |
285 RCAR_PCI_ARBITER_PCIBP_MODE;
286 iowrite32(val, reg + RCAR_PCI_ARBITER_CTR_REG);
287
288 /* PCI-AHB mapping: 0x40000000 base */
289 iowrite32(0x40000000 | RCAR_PCIAHB_PREFETCH16,
290 reg + RCAR_PCIAHB_WIN1_CTR_REG);
291
292 /* AHB-PCI mapping: OHCI/EHCI registers */
293 val = priv->mem_res.start | RCAR_AHBPCI_WIN_CTR_MEM;
294 iowrite32(val, reg + RCAR_AHBPCI_WIN2_CTR_REG);
295
296 /* Enable AHB-PCI bridge PCI configuration access */
297 iowrite32(RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG,
298 reg + RCAR_AHBPCI_WIN1_CTR_REG);
299 /* Set PCI-AHB Window1 address */
300 iowrite32(0x40000000 | PCI_BASE_ADDRESS_MEM_PREFETCH,
301 reg + PCI_BASE_ADDRESS_1);
302 /* Set AHB-PCI bridge PCI communication area address */
303 val = priv->cfg_res->start + RCAR_AHBPCI_PCICOM_OFFSET;
304 iowrite32(val, reg + PCI_BASE_ADDRESS_0);
305
306 val = ioread32(reg + PCI_COMMAND);
307 val |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
308 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
309 iowrite32(val, reg + PCI_COMMAND);
310
311 /* Enable PCI interrupts */
312 iowrite32(RCAR_PCI_INT_A | RCAR_PCI_INT_B | RCAR_PCI_INT_PME,
313 reg + RCAR_PCI_INT_ENABLE_REG);
314
315 if (priv->irq > 0)
316 rcar_pci_setup_errirq(priv);
317
318 /* Add PCI resources */
319 pci_add_resource(&sys->resources, &priv->io_res);
320 pci_add_resource(&sys->resources, &priv->mem_res);
321
322 /* Setup bus number based on platform device id / of bus-range */
323 sys->busnr = priv->busnr;
324 return 1;
325 }
326
327 static struct pci_ops rcar_pci_ops = {
328 .read = rcar_pci_read_config,
329 .write = rcar_pci_write_config,
330 };
331
rcar_pci_probe(struct platform_device * pdev)332 static int rcar_pci_probe(struct platform_device *pdev)
333 {
334 struct resource *cfg_res, *mem_res;
335 struct rcar_pci_priv *priv;
336 void __iomem *reg;
337 struct hw_pci hw;
338 void *hw_private[1];
339
340 cfg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
341 reg = devm_ioremap_resource(&pdev->dev, cfg_res);
342 if (IS_ERR(reg))
343 return PTR_ERR(reg);
344
345 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
346 if (!mem_res || !mem_res->start)
347 return -ENODEV;
348
349 priv = devm_kzalloc(&pdev->dev,
350 sizeof(struct rcar_pci_priv), GFP_KERNEL);
351 if (!priv)
352 return -ENOMEM;
353
354 priv->mem_res = *mem_res;
355 /*
356 * The controller does not support/use port I/O,
357 * so setup a dummy port I/O region here.
358 */
359 priv->io_res.start = priv->mem_res.start;
360 priv->io_res.end = priv->mem_res.end;
361 priv->io_res.flags = IORESOURCE_IO;
362
363 priv->cfg_res = cfg_res;
364
365 priv->irq = platform_get_irq(pdev, 0);
366 priv->reg = reg;
367 priv->dev = &pdev->dev;
368
369 if (priv->irq < 0) {
370 dev_err(&pdev->dev, "no valid irq found\n");
371 return priv->irq;
372 }
373
374 priv->window_size = SZ_1G;
375
376 if (pdev->dev.of_node) {
377 struct resource busnr;
378 int ret;
379
380 ret = of_pci_parse_bus_range(pdev->dev.of_node, &busnr);
381 if (ret < 0) {
382 dev_err(&pdev->dev, "failed to parse bus-range\n");
383 return ret;
384 }
385
386 priv->busnr = busnr.start;
387 if (busnr.end != busnr.start)
388 dev_warn(&pdev->dev, "only one bus number supported\n");
389 } else {
390 priv->busnr = pdev->id;
391 }
392
393 hw_private[0] = priv;
394 memset(&hw, 0, sizeof(hw));
395 hw.nr_controllers = ARRAY_SIZE(hw_private);
396 hw.private_data = hw_private;
397 hw.map_irq = rcar_pci_map_irq;
398 hw.ops = &rcar_pci_ops;
399 hw.setup = rcar_pci_setup;
400 pci_common_init_dev(&pdev->dev, &hw);
401 return 0;
402 }
403
404 static struct of_device_id rcar_pci_of_match[] = {
405 { .compatible = "renesas,pci-r8a7790", },
406 { .compatible = "renesas,pci-r8a7791", },
407 { },
408 };
409
410 MODULE_DEVICE_TABLE(of, rcar_pci_of_match);
411
412 static struct platform_driver rcar_pci_driver = {
413 .driver = {
414 .name = "pci-rcar-gen2",
415 .owner = THIS_MODULE,
416 .suppress_bind_attrs = true,
417 .of_match_table = rcar_pci_of_match,
418 },
419 .probe = rcar_pci_probe,
420 };
421
422 module_platform_driver(rcar_pci_driver);
423
424 MODULE_LICENSE("GPL v2");
425 MODULE_DESCRIPTION("Renesas R-Car Gen2 internal PCI");
426 MODULE_AUTHOR("Valentine Barshak <valentine.barshak@cogentembedded.com>");
427