1 /*
2 * PCIe driver for Renesas R-Car SoCs
3 * Copyright (C) 2014 Renesas Electronics Europe Ltd
4 *
5 * Based on:
6 * arch/sh/drivers/pci/pcie-sh7786.c
7 * arch/sh/drivers/pci/ops-sh7786.c
8 * Copyright (C) 2009 - 2011 Paul Mundt
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/msi.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_pci.h>
26 #include <linux/of_platform.h>
27 #include <linux/pci.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
30
31 #define DRV_NAME "rcar-pcie"
32
33 #define PCIECAR 0x000010
34 #define PCIECCTLR 0x000018
35 #define CONFIG_SEND_ENABLE (1 << 31)
36 #define TYPE0 (0 << 8)
37 #define TYPE1 (1 << 8)
38 #define PCIECDR 0x000020
39 #define PCIEMSR 0x000028
40 #define PCIEINTXR 0x000400
41 #define PCIEMSITXR 0x000840
42
43 /* Transfer control */
44 #define PCIETCTLR 0x02000
45 #define CFINIT 1
46 #define PCIETSTR 0x02004
47 #define DATA_LINK_ACTIVE 1
48 #define PCIEERRFR 0x02020
49 #define UNSUPPORTED_REQUEST (1 << 4)
50 #define PCIEMSIFR 0x02044
51 #define PCIEMSIALR 0x02048
52 #define MSIFE 1
53 #define PCIEMSIAUR 0x0204c
54 #define PCIEMSIIER 0x02050
55
56 /* root port address */
57 #define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
58
59 /* local address reg & mask */
60 #define PCIELAR(x) (0x02200 + ((x) * 0x20))
61 #define PCIELAMR(x) (0x02208 + ((x) * 0x20))
62 #define LAM_PREFETCH (1 << 3)
63 #define LAM_64BIT (1 << 2)
64 #define LAR_ENABLE (1 << 1)
65
66 /* PCIe address reg & mask */
67 #define PCIEPARL(x) (0x03400 + ((x) * 0x20))
68 #define PCIEPARH(x) (0x03404 + ((x) * 0x20))
69 #define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
70 #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
71 #define PAR_ENABLE (1 << 31)
72 #define IO_SPACE (1 << 8)
73
74 /* Configuration */
75 #define PCICONF(x) (0x010000 + ((x) * 0x4))
76 #define PMCAP(x) (0x010040 + ((x) * 0x4))
77 #define EXPCAP(x) (0x010070 + ((x) * 0x4))
78 #define VCCAP(x) (0x010100 + ((x) * 0x4))
79
80 /* link layer */
81 #define IDSETR1 0x011004
82 #define TLCTLR 0x011048
83 #define MACSR 0x011054
84 #define MACCTLR 0x011058
85 #define SCRAMBLE_DISABLE (1 << 27)
86
87 /* R-Car H1 PHY */
88 #define H1_PCIEPHYADRR 0x04000c
89 #define WRITE_CMD (1 << 16)
90 #define PHY_ACK (1 << 24)
91 #define RATE_POS 12
92 #define LANE_POS 8
93 #define ADR_POS 0
94 #define H1_PCIEPHYDOUTR 0x040014
95 #define H1_PCIEPHYSR 0x040018
96
97 #define INT_PCI_MSI_NR 32
98
99 #define RCONF(x) (PCICONF(0)+(x))
100 #define RPMCAP(x) (PMCAP(0)+(x))
101 #define REXPCAP(x) (EXPCAP(0)+(x))
102 #define RVCCAP(x) (VCCAP(0)+(x))
103
104 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
105 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
106 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
107
108 #define RCAR_PCI_MAX_RESOURCES 4
109 #define MAX_NR_INBOUND_MAPS 6
110
111 struct rcar_msi {
112 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
113 struct irq_domain *domain;
114 struct msi_chip chip;
115 unsigned long pages;
116 struct mutex lock;
117 int irq1;
118 int irq2;
119 };
120
to_rcar_msi(struct msi_chip * chip)121 static inline struct rcar_msi *to_rcar_msi(struct msi_chip *chip)
122 {
123 return container_of(chip, struct rcar_msi, chip);
124 }
125
126 /* Structure representing the PCIe interface */
127 struct rcar_pcie {
128 struct device *dev;
129 void __iomem *base;
130 struct resource res[RCAR_PCI_MAX_RESOURCES];
131 struct resource busn;
132 int root_bus_nr;
133 struct clk *clk;
134 struct clk *bus_clk;
135 struct rcar_msi msi;
136 };
137
sys_to_pcie(struct pci_sys_data * sys)138 static inline struct rcar_pcie *sys_to_pcie(struct pci_sys_data *sys)
139 {
140 return sys->private_data;
141 }
142
rcar_pci_write_reg(struct rcar_pcie * pcie,unsigned long val,unsigned long reg)143 static void rcar_pci_write_reg(struct rcar_pcie *pcie, unsigned long val,
144 unsigned long reg)
145 {
146 writel(val, pcie->base + reg);
147 }
148
rcar_pci_read_reg(struct rcar_pcie * pcie,unsigned long reg)149 static unsigned long rcar_pci_read_reg(struct rcar_pcie *pcie,
150 unsigned long reg)
151 {
152 return readl(pcie->base + reg);
153 }
154
155 enum {
156 RCAR_PCI_ACCESS_READ,
157 RCAR_PCI_ACCESS_WRITE,
158 };
159
rcar_rmw32(struct rcar_pcie * pcie,int where,u32 mask,u32 data)160 static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
161 {
162 int shift = 8 * (where & 3);
163 u32 val = rcar_pci_read_reg(pcie, where & ~3);
164
165 val &= ~(mask << shift);
166 val |= data << shift;
167 rcar_pci_write_reg(pcie, val, where & ~3);
168 }
169
rcar_read_conf(struct rcar_pcie * pcie,int where)170 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
171 {
172 int shift = 8 * (where & 3);
173 u32 val = rcar_pci_read_reg(pcie, where & ~3);
174
175 return val >> shift;
176 }
177
178 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
rcar_pcie_config_access(struct rcar_pcie * pcie,unsigned char access_type,struct pci_bus * bus,unsigned int devfn,int where,u32 * data)179 static int rcar_pcie_config_access(struct rcar_pcie *pcie,
180 unsigned char access_type, struct pci_bus *bus,
181 unsigned int devfn, int where, u32 *data)
182 {
183 int dev, func, reg, index;
184
185 dev = PCI_SLOT(devfn);
186 func = PCI_FUNC(devfn);
187 reg = where & ~3;
188 index = reg / 4;
189
190 /*
191 * While each channel has its own memory-mapped extended config
192 * space, it's generally only accessible when in endpoint mode.
193 * When in root complex mode, the controller is unable to target
194 * itself with either type 0 or type 1 accesses, and indeed, any
195 * controller initiated target transfer to its own config space
196 * result in a completer abort.
197 *
198 * Each channel effectively only supports a single device, but as
199 * the same channel <-> device access works for any PCI_SLOT()
200 * value, we cheat a bit here and bind the controller's config
201 * space to devfn 0 in order to enable self-enumeration. In this
202 * case the regular ECAR/ECDR path is sidelined and the mangled
203 * config access itself is initiated as an internal bus transaction.
204 */
205 if (pci_is_root_bus(bus)) {
206 if (dev != 0)
207 return PCIBIOS_DEVICE_NOT_FOUND;
208
209 if (access_type == RCAR_PCI_ACCESS_READ) {
210 *data = rcar_pci_read_reg(pcie, PCICONF(index));
211 } else {
212 /* Keep an eye out for changes to the root bus number */
213 if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS))
214 pcie->root_bus_nr = *data & 0xff;
215
216 rcar_pci_write_reg(pcie, *data, PCICONF(index));
217 }
218
219 return PCIBIOS_SUCCESSFUL;
220 }
221
222 if (pcie->root_bus_nr < 0)
223 return PCIBIOS_DEVICE_NOT_FOUND;
224
225 /* Clear errors */
226 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
227
228 /* Set the PIO address */
229 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) |
230 PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR);
231
232 /* Enable the configuration access */
233 if (bus->parent->number == pcie->root_bus_nr)
234 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
235 else
236 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
237
238 /* Check for errors */
239 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
240 return PCIBIOS_DEVICE_NOT_FOUND;
241
242 /* Check for master and target aborts */
243 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) &
244 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
245 return PCIBIOS_DEVICE_NOT_FOUND;
246
247 if (access_type == RCAR_PCI_ACCESS_READ)
248 *data = rcar_pci_read_reg(pcie, PCIECDR);
249 else
250 rcar_pci_write_reg(pcie, *data, PCIECDR);
251
252 /* Disable the configuration access */
253 rcar_pci_write_reg(pcie, 0, PCIECCTLR);
254
255 return PCIBIOS_SUCCESSFUL;
256 }
257
rcar_pcie_read_conf(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * val)258 static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
259 int where, int size, u32 *val)
260 {
261 struct rcar_pcie *pcie = sys_to_pcie(bus->sysdata);
262 int ret;
263
264 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
265 bus, devfn, where, val);
266 if (ret != PCIBIOS_SUCCESSFUL) {
267 *val = 0xffffffff;
268 return ret;
269 }
270
271 if (size == 1)
272 *val = (*val >> (8 * (where & 3))) & 0xff;
273 else if (size == 2)
274 *val = (*val >> (8 * (where & 2))) & 0xffff;
275
276 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
277 bus->number, devfn, where, size, (unsigned long)*val);
278
279 return ret;
280 }
281
282 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
rcar_pcie_write_conf(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 val)283 static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
284 int where, int size, u32 val)
285 {
286 struct rcar_pcie *pcie = sys_to_pcie(bus->sysdata);
287 int shift, ret;
288 u32 data;
289
290 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
291 bus, devfn, where, &data);
292 if (ret != PCIBIOS_SUCCESSFUL)
293 return ret;
294
295 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
296 bus->number, devfn, where, size, (unsigned long)val);
297
298 if (size == 1) {
299 shift = 8 * (where & 3);
300 data &= ~(0xff << shift);
301 data |= ((val & 0xff) << shift);
302 } else if (size == 2) {
303 shift = 8 * (where & 2);
304 data &= ~(0xffff << shift);
305 data |= ((val & 0xffff) << shift);
306 } else
307 data = val;
308
309 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_WRITE,
310 bus, devfn, where, &data);
311
312 return ret;
313 }
314
315 static struct pci_ops rcar_pcie_ops = {
316 .read = rcar_pcie_read_conf,
317 .write = rcar_pcie_write_conf,
318 };
319
rcar_pcie_setup_window(int win,struct rcar_pcie * pcie)320 static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie)
321 {
322 struct resource *res = &pcie->res[win];
323
324 /* Setup PCIe address space mappings for each resource */
325 resource_size_t size;
326 resource_size_t res_start;
327 u32 mask;
328
329 rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
330
331 /*
332 * The PAMR mask is calculated in units of 128Bytes, which
333 * keeps things pretty simple.
334 */
335 size = resource_size(res);
336 mask = (roundup_pow_of_two(size) / SZ_128) - 1;
337 rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
338
339 if (res->flags & IORESOURCE_IO)
340 res_start = pci_pio_to_address(res->start);
341 else
342 res_start = res->start;
343
344 rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPARH(win));
345 rcar_pci_write_reg(pcie, lower_32_bits(res_start), PCIEPARL(win));
346
347 /* First resource is for IO */
348 mask = PAR_ENABLE;
349 if (res->flags & IORESOURCE_IO)
350 mask |= IO_SPACE;
351
352 rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win));
353 }
354
rcar_pcie_setup(int nr,struct pci_sys_data * sys)355 static int rcar_pcie_setup(int nr, struct pci_sys_data *sys)
356 {
357 struct rcar_pcie *pcie = sys_to_pcie(sys);
358 struct resource *res;
359 int i;
360
361 pcie->root_bus_nr = -1;
362
363 /* Setup PCI resources */
364 for (i = 0; i < RCAR_PCI_MAX_RESOURCES; i++) {
365
366 res = &pcie->res[i];
367 if (!res->flags)
368 continue;
369
370 rcar_pcie_setup_window(i, pcie);
371
372 if (res->flags & IORESOURCE_IO) {
373 phys_addr_t io_start = pci_pio_to_address(res->start);
374 pci_ioremap_io(nr * SZ_64K, io_start);
375 } else
376 pci_add_resource(&sys->resources, res);
377 }
378 pci_add_resource(&sys->resources, &pcie->busn);
379
380 return 1;
381 }
382
rcar_pcie_add_bus(struct pci_bus * bus)383 static void rcar_pcie_add_bus(struct pci_bus *bus)
384 {
385 if (IS_ENABLED(CONFIG_PCI_MSI)) {
386 struct rcar_pcie *pcie = sys_to_pcie(bus->sysdata);
387
388 bus->msi = &pcie->msi.chip;
389 }
390 }
391
392 struct hw_pci rcar_pci = {
393 .setup = rcar_pcie_setup,
394 .map_irq = of_irq_parse_and_map_pci,
395 .ops = &rcar_pcie_ops,
396 .add_bus = rcar_pcie_add_bus,
397 };
398
rcar_pcie_enable(struct rcar_pcie * pcie)399 static void rcar_pcie_enable(struct rcar_pcie *pcie)
400 {
401 struct platform_device *pdev = to_platform_device(pcie->dev);
402
403 rcar_pci.nr_controllers = 1;
404 rcar_pci.private_data = (void **)&pcie;
405
406 pci_common_init_dev(&pdev->dev, &rcar_pci);
407 #ifdef CONFIG_PCI_DOMAINS
408 rcar_pci.domain++;
409 #endif
410 }
411
phy_wait_for_ack(struct rcar_pcie * pcie)412 static int phy_wait_for_ack(struct rcar_pcie *pcie)
413 {
414 unsigned int timeout = 100;
415
416 while (timeout--) {
417 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
418 return 0;
419
420 udelay(100);
421 }
422
423 dev_err(pcie->dev, "Access to PCIe phy timed out\n");
424
425 return -ETIMEDOUT;
426 }
427
phy_write_reg(struct rcar_pcie * pcie,unsigned int rate,unsigned int addr,unsigned int lane,unsigned int data)428 static void phy_write_reg(struct rcar_pcie *pcie,
429 unsigned int rate, unsigned int addr,
430 unsigned int lane, unsigned int data)
431 {
432 unsigned long phyaddr;
433
434 phyaddr = WRITE_CMD |
435 ((rate & 1) << RATE_POS) |
436 ((lane & 0xf) << LANE_POS) |
437 ((addr & 0xff) << ADR_POS);
438
439 /* Set write data */
440 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
441 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
442
443 /* Ignore errors as they will be dealt with if the data link is down */
444 phy_wait_for_ack(pcie);
445
446 /* Clear command */
447 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
448 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
449
450 /* Ignore errors as they will be dealt with if the data link is down */
451 phy_wait_for_ack(pcie);
452 }
453
rcar_pcie_wait_for_dl(struct rcar_pcie * pcie)454 static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
455 {
456 unsigned int timeout = 10;
457
458 while (timeout--) {
459 if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
460 return 0;
461
462 msleep(5);
463 }
464
465 return -ETIMEDOUT;
466 }
467
rcar_pcie_hw_init(struct rcar_pcie * pcie)468 static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
469 {
470 int err;
471
472 /* Begin initialization */
473 rcar_pci_write_reg(pcie, 0, PCIETCTLR);
474
475 /* Set mode */
476 rcar_pci_write_reg(pcie, 1, PCIEMSR);
477
478 /*
479 * Initial header for port config space is type 1, set the device
480 * class to match. Hardware takes care of propagating the IDSETR
481 * settings, so there is no need to bother with a quirk.
482 */
483 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
484
485 /*
486 * Setup Secondary Bus Number & Subordinate Bus Number, even though
487 * they aren't used, to avoid bridge being detected as broken.
488 */
489 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
490 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
491
492 /* Initialize default capabilities. */
493 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
494 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
495 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
496 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
497 PCI_HEADER_TYPE_BRIDGE);
498
499 /* Enable data link layer active state reporting */
500 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC,
501 PCI_EXP_LNKCAP_DLLLARC);
502
503 /* Write out the physical slot number = 0 */
504 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
505
506 /* Set the completion timer timeout to the maximum 50ms. */
507 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
508
509 /* Terminate list of capabilities (Next Capability Offset=0) */
510 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
511
512 /* Enable MSI */
513 if (IS_ENABLED(CONFIG_PCI_MSI))
514 rcar_pci_write_reg(pcie, 0x101f0000, PCIEMSITXR);
515
516 /* Finish initialization - establish a PCI Express link */
517 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
518
519 /* This will timeout if we don't have a link. */
520 err = rcar_pcie_wait_for_dl(pcie);
521 if (err)
522 return err;
523
524 /* Enable INTx interrupts */
525 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
526
527 wmb();
528
529 return 0;
530 }
531
rcar_pcie_hw_init_h1(struct rcar_pcie * pcie)532 static int rcar_pcie_hw_init_h1(struct rcar_pcie *pcie)
533 {
534 unsigned int timeout = 10;
535
536 /* Initialize the phy */
537 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
538 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
539 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188);
540 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188);
541 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014);
542 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014);
543 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0);
544 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB);
545 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062);
546 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000);
547 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000);
548 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806);
549
550 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5);
551 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
552 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
553
554 while (timeout--) {
555 if (rcar_pci_read_reg(pcie, H1_PCIEPHYSR))
556 return rcar_pcie_hw_init(pcie);
557
558 msleep(5);
559 }
560
561 return -ETIMEDOUT;
562 }
563
rcar_msi_alloc(struct rcar_msi * chip)564 static int rcar_msi_alloc(struct rcar_msi *chip)
565 {
566 int msi;
567
568 mutex_lock(&chip->lock);
569
570 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
571 if (msi < INT_PCI_MSI_NR)
572 set_bit(msi, chip->used);
573 else
574 msi = -ENOSPC;
575
576 mutex_unlock(&chip->lock);
577
578 return msi;
579 }
580
rcar_msi_free(struct rcar_msi * chip,unsigned long irq)581 static void rcar_msi_free(struct rcar_msi *chip, unsigned long irq)
582 {
583 mutex_lock(&chip->lock);
584 clear_bit(irq, chip->used);
585 mutex_unlock(&chip->lock);
586 }
587
rcar_pcie_msi_irq(int irq,void * data)588 static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
589 {
590 struct rcar_pcie *pcie = data;
591 struct rcar_msi *msi = &pcie->msi;
592 unsigned long reg;
593
594 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
595
596 /* MSI & INTx share an interrupt - we only handle MSI here */
597 if (!reg)
598 return IRQ_NONE;
599
600 while (reg) {
601 unsigned int index = find_first_bit(®, 32);
602 unsigned int irq;
603
604 /* clear the interrupt */
605 rcar_pci_write_reg(pcie, 1 << index, PCIEMSIFR);
606
607 irq = irq_find_mapping(msi->domain, index);
608 if (irq) {
609 if (test_bit(index, msi->used))
610 generic_handle_irq(irq);
611 else
612 dev_info(pcie->dev, "unhandled MSI\n");
613 } else {
614 /* Unknown MSI, just clear it */
615 dev_dbg(pcie->dev, "unexpected MSI\n");
616 }
617
618 /* see if there's any more pending in this vector */
619 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
620 }
621
622 return IRQ_HANDLED;
623 }
624
rcar_msi_setup_irq(struct msi_chip * chip,struct pci_dev * pdev,struct msi_desc * desc)625 static int rcar_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
626 struct msi_desc *desc)
627 {
628 struct rcar_msi *msi = to_rcar_msi(chip);
629 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
630 struct msi_msg msg;
631 unsigned int irq;
632 int hwirq;
633
634 hwirq = rcar_msi_alloc(msi);
635 if (hwirq < 0)
636 return hwirq;
637
638 irq = irq_create_mapping(msi->domain, hwirq);
639 if (!irq) {
640 rcar_msi_free(msi, hwirq);
641 return -EINVAL;
642 }
643
644 irq_set_msi_desc(irq, desc);
645
646 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
647 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
648 msg.data = hwirq;
649
650 write_msi_msg(irq, &msg);
651
652 return 0;
653 }
654
rcar_msi_teardown_irq(struct msi_chip * chip,unsigned int irq)655 static void rcar_msi_teardown_irq(struct msi_chip *chip, unsigned int irq)
656 {
657 struct rcar_msi *msi = to_rcar_msi(chip);
658 struct irq_data *d = irq_get_irq_data(irq);
659
660 rcar_msi_free(msi, d->hwirq);
661 }
662
663 static struct irq_chip rcar_msi_irq_chip = {
664 .name = "R-Car PCIe MSI",
665 .irq_enable = unmask_msi_irq,
666 .irq_disable = mask_msi_irq,
667 .irq_mask = mask_msi_irq,
668 .irq_unmask = unmask_msi_irq,
669 };
670
rcar_msi_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)671 static int rcar_msi_map(struct irq_domain *domain, unsigned int irq,
672 irq_hw_number_t hwirq)
673 {
674 irq_set_chip_and_handler(irq, &rcar_msi_irq_chip, handle_simple_irq);
675 irq_set_chip_data(irq, domain->host_data);
676 set_irq_flags(irq, IRQF_VALID);
677
678 return 0;
679 }
680
681 static const struct irq_domain_ops msi_domain_ops = {
682 .map = rcar_msi_map,
683 };
684
rcar_pcie_enable_msi(struct rcar_pcie * pcie)685 static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
686 {
687 struct platform_device *pdev = to_platform_device(pcie->dev);
688 struct rcar_msi *msi = &pcie->msi;
689 unsigned long base;
690 int err;
691
692 mutex_init(&msi->lock);
693
694 msi->chip.dev = pcie->dev;
695 msi->chip.setup_irq = rcar_msi_setup_irq;
696 msi->chip.teardown_irq = rcar_msi_teardown_irq;
697
698 msi->domain = irq_domain_add_linear(pcie->dev->of_node, INT_PCI_MSI_NR,
699 &msi_domain_ops, &msi->chip);
700 if (!msi->domain) {
701 dev_err(&pdev->dev, "failed to create IRQ domain\n");
702 return -ENOMEM;
703 }
704
705 /* Two irqs are for MSI, but they are also used for non-MSI irqs */
706 err = devm_request_irq(&pdev->dev, msi->irq1, rcar_pcie_msi_irq,
707 IRQF_SHARED | IRQF_NO_THREAD,
708 rcar_msi_irq_chip.name, pcie);
709 if (err < 0) {
710 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
711 goto err;
712 }
713
714 err = devm_request_irq(&pdev->dev, msi->irq2, rcar_pcie_msi_irq,
715 IRQF_SHARED | IRQF_NO_THREAD,
716 rcar_msi_irq_chip.name, pcie);
717 if (err < 0) {
718 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
719 goto err;
720 }
721
722 /* setup MSI data target */
723 msi->pages = __get_free_pages(GFP_KERNEL, 0);
724 base = virt_to_phys((void *)msi->pages);
725
726 rcar_pci_write_reg(pcie, base | MSIFE, PCIEMSIALR);
727 rcar_pci_write_reg(pcie, 0, PCIEMSIAUR);
728
729 /* enable all MSI interrupts */
730 rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);
731
732 return 0;
733
734 err:
735 irq_domain_remove(msi->domain);
736 return err;
737 }
738
rcar_pcie_get_resources(struct platform_device * pdev,struct rcar_pcie * pcie)739 static int rcar_pcie_get_resources(struct platform_device *pdev,
740 struct rcar_pcie *pcie)
741 {
742 struct resource res;
743 int err, i;
744
745 err = of_address_to_resource(pdev->dev.of_node, 0, &res);
746 if (err)
747 return err;
748
749 pcie->clk = devm_clk_get(&pdev->dev, "pcie");
750 if (IS_ERR(pcie->clk)) {
751 dev_err(pcie->dev, "cannot get platform clock\n");
752 return PTR_ERR(pcie->clk);
753 }
754 err = clk_prepare_enable(pcie->clk);
755 if (err)
756 goto fail_clk;
757
758 pcie->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus");
759 if (IS_ERR(pcie->bus_clk)) {
760 dev_err(pcie->dev, "cannot get pcie bus clock\n");
761 err = PTR_ERR(pcie->bus_clk);
762 goto fail_clk;
763 }
764 err = clk_prepare_enable(pcie->bus_clk);
765 if (err)
766 goto err_map_reg;
767
768 i = irq_of_parse_and_map(pdev->dev.of_node, 0);
769 if (i < 0) {
770 dev_err(pcie->dev, "cannot get platform resources for msi interrupt\n");
771 err = -ENOENT;
772 goto err_map_reg;
773 }
774 pcie->msi.irq1 = i;
775
776 i = irq_of_parse_and_map(pdev->dev.of_node, 1);
777 if (i < 0) {
778 dev_err(pcie->dev, "cannot get platform resources for msi interrupt\n");
779 err = -ENOENT;
780 goto err_map_reg;
781 }
782 pcie->msi.irq2 = i;
783
784 pcie->base = devm_ioremap_resource(&pdev->dev, &res);
785 if (IS_ERR(pcie->base)) {
786 err = PTR_ERR(pcie->base);
787 goto err_map_reg;
788 }
789
790 return 0;
791
792 err_map_reg:
793 clk_disable_unprepare(pcie->bus_clk);
794 fail_clk:
795 clk_disable_unprepare(pcie->clk);
796
797 return err;
798 }
799
rcar_pcie_inbound_ranges(struct rcar_pcie * pcie,struct of_pci_range * range,int * index)800 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
801 struct of_pci_range *range,
802 int *index)
803 {
804 u64 restype = range->flags;
805 u64 cpu_addr = range->cpu_addr;
806 u64 cpu_end = range->cpu_addr + range->size;
807 u64 pci_addr = range->pci_addr;
808 u32 flags = LAM_64BIT | LAR_ENABLE;
809 u64 mask;
810 u64 size;
811 int idx = *index;
812
813 if (restype & IORESOURCE_PREFETCH)
814 flags |= LAM_PREFETCH;
815
816 /*
817 * If the size of the range is larger than the alignment of the start
818 * address, we have to use multiple entries to perform the mapping.
819 */
820 if (cpu_addr > 0) {
821 unsigned long nr_zeros = __ffs64(cpu_addr);
822 u64 alignment = 1ULL << nr_zeros;
823
824 size = min(range->size, alignment);
825 } else {
826 size = range->size;
827 }
828 /* Hardware supports max 4GiB inbound region */
829 size = min(size, 1ULL << 32);
830
831 mask = roundup_pow_of_two(size) - 1;
832 mask &= ~0xf;
833
834 while (cpu_addr < cpu_end) {
835 /*
836 * Set up 64-bit inbound regions as the range parser doesn't
837 * distinguish between 32 and 64-bit types.
838 */
839 rcar_pci_write_reg(pcie, lower_32_bits(pci_addr), PCIEPRAR(idx));
840 rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
841 rcar_pci_write_reg(pcie, lower_32_bits(mask) | flags, PCIELAMR(idx));
842
843 rcar_pci_write_reg(pcie, upper_32_bits(pci_addr), PCIEPRAR(idx+1));
844 rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr), PCIELAR(idx+1));
845 rcar_pci_write_reg(pcie, 0, PCIELAMR(idx + 1));
846
847 pci_addr += size;
848 cpu_addr += size;
849 idx += 2;
850
851 if (idx > MAX_NR_INBOUND_MAPS) {
852 dev_err(pcie->dev, "Failed to map inbound regions!\n");
853 return -EINVAL;
854 }
855 }
856 *index = idx;
857
858 return 0;
859 }
860
pci_dma_range_parser_init(struct of_pci_range_parser * parser,struct device_node * node)861 static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
862 struct device_node *node)
863 {
864 const int na = 3, ns = 2;
865 int rlen;
866
867 parser->node = node;
868 parser->pna = of_n_addr_cells(node);
869 parser->np = parser->pna + na + ns;
870
871 parser->range = of_get_property(node, "dma-ranges", &rlen);
872 if (!parser->range)
873 return -ENOENT;
874
875 parser->end = parser->range + rlen / sizeof(__be32);
876 return 0;
877 }
878
rcar_pcie_parse_map_dma_ranges(struct rcar_pcie * pcie,struct device_node * np)879 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie,
880 struct device_node *np)
881 {
882 struct of_pci_range range;
883 struct of_pci_range_parser parser;
884 int index = 0;
885 int err;
886
887 if (pci_dma_range_parser_init(&parser, np))
888 return -EINVAL;
889
890 /* Get the dma-ranges from DT */
891 for_each_of_pci_range(&parser, &range) {
892 u64 end = range.cpu_addr + range.size - 1;
893 dev_dbg(pcie->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
894 range.flags, range.cpu_addr, end, range.pci_addr);
895
896 err = rcar_pcie_inbound_ranges(pcie, &range, &index);
897 if (err)
898 return err;
899 }
900
901 return 0;
902 }
903
904 static const struct of_device_id rcar_pcie_of_match[] = {
905 { .compatible = "renesas,pcie-r8a7779", .data = rcar_pcie_hw_init_h1 },
906 { .compatible = "renesas,pcie-r8a7790", .data = rcar_pcie_hw_init },
907 { .compatible = "renesas,pcie-r8a7791", .data = rcar_pcie_hw_init },
908 {},
909 };
910 MODULE_DEVICE_TABLE(of, rcar_pcie_of_match);
911
rcar_pcie_probe(struct platform_device * pdev)912 static int rcar_pcie_probe(struct platform_device *pdev)
913 {
914 struct rcar_pcie *pcie;
915 unsigned int data;
916 struct of_pci_range range;
917 struct of_pci_range_parser parser;
918 const struct of_device_id *of_id;
919 int err, win = 0;
920 int (*hw_init_fn)(struct rcar_pcie *);
921
922 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
923 if (!pcie)
924 return -ENOMEM;
925
926 pcie->dev = &pdev->dev;
927 platform_set_drvdata(pdev, pcie);
928
929 /* Get the bus range */
930 if (of_pci_parse_bus_range(pdev->dev.of_node, &pcie->busn)) {
931 dev_err(&pdev->dev, "failed to parse bus-range property\n");
932 return -EINVAL;
933 }
934
935 if (of_pci_range_parser_init(&parser, pdev->dev.of_node)) {
936 dev_err(&pdev->dev, "missing ranges property\n");
937 return -EINVAL;
938 }
939
940 err = rcar_pcie_get_resources(pdev, pcie);
941 if (err < 0) {
942 dev_err(&pdev->dev, "failed to request resources: %d\n", err);
943 return err;
944 }
945
946 for_each_of_pci_range(&parser, &range) {
947 err = of_pci_range_to_resource(&range, pdev->dev.of_node,
948 &pcie->res[win++]);
949 if (err < 0)
950 return err;
951
952 if (win > RCAR_PCI_MAX_RESOURCES)
953 break;
954 }
955
956 err = rcar_pcie_parse_map_dma_ranges(pcie, pdev->dev.of_node);
957 if (err)
958 return err;
959
960 if (IS_ENABLED(CONFIG_PCI_MSI)) {
961 err = rcar_pcie_enable_msi(pcie);
962 if (err < 0) {
963 dev_err(&pdev->dev,
964 "failed to enable MSI support: %d\n",
965 err);
966 return err;
967 }
968 }
969
970 of_id = of_match_device(rcar_pcie_of_match, pcie->dev);
971 if (!of_id || !of_id->data)
972 return -EINVAL;
973 hw_init_fn = of_id->data;
974
975 /* Failure to get a link might just be that no cards are inserted */
976 err = hw_init_fn(pcie);
977 if (err) {
978 dev_info(&pdev->dev, "PCIe link down\n");
979 return 0;
980 }
981
982 data = rcar_pci_read_reg(pcie, MACSR);
983 dev_info(&pdev->dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
984
985 rcar_pcie_enable(pcie);
986
987 return 0;
988 }
989
990 static struct platform_driver rcar_pcie_driver = {
991 .driver = {
992 .name = DRV_NAME,
993 .owner = THIS_MODULE,
994 .of_match_table = rcar_pcie_of_match,
995 .suppress_bind_attrs = true,
996 },
997 .probe = rcar_pcie_probe,
998 };
999 module_platform_driver(rcar_pcie_driver);
1000
1001 MODULE_AUTHOR("Phil Edworthy <phil.edworthy@renesas.com>");
1002 MODULE_DESCRIPTION("Renesas R-Car PCIe driver");
1003 MODULE_LICENSE("GPL v2");
1004