1 /* 2 * r8a7778 processor support - PFC hardware block 3 * 4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6 * Copyright (C) 2013 Cogent Embedded, Inc. 7 * 8 * based on 9 * Copyright (C) 2011 Renesas Solutions Corp. 10 * Copyright (C) 2011 Magnus Damm 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; version 2 of the License. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 */ 21 22 #include <linux/platform_data/gpio-rcar.h> 23 #include <linux/kernel.h> 24 #include "sh_pfc.h" 25 26 #define PORT_GP_27(bank, fn, sfx) \ 27 PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ 28 PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ 29 PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ 30 PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ 31 PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ 32 PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ 33 PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ 34 PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ 35 PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ 36 PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ 37 PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ 38 PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ 39 PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \ 40 PORT_GP_1(bank, 26, fn, sfx) 41 42 #define CPU_ALL_PORT(fn, sfx) \ 43 PORT_GP_32(0, fn, sfx), \ 44 PORT_GP_32(1, fn, sfx), \ 45 PORT_GP_32(2, fn, sfx), \ 46 PORT_GP_32(3, fn, sfx), \ 47 PORT_GP_27(4, fn, sfx) 48 49 enum { 50 PINMUX_RESERVED = 0, 51 52 PINMUX_DATA_BEGIN, 53 GP_ALL(DATA), /* GP_0_0_DATA -> GP_4_26_DATA */ 54 PINMUX_DATA_END, 55 56 PINMUX_FUNCTION_BEGIN, 57 GP_ALL(FN), /* GP_0_0_FN -> GP_4_26_FN */ 58 59 /* GPSR0 */ 60 FN_IP0_1_0, FN_PENC0, FN_PENC1, FN_IP0_4_2, 61 FN_IP0_7_5, FN_IP0_11_8, FN_IP0_14_12, FN_A1, 62 FN_A2, FN_A3, FN_IP0_15, FN_IP0_16, 63 FN_IP0_17, FN_IP0_18, FN_IP0_19, FN_IP0_20, 64 FN_IP0_21, FN_IP0_22, FN_IP0_23, FN_IP0_24, 65 FN_IP0_25, FN_IP0_26, FN_IP0_27, FN_IP0_28, 66 FN_IP0_29, FN_IP0_30, FN_IP1_0, FN_IP1_1, 67 FN_IP1_4_2, FN_IP1_7_5, FN_IP1_10_8, FN_IP1_14_11, 68 69 /* GPSR1 */ 70 FN_IP1_23_21, FN_WE0, FN_IP1_24, FN_IP1_27_25, 71 FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, 72 FN_IP2_11_9, FN_IP2_13_12, FN_IP2_16_14, FN_IP2_17, 73 FN_IP2_30, FN_IP2_31, FN_IP3_1_0, FN_IP3_4_2, 74 FN_IP3_7_5, FN_IP3_9_8, FN_IP3_12_10, FN_IP3_15_13, 75 FN_IP3_18_16, FN_IP3_20_19, FN_IP3_23_21, FN_IP3_26_24, 76 FN_IP3_27, FN_IP3_28, FN_IP3_29, FN_IP3_30, 77 FN_IP3_31, FN_IP4_0, FN_IP4_3_1, FN_IP4_6_4, 78 79 /* GPSR2 */ 80 FN_IP4_7, FN_IP4_8, FN_IP4_10_9, FN_IP4_12_11, 81 FN_IP4_14_13, FN_IP4_16_15, FN_IP4_20_17, FN_IP4_24_21, 82 FN_IP4_26_25, FN_IP4_28_27, FN_IP4_30_29, FN_IP5_1_0, 83 FN_IP5_3_2, FN_IP5_5_4, FN_IP5_6, FN_IP5_7, 84 FN_IP5_9_8, FN_IP5_11_10, FN_IP5_12, FN_IP5_14_13, 85 FN_IP5_17_15, FN_IP5_20_18, FN_AUDIO_CLKA, FN_AUDIO_CLKB, 86 FN_IP5_22_21, FN_IP5_25_23, FN_IP5_28_26, FN_IP5_30_29, 87 FN_IP6_1_0, FN_IP6_4_2, FN_IP6_6_5, FN_IP6_7, 88 89 /* GPSR3 */ 90 FN_IP6_8, FN_IP6_9, FN_SSI_SCK34, FN_IP6_10, 91 FN_IP6_12_11, FN_IP6_13, FN_IP6_15_14, FN_IP6_16, 92 FN_IP6_18_17, FN_IP6_20_19, FN_IP6_21, FN_IP6_23_22, 93 FN_IP6_25_24, FN_IP6_27_26, FN_IP6_29_28, FN_IP6_31_30, 94 FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_8_6, 95 FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18, 96 FN_IP7_21, FN_IP7_24_22, FN_IP7_28_25, FN_IP7_31_29, 97 FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_10_9, 98 99 /* GPSR4 */ 100 FN_IP8_13_11, FN_IP8_15_14, FN_IP8_18_16, FN_IP8_21_19, 101 FN_IP8_23_22, FN_IP8_26_24, FN_IP8_29_27, FN_IP9_2_0, 102 FN_IP9_5_3, FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, 103 FN_IP9_17_15, FN_IP9_20_18, FN_IP9_23_21, FN_IP9_26_24, 104 FN_IP9_29_27, FN_IP10_2_0, FN_IP10_5_3, FN_IP10_8_6, 105 FN_IP10_12_9, FN_IP10_15_13, FN_IP10_18_16, FN_IP10_21_19, 106 FN_IP10_24_22, FN_AVS1, FN_AVS2, 107 108 /* IPSR0 */ 109 FN_PRESETOUT, FN_PWM1, FN_AUDATA0, FN_ARM_TRACEDATA_0, 110 FN_GPSCLK_C, FN_USB_OVC0, FN_TX2_E, FN_SDA2_B, 111 FN_AUDATA1, FN_ARM_TRACEDATA_1, FN_GPSIN_C, 112 FN_USB_OVC1, FN_RX2_E, FN_SCL2_B, FN_SD1_DAT2_A, 113 FN_MMC_D2, FN_BS, FN_ATADIR0_A, FN_SDSELF_A, 114 FN_PWM4_B, FN_SD1_DAT3_A, FN_MMC_D3, FN_A0, 115 FN_ATAG0_A, FN_REMOCON_B, FN_A4, FN_A5, 116 FN_A6, FN_A7, FN_A8, FN_A9, 117 FN_A10, FN_A11, FN_A12, FN_A13, 118 FN_A14, FN_A15, FN_A16, FN_A17, 119 FN_A18, FN_A19, 120 121 /* IPSR1 */ 122 FN_A20, FN_HSPI_CS1_B, FN_A21, FN_HSPI_CLK1_B, 123 FN_A22, FN_HRTS0_B, FN_RX2_B, FN_DREQ2_A, 124 FN_A23, FN_HTX0_B, FN_TX2_B, FN_DACK2_A, 125 FN_TS_SDEN0_A, FN_SD1_CD_A, FN_MMC_D6, FN_A24, 126 FN_DREQ1_A, FN_HRX0_B, FN_TS_SPSYNC0_A, 127 FN_SD1_WP_A, FN_MMC_D7, FN_A25, FN_DACK1_A, 128 FN_HCTS0_B, FN_RX3_C, FN_TS_SDAT0_A, FN_CLKOUT, 129 FN_HSPI_TX1_B, FN_PWM0_B, FN_CS0, FN_HSPI_RX1_B, 130 FN_SSI_SCK1_B, FN_ATAG0_B, FN_CS1_A26, FN_SDA2_A, 131 FN_SCK2_B, FN_MMC_D5, FN_ATADIR0_B, FN_RD_WR, 132 FN_WE1, FN_ATAWR0_B, FN_SSI_WS1_B, FN_EX_CS0, 133 FN_SCL2_A, FN_TX3_C, FN_TS_SCK0_A, FN_EX_CS1, 134 FN_MMC_D4, 135 136 /* IPSR2 */ 137 FN_SD1_CLK_A, FN_MMC_CLK, FN_ATACS00, FN_EX_CS2, 138 FN_SD1_CMD_A, FN_MMC_CMD, FN_ATACS10, FN_EX_CS3, 139 FN_SD1_DAT0_A, FN_MMC_D0, FN_ATARD0, FN_EX_CS4, 140 FN_EX_WAIT1_A, FN_SD1_DAT1_A, FN_MMC_D1, FN_ATAWR0_A, 141 FN_EX_CS5, FN_EX_WAIT2_A, FN_DREQ0_A, FN_RX3_A, 142 FN_DACK0, FN_TX3_A, FN_DRACK0, FN_EX_WAIT0, 143 FN_PWM0_C, FN_D0, FN_D1, FN_D2, 144 FN_D3, FN_D4, FN_D5, FN_D6, 145 FN_D7, FN_D8, FN_D9, FN_D10, 146 FN_D11, FN_RD_WR_B, FN_IRQ0, FN_MLB_CLK, 147 FN_IRQ1_A, 148 149 /* IPSR3 */ 150 FN_MLB_SIG, FN_RX5_B, FN_SDA3_A, FN_IRQ2_A, 151 FN_MLB_DAT, FN_TX5_B, FN_SCL3_A, FN_IRQ3_A, 152 FN_SDSELF_B, FN_SD1_CMD_B, FN_SCIF_CLK, FN_AUDIO_CLKOUT_B, 153 FN_CAN_CLK_B, FN_SDA3_B, FN_SD1_CLK_B, FN_HTX0_A, 154 FN_TX0_A, FN_SD1_DAT0_B, FN_HRX0_A, FN_RX0_A, 155 FN_SD1_DAT1_B, FN_HSCK0, FN_SCK0, FN_SCL3_B, 156 FN_SD1_DAT2_B, FN_HCTS0_A, FN_CTS0, FN_SD1_DAT3_B, 157 FN_HRTS0_A, FN_RTS0, FN_SSI_SCK4, FN_DU0_DR0, 158 FN_LCDOUT0, FN_AUDATA2, FN_ARM_TRACEDATA_2, 159 FN_SDA3_C, FN_ADICHS1, FN_TS_SDEN0_B, FN_SSI_WS4, 160 FN_DU0_DR1, FN_LCDOUT1, FN_AUDATA3, FN_ARM_TRACEDATA_3, 161 FN_SCL3_C, FN_ADICHS2, FN_TS_SPSYNC0_B, 162 FN_DU0_DR2, FN_LCDOUT2, FN_DU0_DR3, FN_LCDOUT3, 163 FN_DU0_DR4, FN_LCDOUT4, FN_DU0_DR5, FN_LCDOUT5, 164 FN_DU0_DR6, FN_LCDOUT6, 165 166 /* IPSR4 */ 167 FN_DU0_DR7, FN_LCDOUT7, FN_DU0_DG0, FN_LCDOUT8, 168 FN_AUDATA4, FN_ARM_TRACEDATA_4, FN_TX1_D, 169 FN_CAN0_TX_A, FN_ADICHS0, FN_DU0_DG1, FN_LCDOUT9, 170 FN_AUDATA5, FN_ARM_TRACEDATA_5, FN_RX1_D, 171 FN_CAN0_RX_A, FN_ADIDATA, FN_DU0_DG2, FN_LCDOUT10, 172 FN_DU0_DG3, FN_LCDOUT11, FN_DU0_DG4, FN_LCDOUT12, 173 FN_RX0_B, FN_DU0_DG5, FN_LCDOUT13, FN_TX0_B, 174 FN_DU0_DG6, FN_LCDOUT14, FN_RX4_A, FN_DU0_DG7, 175 FN_LCDOUT15, FN_TX4_A, FN_SSI_SCK2_B, FN_VI0_R0_B, 176 FN_DU0_DB0, FN_LCDOUT16, FN_AUDATA6, FN_ARM_TRACEDATA_6, 177 FN_GPSCLK_A, FN_PWM0_A, FN_ADICLK, FN_TS_SDAT0_B, 178 FN_AUDIO_CLKC, FN_VI0_R1_B, FN_DU0_DB1, FN_LCDOUT17, 179 FN_AUDATA7, FN_ARM_TRACEDATA_7, FN_GPSIN_A, 180 FN_ADICS_SAMP, FN_TS_SCK0_B, FN_VI0_R2_B, FN_DU0_DB2, 181 FN_LCDOUT18, FN_VI0_R3_B, FN_DU0_DB3, FN_LCDOUT19, 182 FN_VI0_R4_B, FN_DU0_DB4, FN_LCDOUT20, 183 184 /* IPSR5 */ 185 FN_VI0_R5_B, FN_DU0_DB5, FN_LCDOUT21, FN_VI1_DATA10_B, 186 FN_DU0_DB6, FN_LCDOUT22, FN_VI1_DATA11_B, 187 FN_DU0_DB7, FN_LCDOUT23, FN_DU0_DOTCLKIN, 188 FN_QSTVA_QVS, FN_DU0_DOTCLKO_UT0, FN_QCLK, 189 FN_DU0_DOTCLKO_UT1, FN_QSTVB_QVE, FN_AUDIO_CLKOUT_A, 190 FN_REMOCON_C, FN_SSI_WS2_B, FN_DU0_EXHSYNC_DU0_HSYNC, 191 FN_QSTH_QHS, FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 192 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 193 FN_QCPV_QDE, FN_FMCLK_D, FN_SSI_SCK1_A, FN_DU0_DISP, 194 FN_QPOLA, FN_AUDCK, FN_ARM_TRACECLK, 195 FN_BPFCLK_D, FN_SSI_WS1_A, FN_DU0_CDE, FN_QPOLB, 196 FN_AUDSYNC, FN_ARM_TRACECTL, FN_FMIN_D, 197 FN_SD1_CD_B, FN_SSI_SCK78, FN_HSPI_RX0_B, FN_TX1_B, 198 FN_SD1_WP_B, FN_SSI_WS78, FN_HSPI_CLK0_B, FN_RX1_B, 199 FN_CAN_CLK_D, FN_SSI_SDATA8, FN_SSI_SCK2_A, FN_HSPI_CS0_B, 200 FN_TX2_A, FN_CAN0_TX_B, FN_SSI_SDATA7, FN_HSPI_TX0_B, 201 FN_RX2_A, FN_CAN0_RX_B, 202 203 /* IPSR6 */ 204 FN_SSI_SCK6, FN_HSPI_RX2_A, FN_FMCLK_B, FN_CAN1_TX_B, 205 FN_SSI_WS6, FN_HSPI_CLK2_A, FN_BPFCLK_B, FN_CAN1_RX_B, 206 FN_SSI_SDATA6, FN_HSPI_TX2_A, FN_FMIN_B, FN_SSI_SCK5, 207 FN_RX4_C, FN_SSI_WS5, FN_TX4_C, FN_SSI_SDATA5, 208 FN_RX0_D, FN_SSI_WS34, FN_ARM_TRACEDATA_8, 209 FN_SSI_SDATA4, FN_SSI_WS2_A, FN_ARM_TRACEDATA_9, 210 FN_SSI_SDATA3, FN_ARM_TRACEDATA_10, 211 FN_SSI_SCK012, FN_ARM_TRACEDATA_11, 212 FN_TX0_D, FN_SSI_WS012, FN_ARM_TRACEDATA_12, 213 FN_SSI_SDATA2, FN_HSPI_CS2_A, FN_ARM_TRACEDATA_13, 214 FN_SDA1_A, FN_SSI_SDATA1, FN_ARM_TRACEDATA_14, 215 FN_SCL1_A, FN_SCK2_A, FN_SSI_SDATA0, 216 FN_ARM_TRACEDATA_15, 217 FN_SD0_CLK, FN_SUB_TDO, FN_SD0_CMD, FN_SUB_TRST, 218 FN_SD0_DAT0, FN_SUB_TMS, FN_SD0_DAT1, FN_SUB_TCK, 219 FN_SD0_DAT2, FN_SUB_TDI, 220 221 /* IPSR7 */ 222 FN_SD0_DAT3, FN_IRQ1_B, FN_SD0_CD, FN_TX5_A, 223 FN_SD0_WP, FN_RX5_A, FN_VI1_CLKENB, FN_HSPI_CLK0_A, 224 FN_HTX1_A, FN_RTS1_C, FN_VI1_FIELD, FN_HSPI_CS0_A, 225 FN_HRX1_A, FN_SCK1_C, FN_VI1_HSYNC, FN_HSPI_RX0_A, 226 FN_HRTS1_A, FN_FMCLK_A, FN_RX1_C, FN_VI1_VSYNC, 227 FN_HSPI_TX0, FN_HCTS1_A, FN_BPFCLK_A, FN_TX1_C, 228 FN_TCLK0, FN_HSCK1_A, FN_FMIN_A, FN_IRQ2_C, 229 FN_CTS1_C, FN_SPEEDIN, FN_VI0_CLK, FN_CAN_CLK_A, 230 FN_VI0_CLKENB, FN_SD2_DAT2_B, FN_VI1_DATA0, FN_DU1_DG6, 231 FN_HSPI_RX1_A, FN_RX4_B, FN_VI0_FIELD, FN_SD2_DAT3_B, 232 FN_VI0_R3_C, FN_VI1_DATA1, FN_DU1_DG7, FN_HSPI_CLK1_A, 233 FN_TX4_B, FN_VI0_HSYNC, FN_SD2_CD_B, FN_VI1_DATA2, 234 FN_DU1_DR2, FN_HSPI_CS1_A, FN_RX3_B, 235 236 /* IPSR8 */ 237 FN_VI0_VSYNC, FN_SD2_WP_B, FN_VI1_DATA3, FN_DU1_DR3, 238 FN_HSPI_TX1_A, FN_TX3_B, FN_VI0_DATA0_VI0_B0, 239 FN_DU1_DG2, FN_IRQ2_B, FN_RX3_D, FN_VI0_DATA1_VI0_B1, 240 FN_DU1_DG3, FN_IRQ3_B, FN_TX3_D, FN_VI0_DATA2_VI0_B2, 241 FN_DU1_DG4, FN_RX0_C, FN_VI0_DATA3_VI0_B3, 242 FN_DU1_DG5, FN_TX1_A, FN_TX0_C, FN_VI0_DATA4_VI0_B4, 243 FN_DU1_DB2, FN_RX1_A, FN_VI0_DATA5_VI0_B5, 244 FN_DU1_DB3, FN_SCK1_A, FN_PWM4, FN_HSCK1_B, 245 FN_VI0_DATA6_VI0_G0, FN_DU1_DB4, FN_CTS1_A, 246 FN_PWM5, FN_VI0_DATA7_VI0_G1, FN_DU1_DB5, 247 FN_RTS1_A, FN_VI0_G2, FN_SD2_CLK_B, FN_VI1_DATA4, 248 FN_DU1_DR4, FN_HTX1_B, FN_VI0_G3, FN_SD2_CMD_B, 249 FN_VI1_DATA5, FN_DU1_DR5, FN_HRX1_B, 250 251 /* IPSR9 */ 252 FN_VI0_G4, FN_SD2_DAT0_B, FN_VI1_DATA6, FN_DU1_DR6, 253 FN_HRTS1_B, FN_VI0_G5, FN_SD2_DAT1_B, FN_VI1_DATA7, 254 FN_DU1_DR7, FN_HCTS1_B, FN_VI0_R0_A, FN_VI1_CLK, 255 FN_ETH_REF_CLK, FN_DU1_DOTCLKIN, FN_VI0_R1_A, 256 FN_VI1_DATA8, FN_DU1_DB6, FN_ETH_TXD0, FN_PWM2, 257 FN_TCLK1, FN_VI0_R2_A, FN_VI1_DATA9, FN_DU1_DB7, 258 FN_ETH_TXD1, FN_PWM3, FN_VI0_R3_A, FN_ETH_CRS_DV, 259 FN_IECLK, FN_SCK2_C, FN_VI0_R4_A, FN_ETH_TX_EN, 260 FN_IETX, FN_TX2_C, FN_VI0_R5_A, FN_ETH_RX_ER, 261 FN_FMCLK_C, FN_IERX, FN_RX2_C, FN_VI1_DATA10_A, 262 FN_DU1_DOTCLKOUT, FN_ETH_RXD0, FN_BPFCLK_C, 263 FN_TX2_D, FN_SDA2_C, FN_VI1_DATA11_A, 264 FN_DU1_EXHSYNC_DU1_HSYNC, FN_ETH_RXD1, FN_FMIN_C, 265 FN_RX2_D, FN_SCL2_C, 266 267 /* IPSR10 */ 268 FN_SD2_CLK_A, FN_DU1_EXVSYNC_DU1_VSYNC, FN_ATARD1, 269 FN_ETH_MDC, FN_SDA1_B, FN_SD2_CMD_A, 270 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_ATAWR1, 271 FN_ETH_MDIO, FN_SCL1_B, FN_SD2_DAT0_A, FN_DU1_DISP, 272 FN_ATACS01, FN_DREQ1_B, FN_ETH_LINK, FN_CAN1_RX_A, 273 FN_SD2_DAT1_A, FN_DU1_CDE, FN_ATACS11, FN_DACK1_B, 274 FN_ETH_MAGIC, FN_CAN1_TX_A, FN_PWM6, FN_SD2_DAT2_A, 275 FN_VI1_DATA12, FN_DREQ2_B, FN_ATADIR1, FN_HSPI_CLK2_B, 276 FN_GPSCLK_B, FN_SD2_DAT3_A, FN_VI1_DATA13, FN_DACK2_B, 277 FN_ATAG1, FN_HSPI_CS2_B, FN_GPSIN_B, FN_SD2_CD_A, 278 FN_VI1_DATA14, FN_EX_WAIT1_B, FN_DREQ0_B, FN_HSPI_RX2_B, 279 FN_REMOCON_A, FN_SD2_WP_A, FN_VI1_DATA15, FN_EX_WAIT2_B, 280 FN_DACK0_B, FN_HSPI_TX2_B, FN_CAN_CLK_C, 281 282 /* SEL */ 283 FN_SEL_SCIF5_A, FN_SEL_SCIF5_B, 284 FN_SEL_SCIF4_A, FN_SEL_SCIF4_B, FN_SEL_SCIF4_C, 285 FN_SEL_SCIF3_A, FN_SEL_SCIF3_B, FN_SEL_SCIF3_C, FN_SEL_SCIF3_D, 286 FN_SEL_SCIF2_A, FN_SEL_SCIF2_B, FN_SEL_SCIF2_C, FN_SEL_SCIF2_D, FN_SEL_SCIF2_E, 287 FN_SEL_SCIF1_A, FN_SEL_SCIF1_B, FN_SEL_SCIF1_C, FN_SEL_SCIF1_D, 288 FN_SEL_SCIF0_A, FN_SEL_SCIF0_B, FN_SEL_SCIF0_C, FN_SEL_SCIF0_D, 289 FN_SEL_SSI2_A, FN_SEL_SSI2_B, 290 FN_SEL_SSI1_A, FN_SEL_SSI1_B, 291 FN_SEL_VI1_A, FN_SEL_VI1_B, 292 FN_SEL_VI0_A, FN_SEL_VI0_B, FN_SEL_VI0_C, FN_SEL_VI0_D, 293 FN_SEL_SD2_A, FN_SEL_SD2_B, 294 FN_SEL_SD1_A, FN_SEL_SD1_B, 295 FN_SEL_IRQ3_A, FN_SEL_IRQ3_B, 296 FN_SEL_IRQ2_A, FN_SEL_IRQ2_B, FN_SEL_IRQ2_C, 297 FN_SEL_IRQ1_A, FN_SEL_IRQ1_B, 298 FN_SEL_DREQ2_A, FN_SEL_DREQ2_B, 299 FN_SEL_DREQ1_A, FN_SEL_DREQ1_B, 300 FN_SEL_DREQ0_A, FN_SEL_DREQ0_B, 301 FN_SEL_WAIT2_A, FN_SEL_WAIT2_B, 302 FN_SEL_WAIT1_A, FN_SEL_WAIT1_B, 303 FN_SEL_CAN1_A, FN_SEL_CAN1_B, 304 FN_SEL_CAN0_A, FN_SEL_CAN0_B, 305 FN_SEL_CANCLK_A, FN_SEL_CANCLK_B, 306 FN_SEL_CANCLK_C, FN_SEL_CANCLK_D, 307 FN_SEL_HSCIF1_A, FN_SEL_HSCIF1_B, 308 FN_SEL_HSCIF0_A, FN_SEL_HSCIF0_B, 309 FN_SEL_REMOCON_A, FN_SEL_REMOCON_B, FN_SEL_REMOCON_C, 310 FN_SEL_FM_A, FN_SEL_FM_B, FN_SEL_FM_C, FN_SEL_FM_D, 311 FN_SEL_GPS_A, FN_SEL_GPS_B, FN_SEL_GPS_C, 312 FN_SEL_TSIF0_A, FN_SEL_TSIF0_B, 313 FN_SEL_HSPI2_A, FN_SEL_HSPI2_B, 314 FN_SEL_HSPI1_A, FN_SEL_HSPI1_B, 315 FN_SEL_HSPI0_A, FN_SEL_HSPI0_B, 316 FN_SEL_I2C3_A, FN_SEL_I2C3_B, FN_SEL_I2C3_C, 317 FN_SEL_I2C2_A, FN_SEL_I2C2_B, FN_SEL_I2C2_C, 318 FN_SEL_I2C1_A, FN_SEL_I2C1_B, 319 PINMUX_FUNCTION_END, 320 321 PINMUX_MARK_BEGIN, 322 323 /* GPSR0 */ 324 PENC0_MARK, PENC1_MARK, A1_MARK, A2_MARK, A3_MARK, 325 326 /* GPSR1 */ 327 WE0_MARK, 328 329 /* GPSR2 */ 330 AUDIO_CLKA_MARK, 331 AUDIO_CLKB_MARK, 332 333 /* GPSR3 */ 334 SSI_SCK34_MARK, 335 336 /* GPSR4 */ 337 AVS1_MARK, 338 AVS2_MARK, 339 340 VI0_R0_C_MARK, /* see sel_vi0 */ 341 VI0_R1_C_MARK, /* see sel_vi0 */ 342 VI0_R2_C_MARK, /* see sel_vi0 */ 343 /* VI0_R3_C_MARK, */ 344 VI0_R4_C_MARK, /* see sel_vi0 */ 345 VI0_R5_C_MARK, /* see sel_vi0 */ 346 347 VI0_R0_D_MARK, /* see sel_vi0 */ 348 VI0_R1_D_MARK, /* see sel_vi0 */ 349 VI0_R2_D_MARK, /* see sel_vi0 */ 350 VI0_R3_D_MARK, /* see sel_vi0 */ 351 VI0_R4_D_MARK, /* see sel_vi0 */ 352 VI0_R5_D_MARK, /* see sel_vi0 */ 353 354 /* IPSR0 */ 355 PRESETOUT_MARK, PWM1_MARK, AUDATA0_MARK, 356 ARM_TRACEDATA_0_MARK, GPSCLK_C_MARK, USB_OVC0_MARK, 357 TX2_E_MARK, SDA2_B_MARK, AUDATA1_MARK, ARM_TRACEDATA_1_MARK, 358 GPSIN_C_MARK, USB_OVC1_MARK, RX2_E_MARK, SCL2_B_MARK, 359 SD1_DAT2_A_MARK, MMC_D2_MARK, BS_MARK, 360 ATADIR0_A_MARK, SDSELF_A_MARK, PWM4_B_MARK, SD1_DAT3_A_MARK, 361 MMC_D3_MARK, A0_MARK, ATAG0_A_MARK, REMOCON_B_MARK, 362 A4_MARK, A5_MARK, A6_MARK, A7_MARK, 363 A8_MARK, A9_MARK, A10_MARK, A11_MARK, 364 A12_MARK, A13_MARK, A14_MARK, A15_MARK, 365 A16_MARK, A17_MARK, A18_MARK, A19_MARK, 366 367 /* IPSR1 */ 368 A20_MARK, HSPI_CS1_B_MARK, A21_MARK, 369 HSPI_CLK1_B_MARK, A22_MARK, HRTS0_B_MARK, 370 RX2_B_MARK, DREQ2_A_MARK, A23_MARK, HTX0_B_MARK, 371 TX2_B_MARK, DACK2_A_MARK, TS_SDEN0_A_MARK, 372 SD1_CD_A_MARK, MMC_D6_MARK, A24_MARK, DREQ1_A_MARK, 373 HRX0_B_MARK, TS_SPSYNC0_A_MARK, SD1_WP_A_MARK, 374 MMC_D7_MARK, A25_MARK, DACK1_A_MARK, HCTS0_B_MARK, 375 RX3_C_MARK, TS_SDAT0_A_MARK, CLKOUT_MARK, 376 HSPI_TX1_B_MARK, PWM0_B_MARK, CS0_MARK, 377 HSPI_RX1_B_MARK, SSI_SCK1_B_MARK, 378 ATAG0_B_MARK, CS1_A26_MARK, SDA2_A_MARK, SCK2_B_MARK, 379 MMC_D5_MARK, ATADIR0_B_MARK, RD_WR_MARK, WE1_MARK, 380 ATAWR0_B_MARK, SSI_WS1_B_MARK, EX_CS0_MARK, SCL2_A_MARK, 381 TX3_C_MARK, TS_SCK0_A_MARK, EX_CS1_MARK, MMC_D4_MARK, 382 383 /* IPSR2 */ 384 SD1_CLK_A_MARK, MMC_CLK_MARK, ATACS00_MARK, EX_CS2_MARK, 385 SD1_CMD_A_MARK, MMC_CMD_MARK, ATACS10_MARK, EX_CS3_MARK, 386 SD1_DAT0_A_MARK, MMC_D0_MARK, ATARD0_MARK, 387 EX_CS4_MARK, EX_WAIT1_A_MARK, SD1_DAT1_A_MARK, 388 MMC_D1_MARK, ATAWR0_A_MARK, EX_CS5_MARK, EX_WAIT2_A_MARK, 389 DREQ0_A_MARK, RX3_A_MARK, DACK0_MARK, TX3_A_MARK, 390 DRACK0_MARK, EX_WAIT0_MARK, PWM0_C_MARK, D0_MARK, 391 D1_MARK, D2_MARK, D3_MARK, D4_MARK, 392 D5_MARK, D6_MARK, D7_MARK, D8_MARK, 393 D9_MARK, D10_MARK, D11_MARK, RD_WR_B_MARK, 394 IRQ0_MARK, MLB_CLK_MARK, IRQ1_A_MARK, 395 396 /* IPSR3 */ 397 MLB_SIG_MARK, RX5_B_MARK, SDA3_A_MARK, IRQ2_A_MARK, 398 MLB_DAT_MARK, TX5_B_MARK, SCL3_A_MARK, IRQ3_A_MARK, 399 SDSELF_B_MARK, SD1_CMD_B_MARK, SCIF_CLK_MARK, AUDIO_CLKOUT_B_MARK, 400 CAN_CLK_B_MARK, SDA3_B_MARK, SD1_CLK_B_MARK, HTX0_A_MARK, 401 TX0_A_MARK, SD1_DAT0_B_MARK, HRX0_A_MARK, 402 RX0_A_MARK, SD1_DAT1_B_MARK, HSCK0_MARK, 403 SCK0_MARK, SCL3_B_MARK, SD1_DAT2_B_MARK, 404 HCTS0_A_MARK, CTS0_MARK, SD1_DAT3_B_MARK, 405 HRTS0_A_MARK, RTS0_MARK, SSI_SCK4_MARK, 406 DU0_DR0_MARK, LCDOUT0_MARK, AUDATA2_MARK, ARM_TRACEDATA_2_MARK, 407 SDA3_C_MARK, ADICHS1_MARK, TS_SDEN0_B_MARK, 408 SSI_WS4_MARK, DU0_DR1_MARK, LCDOUT1_MARK, AUDATA3_MARK, 409 ARM_TRACEDATA_3_MARK, SCL3_C_MARK, ADICHS2_MARK, 410 TS_SPSYNC0_B_MARK, DU0_DR2_MARK, LCDOUT2_MARK, 411 DU0_DR3_MARK, LCDOUT3_MARK, DU0_DR4_MARK, LCDOUT4_MARK, 412 DU0_DR5_MARK, LCDOUT5_MARK, DU0_DR6_MARK, LCDOUT6_MARK, 413 414 /* IPSR4 */ 415 DU0_DR7_MARK, LCDOUT7_MARK, DU0_DG0_MARK, LCDOUT8_MARK, 416 AUDATA4_MARK, ARM_TRACEDATA_4_MARK, 417 TX1_D_MARK, CAN0_TX_A_MARK, ADICHS0_MARK, DU0_DG1_MARK, 418 LCDOUT9_MARK, AUDATA5_MARK, ARM_TRACEDATA_5_MARK, 419 RX1_D_MARK, CAN0_RX_A_MARK, ADIDATA_MARK, DU0_DG2_MARK, 420 LCDOUT10_MARK, DU0_DG3_MARK, LCDOUT11_MARK, DU0_DG4_MARK, 421 LCDOUT12_MARK, RX0_B_MARK, DU0_DG5_MARK, LCDOUT13_MARK, 422 TX0_B_MARK, DU0_DG6_MARK, LCDOUT14_MARK, RX4_A_MARK, 423 DU0_DG7_MARK, LCDOUT15_MARK, TX4_A_MARK, SSI_SCK2_B_MARK, 424 VI0_R0_B_MARK, DU0_DB0_MARK, LCDOUT16_MARK, AUDATA6_MARK, 425 ARM_TRACEDATA_6_MARK, GPSCLK_A_MARK, PWM0_A_MARK, 426 ADICLK_MARK, TS_SDAT0_B_MARK, AUDIO_CLKC_MARK, 427 VI0_R1_B_MARK, DU0_DB1_MARK, LCDOUT17_MARK, AUDATA7_MARK, 428 ARM_TRACEDATA_7_MARK, GPSIN_A_MARK, ADICS_SAMP_MARK, 429 TS_SCK0_B_MARK, VI0_R2_B_MARK, DU0_DB2_MARK, LCDOUT18_MARK, 430 VI0_R3_B_MARK, DU0_DB3_MARK, LCDOUT19_MARK, VI0_R4_B_MARK, 431 DU0_DB4_MARK, LCDOUT20_MARK, 432 433 /* IPSR5 */ 434 VI0_R5_B_MARK, DU0_DB5_MARK, LCDOUT21_MARK, VI1_DATA10_B_MARK, 435 DU0_DB6_MARK, LCDOUT22_MARK, VI1_DATA11_B_MARK, 436 DU0_DB7_MARK, LCDOUT23_MARK, DU0_DOTCLKIN_MARK, 437 QSTVA_QVS_MARK, DU0_DOTCLKO_UT0_MARK, 438 QCLK_MARK, DU0_DOTCLKO_UT1_MARK, QSTVB_QVE_MARK, 439 AUDIO_CLKOUT_A_MARK, REMOCON_C_MARK, SSI_WS2_B_MARK, 440 DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK, 441 DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, 442 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, 443 QCPV_QDE_MARK, FMCLK_D_MARK, SSI_SCK1_A_MARK, 444 DU0_DISP_MARK, QPOLA_MARK, AUDCK_MARK, ARM_TRACECLK_MARK, 445 BPFCLK_D_MARK, SSI_WS1_A_MARK, DU0_CDE_MARK, QPOLB_MARK, 446 AUDSYNC_MARK, ARM_TRACECTL_MARK, FMIN_D_MARK, 447 SD1_CD_B_MARK, SSI_SCK78_MARK, HSPI_RX0_B_MARK, 448 TX1_B_MARK, SD1_WP_B_MARK, SSI_WS78_MARK, HSPI_CLK0_B_MARK, 449 RX1_B_MARK, CAN_CLK_D_MARK, SSI_SDATA8_MARK, 450 SSI_SCK2_A_MARK, HSPI_CS0_B_MARK, 451 TX2_A_MARK, CAN0_TX_B_MARK, SSI_SDATA7_MARK, 452 HSPI_TX0_B_MARK, RX2_A_MARK, CAN0_RX_B_MARK, 453 454 /* IPSR6 */ 455 SSI_SCK6_MARK, HSPI_RX2_A_MARK, FMCLK_B_MARK, 456 CAN1_TX_B_MARK, SSI_WS6_MARK, HSPI_CLK2_A_MARK, 457 BPFCLK_B_MARK, CAN1_RX_B_MARK, SSI_SDATA6_MARK, 458 HSPI_TX2_A_MARK, FMIN_B_MARK, SSI_SCK5_MARK, 459 RX4_C_MARK, SSI_WS5_MARK, TX4_C_MARK, SSI_SDATA5_MARK, 460 RX0_D_MARK, SSI_WS34_MARK, ARM_TRACEDATA_8_MARK, 461 SSI_SDATA4_MARK, SSI_WS2_A_MARK, ARM_TRACEDATA_9_MARK, 462 SSI_SDATA3_MARK, ARM_TRACEDATA_10_MARK, 463 SSI_SCK012_MARK, ARM_TRACEDATA_11_MARK, 464 TX0_D_MARK, SSI_WS012_MARK, ARM_TRACEDATA_12_MARK, 465 SSI_SDATA2_MARK, HSPI_CS2_A_MARK, 466 ARM_TRACEDATA_13_MARK, SDA1_A_MARK, SSI_SDATA1_MARK, 467 ARM_TRACEDATA_14_MARK, SCL1_A_MARK, SCK2_A_MARK, 468 SSI_SDATA0_MARK, ARM_TRACEDATA_15_MARK, 469 SD0_CLK_MARK, SUB_TDO_MARK, SD0_CMD_MARK, SUB_TRST_MARK, 470 SD0_DAT0_MARK, SUB_TMS_MARK, SD0_DAT1_MARK, SUB_TCK_MARK, 471 SD0_DAT2_MARK, SUB_TDI_MARK, 472 473 /* IPSR7 */ 474 SD0_DAT3_MARK, IRQ1_B_MARK, SD0_CD_MARK, TX5_A_MARK, 475 SD0_WP_MARK, RX5_A_MARK, VI1_CLKENB_MARK, 476 HSPI_CLK0_A_MARK, HTX1_A_MARK, RTS1_C_MARK, VI1_FIELD_MARK, 477 HSPI_CS0_A_MARK, HRX1_A_MARK, SCK1_C_MARK, VI1_HSYNC_MARK, 478 HSPI_RX0_A_MARK, HRTS1_A_MARK, FMCLK_A_MARK, RX1_C_MARK, 479 VI1_VSYNC_MARK, HSPI_TX0_MARK, HCTS1_A_MARK, BPFCLK_A_MARK, 480 TX1_C_MARK, TCLK0_MARK, HSCK1_A_MARK, FMIN_A_MARK, 481 IRQ2_C_MARK, CTS1_C_MARK, SPEEDIN_MARK, VI0_CLK_MARK, 482 CAN_CLK_A_MARK, VI0_CLKENB_MARK, SD2_DAT2_B_MARK, 483 VI1_DATA0_MARK, DU1_DG6_MARK, HSPI_RX1_A_MARK, 484 RX4_B_MARK, VI0_FIELD_MARK, SD2_DAT3_B_MARK, 485 VI0_R3_C_MARK, VI1_DATA1_MARK, DU1_DG7_MARK, HSPI_CLK1_A_MARK, 486 TX4_B_MARK, VI0_HSYNC_MARK, SD2_CD_B_MARK, VI1_DATA2_MARK, 487 DU1_DR2_MARK, HSPI_CS1_A_MARK, RX3_B_MARK, 488 489 /* IPSR8 */ 490 VI0_VSYNC_MARK, SD2_WP_B_MARK, VI1_DATA3_MARK, DU1_DR3_MARK, 491 HSPI_TX1_A_MARK, TX3_B_MARK, VI0_DATA0_VI0_B0_MARK, 492 DU1_DG2_MARK, IRQ2_B_MARK, RX3_D_MARK, VI0_DATA1_VI0_B1_MARK, 493 DU1_DG3_MARK, IRQ3_B_MARK, TX3_D_MARK, VI0_DATA2_VI0_B2_MARK, 494 DU1_DG4_MARK, RX0_C_MARK, VI0_DATA3_VI0_B3_MARK, 495 DU1_DG5_MARK, TX1_A_MARK, TX0_C_MARK, VI0_DATA4_VI0_B4_MARK, 496 DU1_DB2_MARK, RX1_A_MARK, VI0_DATA5_VI0_B5_MARK, 497 DU1_DB3_MARK, SCK1_A_MARK, PWM4_MARK, HSCK1_B_MARK, 498 VI0_DATA6_VI0_G0_MARK, DU1_DB4_MARK, CTS1_A_MARK, 499 PWM5_MARK, VI0_DATA7_VI0_G1_MARK, DU1_DB5_MARK, 500 RTS1_A_MARK, VI0_G2_MARK, SD2_CLK_B_MARK, VI1_DATA4_MARK, 501 DU1_DR4_MARK, HTX1_B_MARK, VI0_G3_MARK, SD2_CMD_B_MARK, 502 VI1_DATA5_MARK, DU1_DR5_MARK, HRX1_B_MARK, 503 504 /* IPSR9 */ 505 VI0_G4_MARK, SD2_DAT0_B_MARK, VI1_DATA6_MARK, 506 DU1_DR6_MARK, HRTS1_B_MARK, VI0_G5_MARK, SD2_DAT1_B_MARK, 507 VI1_DATA7_MARK, DU1_DR7_MARK, HCTS1_B_MARK, VI0_R0_A_MARK, 508 VI1_CLK_MARK, ETH_REF_CLK_MARK, DU1_DOTCLKIN_MARK, 509 VI0_R1_A_MARK, VI1_DATA8_MARK, DU1_DB6_MARK, ETH_TXD0_MARK, 510 PWM2_MARK, TCLK1_MARK, VI0_R2_A_MARK, VI1_DATA9_MARK, 511 DU1_DB7_MARK, ETH_TXD1_MARK, PWM3_MARK, VI0_R3_A_MARK, 512 ETH_CRS_DV_MARK, IECLK_MARK, SCK2_C_MARK, 513 VI0_R4_A_MARK, ETH_TX_EN_MARK, IETX_MARK, 514 TX2_C_MARK, VI0_R5_A_MARK, ETH_RX_ER_MARK, FMCLK_C_MARK, 515 IERX_MARK, RX2_C_MARK, VI1_DATA10_A_MARK, 516 DU1_DOTCLKOUT_MARK, ETH_RXD0_MARK, 517 BPFCLK_C_MARK, TX2_D_MARK, SDA2_C_MARK, VI1_DATA11_A_MARK, 518 DU1_EXHSYNC_DU1_HSYNC_MARK, ETH_RXD1_MARK, FMIN_C_MARK, 519 RX2_D_MARK, SCL2_C_MARK, 520 521 /* IPSR10 */ 522 SD2_CLK_A_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, ATARD1_MARK, 523 ETH_MDC_MARK, SDA1_B_MARK, SD2_CMD_A_MARK, 524 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, ATAWR1_MARK, 525 ETH_MDIO_MARK, SCL1_B_MARK, SD2_DAT0_A_MARK, 526 DU1_DISP_MARK, ATACS01_MARK, DREQ1_B_MARK, ETH_LINK_MARK, 527 CAN1_RX_A_MARK, SD2_DAT1_A_MARK, DU1_CDE_MARK, 528 ATACS11_MARK, DACK1_B_MARK, ETH_MAGIC_MARK, CAN1_TX_A_MARK, 529 PWM6_MARK, SD2_DAT2_A_MARK, VI1_DATA12_MARK, 530 DREQ2_B_MARK, ATADIR1_MARK, HSPI_CLK2_B_MARK, 531 GPSCLK_B_MARK, SD2_DAT3_A_MARK, VI1_DATA13_MARK, 532 DACK2_B_MARK, ATAG1_MARK, HSPI_CS2_B_MARK, 533 GPSIN_B_MARK, SD2_CD_A_MARK, VI1_DATA14_MARK, 534 EX_WAIT1_B_MARK, DREQ0_B_MARK, HSPI_RX2_B_MARK, 535 REMOCON_A_MARK, SD2_WP_A_MARK, VI1_DATA15_MARK, 536 EX_WAIT2_B_MARK, DACK0_B_MARK, 537 HSPI_TX2_B_MARK, CAN_CLK_C_MARK, 538 539 PINMUX_MARK_END, 540 }; 541 542 static const u16 pinmux_data[] = { 543 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ 544 545 PINMUX_DATA(PENC0_MARK, FN_PENC0), 546 PINMUX_DATA(PENC1_MARK, FN_PENC1), 547 PINMUX_DATA(A1_MARK, FN_A1), 548 PINMUX_DATA(A2_MARK, FN_A2), 549 PINMUX_DATA(A3_MARK, FN_A3), 550 PINMUX_DATA(WE0_MARK, FN_WE0), 551 PINMUX_DATA(AUDIO_CLKA_MARK, FN_AUDIO_CLKA), 552 PINMUX_DATA(AUDIO_CLKB_MARK, FN_AUDIO_CLKB), 553 PINMUX_DATA(SSI_SCK34_MARK, FN_SSI_SCK34), 554 PINMUX_DATA(AVS1_MARK, FN_AVS1), 555 PINMUX_DATA(AVS2_MARK, FN_AVS2), 556 557 /* IPSR0 */ 558 PINMUX_IPSR_DATA(IP0_1_0, PRESETOUT), 559 PINMUX_IPSR_DATA(IP0_1_0, PWM1), 560 561 PINMUX_IPSR_DATA(IP0_4_2, AUDATA0), 562 PINMUX_IPSR_DATA(IP0_4_2, ARM_TRACEDATA_0), 563 PINMUX_IPSR_MSEL(IP0_4_2, GPSCLK_C, SEL_GPS_C), 564 PINMUX_IPSR_DATA(IP0_4_2, USB_OVC0), 565 PINMUX_IPSR_DATA(IP0_4_2, TX2_E), 566 PINMUX_IPSR_MSEL(IP0_4_2, SDA2_B, SEL_I2C2_B), 567 568 PINMUX_IPSR_DATA(IP0_7_5, AUDATA1), 569 PINMUX_IPSR_DATA(IP0_7_5, ARM_TRACEDATA_1), 570 PINMUX_IPSR_MSEL(IP0_7_5, GPSIN_C, SEL_GPS_C), 571 PINMUX_IPSR_DATA(IP0_7_5, USB_OVC1), 572 PINMUX_IPSR_MSEL(IP0_7_5, RX2_E, SEL_SCIF2_E), 573 PINMUX_IPSR_MSEL(IP0_7_5, SCL2_B, SEL_I2C2_B), 574 575 PINMUX_IPSR_MSEL(IP0_11_8, SD1_DAT2_A, SEL_SD1_A), 576 PINMUX_IPSR_DATA(IP0_11_8, MMC_D2), 577 PINMUX_IPSR_DATA(IP0_11_8, BS), 578 PINMUX_IPSR_DATA(IP0_11_8, ATADIR0_A), 579 PINMUX_IPSR_DATA(IP0_11_8, SDSELF_A), 580 PINMUX_IPSR_DATA(IP0_11_8, PWM4_B), 581 582 PINMUX_IPSR_MSEL(IP0_14_12, SD1_DAT3_A, SEL_SD1_A), 583 PINMUX_IPSR_DATA(IP0_14_12, MMC_D3), 584 PINMUX_IPSR_DATA(IP0_14_12, A0), 585 PINMUX_IPSR_DATA(IP0_14_12, ATAG0_A), 586 PINMUX_IPSR_MSEL(IP0_14_12, REMOCON_B, SEL_REMOCON_B), 587 588 PINMUX_IPSR_DATA(IP0_15, A4), 589 PINMUX_IPSR_DATA(IP0_16, A5), 590 PINMUX_IPSR_DATA(IP0_17, A6), 591 PINMUX_IPSR_DATA(IP0_18, A7), 592 PINMUX_IPSR_DATA(IP0_19, A8), 593 PINMUX_IPSR_DATA(IP0_20, A9), 594 PINMUX_IPSR_DATA(IP0_21, A10), 595 PINMUX_IPSR_DATA(IP0_22, A11), 596 PINMUX_IPSR_DATA(IP0_23, A12), 597 PINMUX_IPSR_DATA(IP0_24, A13), 598 PINMUX_IPSR_DATA(IP0_25, A14), 599 PINMUX_IPSR_DATA(IP0_26, A15), 600 PINMUX_IPSR_DATA(IP0_27, A16), 601 PINMUX_IPSR_DATA(IP0_28, A17), 602 PINMUX_IPSR_DATA(IP0_29, A18), 603 PINMUX_IPSR_DATA(IP0_30, A19), 604 605 /* IPSR1 */ 606 PINMUX_IPSR_DATA(IP1_0, A20), 607 PINMUX_IPSR_MSEL(IP1_0, HSPI_CS1_B, SEL_HSPI1_B), 608 609 PINMUX_IPSR_DATA(IP1_1, A21), 610 PINMUX_IPSR_MSEL(IP1_1, HSPI_CLK1_B, SEL_HSPI1_B), 611 612 PINMUX_IPSR_DATA(IP1_4_2, A22), 613 PINMUX_IPSR_MSEL(IP1_4_2, HRTS0_B, SEL_HSCIF0_B), 614 PINMUX_IPSR_MSEL(IP1_4_2, RX2_B, SEL_SCIF2_B), 615 PINMUX_IPSR_MSEL(IP1_4_2, DREQ2_A, SEL_DREQ2_A), 616 617 PINMUX_IPSR_DATA(IP1_7_5, A23), 618 PINMUX_IPSR_DATA(IP1_7_5, HTX0_B), 619 PINMUX_IPSR_DATA(IP1_7_5, TX2_B), 620 PINMUX_IPSR_DATA(IP1_7_5, DACK2_A), 621 PINMUX_IPSR_MSEL(IP1_7_5, TS_SDEN0_A, SEL_TSIF0_A), 622 623 PINMUX_IPSR_MSEL(IP1_10_8, SD1_CD_A, SEL_SD1_A), 624 PINMUX_IPSR_DATA(IP1_10_8, MMC_D6), 625 PINMUX_IPSR_DATA(IP1_10_8, A24), 626 PINMUX_IPSR_MSEL(IP1_10_8, DREQ1_A, SEL_DREQ1_A), 627 PINMUX_IPSR_MSEL(IP1_10_8, HRX0_B, SEL_HSCIF0_B), 628 PINMUX_IPSR_MSEL(IP1_10_8, TS_SPSYNC0_A, SEL_TSIF0_A), 629 630 PINMUX_IPSR_MSEL(IP1_14_11, SD1_WP_A, SEL_SD1_A), 631 PINMUX_IPSR_DATA(IP1_14_11, MMC_D7), 632 PINMUX_IPSR_DATA(IP1_14_11, A25), 633 PINMUX_IPSR_DATA(IP1_14_11, DACK1_A), 634 PINMUX_IPSR_MSEL(IP1_14_11, HCTS0_B, SEL_HSCIF0_B), 635 PINMUX_IPSR_MSEL(IP1_14_11, RX3_C, SEL_SCIF3_C), 636 PINMUX_IPSR_MSEL(IP1_14_11, TS_SDAT0_A, SEL_TSIF0_A), 637 638 PINMUX_IPSR_NOGP(IP1_16_15, CLKOUT), 639 PINMUX_IPSR_NOGP(IP1_16_15, HSPI_TX1_B), 640 PINMUX_IPSR_NOGP(IP1_16_15, PWM0_B), 641 642 PINMUX_IPSR_NOGP(IP1_17, CS0), 643 PINMUX_IPSR_NOGM(IP1_17, HSPI_RX1_B, SEL_HSPI1_B), 644 645 PINMUX_IPSR_NOGM(IP1_20_18, SSI_SCK1_B, SEL_SSI1_B), 646 PINMUX_IPSR_NOGP(IP1_20_18, ATAG0_B), 647 PINMUX_IPSR_NOGP(IP1_20_18, CS1_A26), 648 PINMUX_IPSR_NOGM(IP1_20_18, SDA2_A, SEL_I2C2_A), 649 PINMUX_IPSR_NOGM(IP1_20_18, SCK2_B, SEL_SCIF2_B), 650 651 PINMUX_IPSR_DATA(IP1_23_21, MMC_D5), 652 PINMUX_IPSR_DATA(IP1_23_21, ATADIR0_B), 653 PINMUX_IPSR_DATA(IP1_23_21, RD_WR), 654 655 PINMUX_IPSR_DATA(IP1_24, WE1), 656 PINMUX_IPSR_DATA(IP1_24, ATAWR0_B), 657 658 PINMUX_IPSR_MSEL(IP1_27_25, SSI_WS1_B, SEL_SSI1_B), 659 PINMUX_IPSR_DATA(IP1_27_25, EX_CS0), 660 PINMUX_IPSR_MSEL(IP1_27_25, SCL2_A, SEL_I2C2_A), 661 PINMUX_IPSR_DATA(IP1_27_25, TX3_C), 662 PINMUX_IPSR_MSEL(IP1_27_25, TS_SCK0_A, SEL_TSIF0_A), 663 664 PINMUX_IPSR_DATA(IP1_29_28, EX_CS1), 665 PINMUX_IPSR_DATA(IP1_29_28, MMC_D4), 666 667 /* IPSR2 */ 668 PINMUX_IPSR_DATA(IP2_2_0, SD1_CLK_A), 669 PINMUX_IPSR_DATA(IP2_2_0, MMC_CLK), 670 PINMUX_IPSR_DATA(IP2_2_0, ATACS00), 671 PINMUX_IPSR_DATA(IP2_2_0, EX_CS2), 672 673 PINMUX_IPSR_MSEL(IP2_5_3, SD1_CMD_A, SEL_SD1_A), 674 PINMUX_IPSR_DATA(IP2_5_3, MMC_CMD), 675 PINMUX_IPSR_DATA(IP2_5_3, ATACS10), 676 PINMUX_IPSR_DATA(IP2_5_3, EX_CS3), 677 678 PINMUX_IPSR_MSEL(IP2_8_6, SD1_DAT0_A, SEL_SD1_A), 679 PINMUX_IPSR_DATA(IP2_8_6, MMC_D0), 680 PINMUX_IPSR_DATA(IP2_8_6, ATARD0), 681 PINMUX_IPSR_DATA(IP2_8_6, EX_CS4), 682 PINMUX_IPSR_MSEL(IP2_8_6, EX_WAIT1_A, SEL_WAIT1_A), 683 684 PINMUX_IPSR_MSEL(IP2_11_9, SD1_DAT1_A, SEL_SD1_A), 685 PINMUX_IPSR_DATA(IP2_11_9, MMC_D1), 686 PINMUX_IPSR_DATA(IP2_11_9, ATAWR0_A), 687 PINMUX_IPSR_DATA(IP2_11_9, EX_CS5), 688 PINMUX_IPSR_MSEL(IP2_11_9, EX_WAIT2_A, SEL_WAIT2_A), 689 690 PINMUX_IPSR_MSEL(IP2_13_12, DREQ0_A, SEL_DREQ0_A), 691 PINMUX_IPSR_MSEL(IP2_13_12, RX3_A, SEL_SCIF3_A), 692 693 PINMUX_IPSR_DATA(IP2_16_14, DACK0), 694 PINMUX_IPSR_DATA(IP2_16_14, TX3_A), 695 PINMUX_IPSR_DATA(IP2_16_14, DRACK0), 696 697 PINMUX_IPSR_DATA(IP2_17, EX_WAIT0), 698 PINMUX_IPSR_DATA(IP2_17, PWM0_C), 699 700 PINMUX_IPSR_NOGP(IP2_18, D0), 701 PINMUX_IPSR_NOGP(IP2_19, D1), 702 PINMUX_IPSR_NOGP(IP2_20, D2), 703 PINMUX_IPSR_NOGP(IP2_21, D3), 704 PINMUX_IPSR_NOGP(IP2_22, D4), 705 PINMUX_IPSR_NOGP(IP2_23, D5), 706 PINMUX_IPSR_NOGP(IP2_24, D6), 707 PINMUX_IPSR_NOGP(IP2_25, D7), 708 PINMUX_IPSR_NOGP(IP2_26, D8), 709 PINMUX_IPSR_NOGP(IP2_27, D9), 710 PINMUX_IPSR_NOGP(IP2_28, D10), 711 PINMUX_IPSR_NOGP(IP2_29, D11), 712 713 PINMUX_IPSR_DATA(IP2_30, RD_WR_B), 714 PINMUX_IPSR_DATA(IP2_30, IRQ0), 715 716 PINMUX_IPSR_DATA(IP2_31, MLB_CLK), 717 PINMUX_IPSR_MSEL(IP2_31, IRQ1_A, SEL_IRQ1_A), 718 719 /* IPSR3 */ 720 PINMUX_IPSR_DATA(IP3_1_0, MLB_SIG), 721 PINMUX_IPSR_MSEL(IP3_1_0, RX5_B, SEL_SCIF5_B), 722 PINMUX_IPSR_MSEL(IP3_1_0, SDA3_A, SEL_I2C3_A), 723 PINMUX_IPSR_MSEL(IP3_1_0, IRQ2_A, SEL_IRQ2_A), 724 725 PINMUX_IPSR_DATA(IP3_4_2, MLB_DAT), 726 PINMUX_IPSR_DATA(IP3_4_2, TX5_B), 727 PINMUX_IPSR_MSEL(IP3_4_2, SCL3_A, SEL_I2C3_A), 728 PINMUX_IPSR_MSEL(IP3_4_2, IRQ3_A, SEL_IRQ3_A), 729 PINMUX_IPSR_DATA(IP3_4_2, SDSELF_B), 730 731 PINMUX_IPSR_MSEL(IP3_7_5, SD1_CMD_B, SEL_SD1_B), 732 PINMUX_IPSR_DATA(IP3_7_5, SCIF_CLK), 733 PINMUX_IPSR_DATA(IP3_7_5, AUDIO_CLKOUT_B), 734 PINMUX_IPSR_MSEL(IP3_7_5, CAN_CLK_B, SEL_CANCLK_B), 735 PINMUX_IPSR_MSEL(IP3_7_5, SDA3_B, SEL_I2C3_B), 736 737 PINMUX_IPSR_DATA(IP3_9_8, SD1_CLK_B), 738 PINMUX_IPSR_DATA(IP3_9_8, HTX0_A), 739 PINMUX_IPSR_DATA(IP3_9_8, TX0_A), 740 741 PINMUX_IPSR_MSEL(IP3_12_10, SD1_DAT0_B, SEL_SD1_B), 742 PINMUX_IPSR_MSEL(IP3_12_10, HRX0_A, SEL_HSCIF0_A), 743 PINMUX_IPSR_MSEL(IP3_12_10, RX0_A, SEL_SCIF0_A), 744 745 PINMUX_IPSR_MSEL(IP3_15_13, SD1_DAT1_B, SEL_SD1_B), 746 PINMUX_IPSR_MSEL(IP3_15_13, HSCK0, SEL_HSCIF0_A), 747 PINMUX_IPSR_DATA(IP3_15_13, SCK0), 748 PINMUX_IPSR_MSEL(IP3_15_13, SCL3_B, SEL_I2C3_B), 749 750 PINMUX_IPSR_MSEL(IP3_18_16, SD1_DAT2_B, SEL_SD1_B), 751 PINMUX_IPSR_MSEL(IP3_18_16, HCTS0_A, SEL_HSCIF0_A), 752 PINMUX_IPSR_DATA(IP3_18_16, CTS0), 753 754 PINMUX_IPSR_MSEL(IP3_20_19, SD1_DAT3_B, SEL_SD1_B), 755 PINMUX_IPSR_MSEL(IP3_20_19, HRTS0_A, SEL_HSCIF0_A), 756 PINMUX_IPSR_DATA(IP3_20_19, RTS0), 757 758 PINMUX_IPSR_DATA(IP3_23_21, SSI_SCK4), 759 PINMUX_IPSR_DATA(IP3_23_21, DU0_DR0), 760 PINMUX_IPSR_DATA(IP3_23_21, LCDOUT0), 761 PINMUX_IPSR_DATA(IP3_23_21, AUDATA2), 762 PINMUX_IPSR_DATA(IP3_23_21, ARM_TRACEDATA_2), 763 PINMUX_IPSR_MSEL(IP3_23_21, SDA3_C, SEL_I2C3_C), 764 PINMUX_IPSR_DATA(IP3_23_21, ADICHS1), 765 PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN0_B, SEL_TSIF0_B), 766 767 PINMUX_IPSR_DATA(IP3_26_24, SSI_WS4), 768 PINMUX_IPSR_DATA(IP3_26_24, DU0_DR1), 769 PINMUX_IPSR_DATA(IP3_26_24, LCDOUT1), 770 PINMUX_IPSR_DATA(IP3_26_24, AUDATA3), 771 PINMUX_IPSR_DATA(IP3_26_24, ARM_TRACEDATA_3), 772 PINMUX_IPSR_MSEL(IP3_26_24, SCL3_C, SEL_I2C3_C), 773 PINMUX_IPSR_DATA(IP3_26_24, ADICHS2), 774 PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC0_B, SEL_TSIF0_B), 775 776 PINMUX_IPSR_DATA(IP3_27, DU0_DR2), 777 PINMUX_IPSR_DATA(IP3_27, LCDOUT2), 778 779 PINMUX_IPSR_DATA(IP3_28, DU0_DR3), 780 PINMUX_IPSR_DATA(IP3_28, LCDOUT3), 781 782 PINMUX_IPSR_DATA(IP3_29, DU0_DR4), 783 PINMUX_IPSR_DATA(IP3_29, LCDOUT4), 784 785 PINMUX_IPSR_DATA(IP3_30, DU0_DR5), 786 PINMUX_IPSR_DATA(IP3_30, LCDOUT5), 787 788 PINMUX_IPSR_DATA(IP3_31, DU0_DR6), 789 PINMUX_IPSR_DATA(IP3_31, LCDOUT6), 790 791 /* IPSR4 */ 792 PINMUX_IPSR_DATA(IP4_0, DU0_DR7), 793 PINMUX_IPSR_DATA(IP4_0, LCDOUT7), 794 795 PINMUX_IPSR_DATA(IP4_3_1, DU0_DG0), 796 PINMUX_IPSR_DATA(IP4_3_1, LCDOUT8), 797 PINMUX_IPSR_DATA(IP4_3_1, AUDATA4), 798 PINMUX_IPSR_DATA(IP4_3_1, ARM_TRACEDATA_4), 799 PINMUX_IPSR_DATA(IP4_3_1, TX1_D), 800 PINMUX_IPSR_DATA(IP4_3_1, CAN0_TX_A), 801 PINMUX_IPSR_DATA(IP4_3_1, ADICHS0), 802 803 PINMUX_IPSR_DATA(IP4_6_4, DU0_DG1), 804 PINMUX_IPSR_DATA(IP4_6_4, LCDOUT9), 805 PINMUX_IPSR_DATA(IP4_6_4, AUDATA5), 806 PINMUX_IPSR_DATA(IP4_6_4, ARM_TRACEDATA_5), 807 PINMUX_IPSR_MSEL(IP4_6_4, RX1_D, SEL_SCIF1_D), 808 PINMUX_IPSR_MSEL(IP4_6_4, CAN0_RX_A, SEL_CAN0_A), 809 PINMUX_IPSR_DATA(IP4_6_4, ADIDATA), 810 811 PINMUX_IPSR_DATA(IP4_7, DU0_DG2), 812 PINMUX_IPSR_DATA(IP4_7, LCDOUT10), 813 814 PINMUX_IPSR_DATA(IP4_8, DU0_DG3), 815 PINMUX_IPSR_DATA(IP4_8, LCDOUT11), 816 817 PINMUX_IPSR_DATA(IP4_10_9, DU0_DG4), 818 PINMUX_IPSR_DATA(IP4_10_9, LCDOUT12), 819 PINMUX_IPSR_MSEL(IP4_10_9, RX0_B, SEL_SCIF0_B), 820 821 PINMUX_IPSR_DATA(IP4_12_11, DU0_DG5), 822 PINMUX_IPSR_DATA(IP4_12_11, LCDOUT13), 823 PINMUX_IPSR_DATA(IP4_12_11, TX0_B), 824 825 PINMUX_IPSR_DATA(IP4_14_13, DU0_DG6), 826 PINMUX_IPSR_DATA(IP4_14_13, LCDOUT14), 827 PINMUX_IPSR_MSEL(IP4_14_13, RX4_A, SEL_SCIF4_A), 828 829 PINMUX_IPSR_DATA(IP4_16_15, DU0_DG7), 830 PINMUX_IPSR_DATA(IP4_16_15, LCDOUT15), 831 PINMUX_IPSR_DATA(IP4_16_15, TX4_A), 832 833 PINMUX_IPSR_MSEL(IP4_20_17, SSI_SCK2_B, SEL_SSI2_B), 834 PINMUX_DATA(VI0_R0_B_MARK, FN_IP4_20_17, FN_VI0_R0_B, FN_SEL_VI0_B), /* see sel_vi0 */ 835 PINMUX_DATA(VI0_R0_D_MARK, FN_IP4_20_17, FN_VI0_R0_B, FN_SEL_VI0_D), /* see sel_vi0 */ 836 PINMUX_IPSR_DATA(IP4_20_17, DU0_DB0), 837 PINMUX_IPSR_DATA(IP4_20_17, LCDOUT16), 838 PINMUX_IPSR_DATA(IP4_20_17, AUDATA6), 839 PINMUX_IPSR_DATA(IP4_20_17, ARM_TRACEDATA_6), 840 PINMUX_IPSR_MSEL(IP4_20_17, GPSCLK_A, SEL_GPS_A), 841 PINMUX_IPSR_DATA(IP4_20_17, PWM0_A), 842 PINMUX_IPSR_DATA(IP4_20_17, ADICLK), 843 PINMUX_IPSR_MSEL(IP4_20_17, TS_SDAT0_B, SEL_TSIF0_B), 844 845 PINMUX_IPSR_DATA(IP4_24_21, AUDIO_CLKC), 846 PINMUX_DATA(VI0_R1_B_MARK, FN_IP4_24_21, FN_VI0_R1_B, FN_SEL_VI0_B), /* see sel_vi0 */ 847 PINMUX_DATA(VI0_R1_D_MARK, FN_IP4_24_21, FN_VI0_R1_B, FN_SEL_VI0_D), /* see sel_vi0 */ 848 PINMUX_IPSR_DATA(IP4_24_21, DU0_DB1), 849 PINMUX_IPSR_DATA(IP4_24_21, LCDOUT17), 850 PINMUX_IPSR_DATA(IP4_24_21, AUDATA7), 851 PINMUX_IPSR_DATA(IP4_24_21, ARM_TRACEDATA_7), 852 PINMUX_IPSR_MSEL(IP4_24_21, GPSIN_A, SEL_GPS_A), 853 PINMUX_IPSR_DATA(IP4_24_21, ADICS_SAMP), 854 PINMUX_IPSR_MSEL(IP4_24_21, TS_SCK0_B, SEL_TSIF0_B), 855 856 PINMUX_DATA(VI0_R2_B_MARK, FN_IP4_26_25, FN_VI0_R2_B, FN_SEL_VI0_B), /* see sel_vi0 */ 857 PINMUX_DATA(VI0_R2_D_MARK, FN_IP4_26_25, FN_VI0_R2_B, FN_SEL_VI0_D), /* see sel_vi0 */ 858 PINMUX_IPSR_DATA(IP4_26_25, DU0_DB2), 859 PINMUX_IPSR_DATA(IP4_26_25, LCDOUT18), 860 861 PINMUX_IPSR_MSEL(IP4_28_27, VI0_R3_B, SEL_VI0_B), 862 PINMUX_IPSR_DATA(IP4_28_27, DU0_DB3), 863 PINMUX_IPSR_DATA(IP4_28_27, LCDOUT19), 864 865 PINMUX_DATA(VI0_R4_B_MARK, FN_IP4_30_29, FN_VI0_R4_B, FN_SEL_VI0_B), /* see sel_vi0 */ 866 PINMUX_DATA(VI0_R4_D_MARK, FN_IP4_30_29, FN_VI0_R4_B, FN_SEL_VI0_D), /* see sel_vi0 */ 867 PINMUX_IPSR_DATA(IP4_30_29, DU0_DB4), 868 PINMUX_IPSR_DATA(IP4_30_29, LCDOUT20), 869 870 /* IPSR5 */ 871 PINMUX_DATA(VI0_R5_B_MARK, FN_IP5_1_0, FN_VI0_R5_B, FN_SEL_VI0_B), /* see sel_vi0 */ 872 PINMUX_DATA(VI0_R5_D_MARK, FN_IP5_1_0, FN_VI0_R5_B, FN_SEL_VI0_D), /* see sel_vi0 */ 873 PINMUX_IPSR_DATA(IP5_1_0, DU0_DB5), 874 PINMUX_IPSR_DATA(IP5_1_0, LCDOUT21), 875 876 PINMUX_IPSR_MSEL(IP5_3_2, VI1_DATA10_B, SEL_VI1_B), 877 PINMUX_IPSR_DATA(IP5_3_2, DU0_DB6), 878 PINMUX_IPSR_DATA(IP5_3_2, LCDOUT22), 879 880 PINMUX_IPSR_MSEL(IP5_5_4, VI1_DATA11_B, SEL_VI1_B), 881 PINMUX_IPSR_DATA(IP5_5_4, DU0_DB7), 882 PINMUX_IPSR_DATA(IP5_5_4, LCDOUT23), 883 884 PINMUX_IPSR_DATA(IP5_6, DU0_DOTCLKIN), 885 PINMUX_IPSR_DATA(IP5_6, QSTVA_QVS), 886 887 PINMUX_IPSR_DATA(IP5_7, DU0_DOTCLKO_UT0), 888 PINMUX_IPSR_DATA(IP5_7, QCLK), 889 890 PINMUX_IPSR_DATA(IP5_9_8, DU0_DOTCLKO_UT1), 891 PINMUX_IPSR_DATA(IP5_9_8, QSTVB_QVE), 892 PINMUX_IPSR_DATA(IP5_9_8, AUDIO_CLKOUT_A), 893 PINMUX_IPSR_MSEL(IP5_9_8, REMOCON_C, SEL_REMOCON_C), 894 895 PINMUX_IPSR_MSEL(IP5_11_10, SSI_WS2_B, SEL_SSI2_B), 896 PINMUX_IPSR_DATA(IP5_11_10, DU0_EXHSYNC_DU0_HSYNC), 897 PINMUX_IPSR_DATA(IP5_11_10, QSTH_QHS), 898 899 PINMUX_IPSR_DATA(IP5_12, DU0_EXVSYNC_DU0_VSYNC), 900 PINMUX_IPSR_DATA(IP5_12, QSTB_QHE), 901 902 PINMUX_IPSR_DATA(IP5_14_13, DU0_EXODDF_DU0_ODDF_DISP_CDE), 903 PINMUX_IPSR_DATA(IP5_14_13, QCPV_QDE), 904 PINMUX_IPSR_MSEL(IP5_14_13, FMCLK_D, SEL_FM_D), 905 906 PINMUX_IPSR_MSEL(IP5_17_15, SSI_SCK1_A, SEL_SSI1_A), 907 PINMUX_IPSR_DATA(IP5_17_15, DU0_DISP), 908 PINMUX_IPSR_DATA(IP5_17_15, QPOLA), 909 PINMUX_IPSR_DATA(IP5_17_15, AUDCK), 910 PINMUX_IPSR_DATA(IP5_17_15, ARM_TRACECLK), 911 PINMUX_IPSR_DATA(IP5_17_15, BPFCLK_D), 912 913 PINMUX_IPSR_MSEL(IP5_20_18, SSI_WS1_A, SEL_SSI1_A), 914 PINMUX_IPSR_DATA(IP5_20_18, DU0_CDE), 915 PINMUX_IPSR_DATA(IP5_20_18, QPOLB), 916 PINMUX_IPSR_DATA(IP5_20_18, AUDSYNC), 917 PINMUX_IPSR_DATA(IP5_20_18, ARM_TRACECTL), 918 PINMUX_IPSR_MSEL(IP5_20_18, FMIN_D, SEL_FM_D), 919 920 PINMUX_IPSR_MSEL(IP5_22_21, SD1_CD_B, SEL_SD1_B), 921 PINMUX_IPSR_DATA(IP5_22_21, SSI_SCK78), 922 PINMUX_IPSR_MSEL(IP5_22_21, HSPI_RX0_B, SEL_HSPI0_B), 923 PINMUX_IPSR_DATA(IP5_22_21, TX1_B), 924 925 PINMUX_IPSR_MSEL(IP5_25_23, SD1_WP_B, SEL_SD1_B), 926 PINMUX_IPSR_DATA(IP5_25_23, SSI_WS78), 927 PINMUX_IPSR_MSEL(IP5_25_23, HSPI_CLK0_B, SEL_HSPI0_B), 928 PINMUX_IPSR_MSEL(IP5_25_23, RX1_B, SEL_SCIF1_B), 929 PINMUX_IPSR_MSEL(IP5_25_23, CAN_CLK_D, SEL_CANCLK_D), 930 931 PINMUX_IPSR_DATA(IP5_28_26, SSI_SDATA8), 932 PINMUX_IPSR_MSEL(IP5_28_26, SSI_SCK2_A, SEL_SSI2_A), 933 PINMUX_IPSR_MSEL(IP5_28_26, HSPI_CS0_B, SEL_HSPI0_B), 934 PINMUX_IPSR_DATA(IP5_28_26, TX2_A), 935 PINMUX_IPSR_DATA(IP5_28_26, CAN0_TX_B), 936 937 PINMUX_IPSR_DATA(IP5_30_29, SSI_SDATA7), 938 PINMUX_IPSR_DATA(IP5_30_29, HSPI_TX0_B), 939 PINMUX_IPSR_MSEL(IP5_30_29, RX2_A, SEL_SCIF2_A), 940 PINMUX_IPSR_MSEL(IP5_30_29, CAN0_RX_B, SEL_CAN0_B), 941 942 /* IPSR6 */ 943 PINMUX_IPSR_DATA(IP6_1_0, SSI_SCK6), 944 PINMUX_IPSR_MSEL(IP6_1_0, HSPI_RX2_A, SEL_HSPI2_A), 945 PINMUX_IPSR_MSEL(IP6_1_0, FMCLK_B, SEL_FM_B), 946 PINMUX_IPSR_DATA(IP6_1_0, CAN1_TX_B), 947 948 PINMUX_IPSR_DATA(IP6_4_2, SSI_WS6), 949 PINMUX_IPSR_MSEL(IP6_4_2, HSPI_CLK2_A, SEL_HSPI2_A), 950 PINMUX_IPSR_DATA(IP6_4_2, BPFCLK_B), 951 PINMUX_IPSR_MSEL(IP6_4_2, CAN1_RX_B, SEL_CAN1_B), 952 953 PINMUX_IPSR_DATA(IP6_6_5, SSI_SDATA6), 954 PINMUX_IPSR_DATA(IP6_6_5, HSPI_TX2_A), 955 PINMUX_IPSR_MSEL(IP6_6_5, FMIN_B, SEL_FM_B), 956 957 PINMUX_IPSR_DATA(IP6_7, SSI_SCK5), 958 PINMUX_IPSR_MSEL(IP6_7, RX4_C, SEL_SCIF4_C), 959 960 PINMUX_IPSR_DATA(IP6_8, SSI_WS5), 961 PINMUX_IPSR_DATA(IP6_8, TX4_C), 962 963 PINMUX_IPSR_DATA(IP6_9, SSI_SDATA5), 964 PINMUX_IPSR_MSEL(IP6_9, RX0_D, SEL_SCIF0_D), 965 966 PINMUX_IPSR_DATA(IP6_10, SSI_WS34), 967 PINMUX_IPSR_DATA(IP6_10, ARM_TRACEDATA_8), 968 969 PINMUX_IPSR_DATA(IP6_12_11, SSI_SDATA4), 970 PINMUX_IPSR_MSEL(IP6_12_11, SSI_WS2_A, SEL_SSI2_A), 971 PINMUX_IPSR_DATA(IP6_12_11, ARM_TRACEDATA_9), 972 973 PINMUX_IPSR_DATA(IP6_13, SSI_SDATA3), 974 PINMUX_IPSR_DATA(IP6_13, ARM_TRACEDATA_10), 975 976 PINMUX_IPSR_DATA(IP6_15_14, SSI_SCK012), 977 PINMUX_IPSR_DATA(IP6_15_14, ARM_TRACEDATA_11), 978 PINMUX_IPSR_DATA(IP6_15_14, TX0_D), 979 980 PINMUX_IPSR_DATA(IP6_16, SSI_WS012), 981 PINMUX_IPSR_DATA(IP6_16, ARM_TRACEDATA_12), 982 983 PINMUX_IPSR_DATA(IP6_18_17, SSI_SDATA2), 984 PINMUX_IPSR_MSEL(IP6_18_17, HSPI_CS2_A, SEL_HSPI2_A), 985 PINMUX_IPSR_DATA(IP6_18_17, ARM_TRACEDATA_13), 986 PINMUX_IPSR_MSEL(IP6_18_17, SDA1_A, SEL_I2C1_A), 987 988 PINMUX_IPSR_DATA(IP6_20_19, SSI_SDATA1), 989 PINMUX_IPSR_DATA(IP6_20_19, ARM_TRACEDATA_14), 990 PINMUX_IPSR_MSEL(IP6_20_19, SCL1_A, SEL_I2C1_A), 991 PINMUX_IPSR_MSEL(IP6_20_19, SCK2_A, SEL_SCIF2_A), 992 993 PINMUX_IPSR_DATA(IP6_21, SSI_SDATA0), 994 PINMUX_IPSR_DATA(IP6_21, ARM_TRACEDATA_15), 995 996 PINMUX_IPSR_DATA(IP6_23_22, SD0_CLK), 997 PINMUX_IPSR_DATA(IP6_23_22, SUB_TDO), 998 999 PINMUX_IPSR_DATA(IP6_25_24, SD0_CMD), 1000 PINMUX_IPSR_DATA(IP6_25_24, SUB_TRST), 1001 1002 PINMUX_IPSR_DATA(IP6_27_26, SD0_DAT0), 1003 PINMUX_IPSR_DATA(IP6_27_26, SUB_TMS), 1004 1005 PINMUX_IPSR_DATA(IP6_29_28, SD0_DAT1), 1006 PINMUX_IPSR_DATA(IP6_29_28, SUB_TCK), 1007 1008 PINMUX_IPSR_DATA(IP6_31_30, SD0_DAT2), 1009 PINMUX_IPSR_DATA(IP6_31_30, SUB_TDI), 1010 1011 /* IPSR7 */ 1012 PINMUX_IPSR_DATA(IP7_1_0, SD0_DAT3), 1013 PINMUX_IPSR_MSEL(IP7_1_0, IRQ1_B, SEL_IRQ1_B), 1014 1015 PINMUX_IPSR_DATA(IP7_3_2, SD0_CD), 1016 PINMUX_IPSR_DATA(IP7_3_2, TX5_A), 1017 1018 PINMUX_IPSR_DATA(IP7_5_4, SD0_WP), 1019 PINMUX_IPSR_MSEL(IP7_5_4, RX5_A, SEL_SCIF5_A), 1020 1021 PINMUX_IPSR_DATA(IP7_8_6, VI1_CLKENB), 1022 PINMUX_IPSR_MSEL(IP7_8_6, HSPI_CLK0_A, SEL_HSPI0_A), 1023 PINMUX_IPSR_DATA(IP7_8_6, HTX1_A), 1024 PINMUX_IPSR_MSEL(IP7_8_6, RTS1_C, SEL_SCIF1_C), 1025 1026 PINMUX_IPSR_DATA(IP7_11_9, VI1_FIELD), 1027 PINMUX_IPSR_MSEL(IP7_11_9, HSPI_CS0_A, SEL_HSPI0_A), 1028 PINMUX_IPSR_MSEL(IP7_11_9, HRX1_A, SEL_HSCIF1_A), 1029 PINMUX_IPSR_MSEL(IP7_11_9, SCK1_C, SEL_SCIF1_C), 1030 1031 PINMUX_IPSR_DATA(IP7_14_12, VI1_HSYNC), 1032 PINMUX_IPSR_MSEL(IP7_14_12, HSPI_RX0_A, SEL_HSPI0_A), 1033 PINMUX_IPSR_MSEL(IP7_14_12, HRTS1_A, SEL_HSCIF1_A), 1034 PINMUX_IPSR_MSEL(IP7_14_12, FMCLK_A, SEL_FM_A), 1035 PINMUX_IPSR_MSEL(IP7_14_12, RX1_C, SEL_SCIF1_C), 1036 1037 PINMUX_IPSR_DATA(IP7_17_15, VI1_VSYNC), 1038 PINMUX_IPSR_DATA(IP7_17_15, HSPI_TX0), 1039 PINMUX_IPSR_MSEL(IP7_17_15, HCTS1_A, SEL_HSCIF1_A), 1040 PINMUX_IPSR_DATA(IP7_17_15, BPFCLK_A), 1041 PINMUX_IPSR_DATA(IP7_17_15, TX1_C), 1042 1043 PINMUX_IPSR_DATA(IP7_20_18, TCLK0), 1044 PINMUX_IPSR_MSEL(IP7_20_18, HSCK1_A, SEL_HSCIF1_A), 1045 PINMUX_IPSR_MSEL(IP7_20_18, FMIN_A, SEL_FM_A), 1046 PINMUX_IPSR_MSEL(IP7_20_18, IRQ2_C, SEL_IRQ2_C), 1047 PINMUX_IPSR_MSEL(IP7_20_18, CTS1_C, SEL_SCIF1_C), 1048 PINMUX_IPSR_DATA(IP7_20_18, SPEEDIN), 1049 1050 PINMUX_IPSR_DATA(IP7_21, VI0_CLK), 1051 PINMUX_IPSR_MSEL(IP7_21, CAN_CLK_A, SEL_CANCLK_A), 1052 1053 PINMUX_IPSR_DATA(IP7_24_22, VI0_CLKENB), 1054 PINMUX_IPSR_MSEL(IP7_24_22, SD2_DAT2_B, SEL_SD2_B), 1055 PINMUX_IPSR_DATA(IP7_24_22, VI1_DATA0), 1056 PINMUX_IPSR_DATA(IP7_24_22, DU1_DG6), 1057 PINMUX_IPSR_MSEL(IP7_24_22, HSPI_RX1_A, SEL_HSPI1_A), 1058 PINMUX_IPSR_MSEL(IP7_24_22, RX4_B, SEL_SCIF4_B), 1059 1060 PINMUX_IPSR_DATA(IP7_28_25, VI0_FIELD), 1061 PINMUX_IPSR_MSEL(IP7_28_25, SD2_DAT3_B, SEL_SD2_B), 1062 PINMUX_DATA(VI0_R3_C_MARK, FN_IP7_28_25, FN_VI0_R3_C, FN_SEL_VI0_C), /* see sel_vi0 */ 1063 PINMUX_DATA(VI0_R3_D_MARK, FN_IP7_28_25, FN_VI0_R3_C, FN_SEL_VI0_D), /* see sel_vi0 */ 1064 PINMUX_IPSR_DATA(IP7_28_25, VI1_DATA1), 1065 PINMUX_IPSR_DATA(IP7_28_25, DU1_DG7), 1066 PINMUX_IPSR_MSEL(IP7_28_25, HSPI_CLK1_A, SEL_HSPI1_A), 1067 PINMUX_IPSR_DATA(IP7_28_25, TX4_B), 1068 1069 PINMUX_IPSR_DATA(IP7_31_29, VI0_HSYNC), 1070 PINMUX_IPSR_MSEL(IP7_31_29, SD2_CD_B, SEL_SD2_B), 1071 PINMUX_IPSR_DATA(IP7_31_29, VI1_DATA2), 1072 PINMUX_IPSR_DATA(IP7_31_29, DU1_DR2), 1073 PINMUX_IPSR_MSEL(IP7_31_29, HSPI_CS1_A, SEL_HSPI1_A), 1074 PINMUX_IPSR_MSEL(IP7_31_29, RX3_B, SEL_SCIF3_B), 1075 1076 /* IPSR8 */ 1077 PINMUX_IPSR_DATA(IP8_2_0, VI0_VSYNC), 1078 PINMUX_IPSR_MSEL(IP8_2_0, SD2_WP_B, SEL_SD2_B), 1079 PINMUX_IPSR_DATA(IP8_2_0, VI1_DATA3), 1080 PINMUX_IPSR_DATA(IP8_2_0, DU1_DR3), 1081 PINMUX_IPSR_DATA(IP8_2_0, HSPI_TX1_A), 1082 PINMUX_IPSR_DATA(IP8_2_0, TX3_B), 1083 1084 PINMUX_IPSR_DATA(IP8_5_3, VI0_DATA0_VI0_B0), 1085 PINMUX_IPSR_DATA(IP8_5_3, DU1_DG2), 1086 PINMUX_IPSR_MSEL(IP8_5_3, IRQ2_B, SEL_IRQ2_B), 1087 PINMUX_IPSR_MSEL(IP8_5_3, RX3_D, SEL_SCIF3_D), 1088 1089 PINMUX_IPSR_DATA(IP8_8_6, VI0_DATA1_VI0_B1), 1090 PINMUX_IPSR_DATA(IP8_8_6, DU1_DG3), 1091 PINMUX_IPSR_MSEL(IP8_8_6, IRQ3_B, SEL_IRQ3_B), 1092 PINMUX_IPSR_DATA(IP8_8_6, TX3_D), 1093 1094 PINMUX_IPSR_DATA(IP8_10_9, VI0_DATA2_VI0_B2), 1095 PINMUX_IPSR_DATA(IP8_10_9, DU1_DG4), 1096 PINMUX_IPSR_MSEL(IP8_10_9, RX0_C, SEL_SCIF0_C), 1097 1098 PINMUX_IPSR_DATA(IP8_13_11, VI0_DATA3_VI0_B3), 1099 PINMUX_IPSR_DATA(IP8_13_11, DU1_DG5), 1100 PINMUX_IPSR_DATA(IP8_13_11, TX1_A), 1101 PINMUX_IPSR_DATA(IP8_13_11, TX0_C), 1102 1103 PINMUX_IPSR_DATA(IP8_15_14, VI0_DATA4_VI0_B4), 1104 PINMUX_IPSR_DATA(IP8_15_14, DU1_DB2), 1105 PINMUX_IPSR_MSEL(IP8_15_14, RX1_A, SEL_SCIF1_A), 1106 1107 PINMUX_IPSR_DATA(IP8_18_16, VI0_DATA5_VI0_B5), 1108 PINMUX_IPSR_DATA(IP8_18_16, DU1_DB3), 1109 PINMUX_IPSR_MSEL(IP8_18_16, SCK1_A, SEL_SCIF1_A), 1110 PINMUX_IPSR_DATA(IP8_18_16, PWM4), 1111 PINMUX_IPSR_MSEL(IP8_18_16, HSCK1_B, SEL_HSCIF1_B), 1112 1113 PINMUX_IPSR_DATA(IP8_21_19, VI0_DATA6_VI0_G0), 1114 PINMUX_IPSR_DATA(IP8_21_19, DU1_DB4), 1115 PINMUX_IPSR_MSEL(IP8_21_19, CTS1_A, SEL_SCIF1_A), 1116 PINMUX_IPSR_DATA(IP8_21_19, PWM5), 1117 1118 PINMUX_IPSR_DATA(IP8_23_22, VI0_DATA7_VI0_G1), 1119 PINMUX_IPSR_DATA(IP8_23_22, DU1_DB5), 1120 PINMUX_IPSR_MSEL(IP8_23_22, RTS1_A, SEL_SCIF1_A), 1121 1122 PINMUX_IPSR_DATA(IP8_26_24, VI0_G2), 1123 PINMUX_IPSR_DATA(IP8_26_24, SD2_CLK_B), 1124 PINMUX_IPSR_DATA(IP8_26_24, VI1_DATA4), 1125 PINMUX_IPSR_DATA(IP8_26_24, DU1_DR4), 1126 PINMUX_IPSR_DATA(IP8_26_24, HTX1_B), 1127 1128 PINMUX_IPSR_DATA(IP8_29_27, VI0_G3), 1129 PINMUX_IPSR_MSEL(IP8_29_27, SD2_CMD_B, SEL_SD2_B), 1130 PINMUX_IPSR_DATA(IP8_29_27, VI1_DATA5), 1131 PINMUX_IPSR_DATA(IP8_29_27, DU1_DR5), 1132 PINMUX_IPSR_MSEL(IP8_29_27, HRX1_B, SEL_HSCIF1_B), 1133 1134 /* IPSR9 */ 1135 PINMUX_IPSR_DATA(IP9_2_0, VI0_G4), 1136 PINMUX_IPSR_MSEL(IP9_2_0, SD2_DAT0_B, SEL_SD2_B), 1137 PINMUX_IPSR_DATA(IP9_2_0, VI1_DATA6), 1138 PINMUX_IPSR_DATA(IP9_2_0, DU1_DR6), 1139 PINMUX_IPSR_MSEL(IP9_2_0, HRTS1_B, SEL_HSCIF1_B), 1140 1141 PINMUX_IPSR_DATA(IP9_5_3, VI0_G5), 1142 PINMUX_IPSR_MSEL(IP9_5_3, SD2_DAT1_B, SEL_SD2_B), 1143 PINMUX_IPSR_DATA(IP9_5_3, VI1_DATA7), 1144 PINMUX_IPSR_DATA(IP9_5_3, DU1_DR7), 1145 PINMUX_IPSR_MSEL(IP9_5_3, HCTS1_B, SEL_HSCIF1_B), 1146 1147 PINMUX_DATA(VI0_R0_A_MARK, FN_IP9_8_6, FN_VI0_R0_A, FN_SEL_VI0_A), /* see sel_vi0 */ 1148 PINMUX_DATA(VI0_R0_C_MARK, FN_IP9_8_6, FN_VI0_R0_A, FN_SEL_VI0_C), /* see sel_vi0 */ 1149 PINMUX_IPSR_DATA(IP9_8_6, VI1_CLK), 1150 PINMUX_IPSR_DATA(IP9_8_6, ETH_REF_CLK), 1151 PINMUX_IPSR_DATA(IP9_8_6, DU1_DOTCLKIN), 1152 1153 PINMUX_DATA(VI0_R1_A_MARK, FN_IP9_11_9, FN_VI0_R1_A, FN_SEL_VI0_A), /* see sel_vi0 */ 1154 PINMUX_DATA(VI0_R1_C_MARK, FN_IP9_11_9, FN_VI0_R1_A, FN_SEL_VI0_C), /* see sel_vi0 */ 1155 PINMUX_IPSR_DATA(IP9_11_9, VI1_DATA8), 1156 PINMUX_IPSR_DATA(IP9_11_9, DU1_DB6), 1157 PINMUX_IPSR_DATA(IP9_11_9, ETH_TXD0), 1158 PINMUX_IPSR_DATA(IP9_11_9, PWM2), 1159 PINMUX_IPSR_DATA(IP9_11_9, TCLK1), 1160 1161 PINMUX_DATA(VI0_R2_A_MARK, FN_IP9_14_12, FN_VI0_R2_A, FN_SEL_VI0_A), /* see sel_vi0 */ 1162 PINMUX_DATA(VI0_R2_C_MARK, FN_IP9_14_12, FN_VI0_R2_A, FN_SEL_VI0_C), /* see sel_vi0 */ 1163 PINMUX_IPSR_DATA(IP9_14_12, VI1_DATA9), 1164 PINMUX_IPSR_DATA(IP9_14_12, DU1_DB7), 1165 PINMUX_IPSR_DATA(IP9_14_12, ETH_TXD1), 1166 PINMUX_IPSR_DATA(IP9_14_12, PWM3), 1167 1168 PINMUX_IPSR_MSEL(IP9_17_15, VI0_R3_A, SEL_VI0_A), 1169 PINMUX_IPSR_DATA(IP9_17_15, ETH_CRS_DV), 1170 PINMUX_IPSR_DATA(IP9_17_15, IECLK), 1171 PINMUX_IPSR_MSEL(IP9_17_15, SCK2_C, SEL_SCIF2_C), 1172 1173 PINMUX_DATA(VI0_R4_A_MARK, FN_IP9_20_18, FN_VI0_R4_A, FN_SEL_VI0_A), /* see sel_vi0 */ 1174 PINMUX_DATA(VI0_R3_C_MARK, FN_IP9_20_18, FN_VI0_R4_A, FN_SEL_VI0_C), /* see sel_vi0 */ 1175 PINMUX_IPSR_DATA(IP9_20_18, ETH_TX_EN), 1176 PINMUX_IPSR_DATA(IP9_20_18, IETX), 1177 PINMUX_IPSR_DATA(IP9_20_18, TX2_C), 1178 1179 PINMUX_DATA(VI0_R5_A_MARK, FN_IP9_23_21, FN_VI0_R5_A, FN_SEL_VI0_A), /* see sel_vi0 */ 1180 PINMUX_DATA(VI0_R5_C_MARK, FN_IP9_23_21, FN_VI0_R5_A, FN_SEL_VI0_C), /* see sel_vi0 */ 1181 PINMUX_IPSR_DATA(IP9_23_21, ETH_RX_ER), 1182 PINMUX_IPSR_MSEL(IP9_23_21, FMCLK_C, SEL_FM_C), 1183 PINMUX_IPSR_DATA(IP9_23_21, IERX), 1184 PINMUX_IPSR_MSEL(IP9_23_21, RX2_C, SEL_SCIF2_C), 1185 1186 PINMUX_IPSR_MSEL(IP9_26_24, VI1_DATA10_A, SEL_VI1_A), 1187 PINMUX_IPSR_DATA(IP9_26_24, DU1_DOTCLKOUT), 1188 PINMUX_IPSR_DATA(IP9_26_24, ETH_RXD0), 1189 PINMUX_IPSR_DATA(IP9_26_24, BPFCLK_C), 1190 PINMUX_IPSR_DATA(IP9_26_24, TX2_D), 1191 PINMUX_IPSR_MSEL(IP9_26_24, SDA2_C, SEL_I2C2_C), 1192 1193 PINMUX_IPSR_MSEL(IP9_29_27, VI1_DATA11_A, SEL_VI1_A), 1194 PINMUX_IPSR_DATA(IP9_29_27, DU1_EXHSYNC_DU1_HSYNC), 1195 PINMUX_IPSR_DATA(IP9_29_27, ETH_RXD1), 1196 PINMUX_IPSR_MSEL(IP9_29_27, FMIN_C, SEL_FM_C), 1197 PINMUX_IPSR_MSEL(IP9_29_27, RX2_D, SEL_SCIF2_D), 1198 PINMUX_IPSR_MSEL(IP9_29_27, SCL2_C, SEL_I2C2_C), 1199 1200 /* IPSR10 */ 1201 PINMUX_IPSR_DATA(IP10_2_0, SD2_CLK_A), 1202 PINMUX_IPSR_DATA(IP10_2_0, DU1_EXVSYNC_DU1_VSYNC), 1203 PINMUX_IPSR_DATA(IP10_2_0, ATARD1), 1204 PINMUX_IPSR_DATA(IP10_2_0, ETH_MDC), 1205 PINMUX_IPSR_MSEL(IP10_2_0, SDA1_B, SEL_I2C1_B), 1206 1207 PINMUX_IPSR_MSEL(IP10_5_3, SD2_CMD_A, SEL_SD2_A), 1208 PINMUX_IPSR_DATA(IP10_5_3, DU1_EXODDF_DU1_ODDF_DISP_CDE), 1209 PINMUX_IPSR_DATA(IP10_5_3, ATAWR1), 1210 PINMUX_IPSR_DATA(IP10_5_3, ETH_MDIO), 1211 PINMUX_IPSR_MSEL(IP10_5_3, SCL1_B, SEL_I2C1_B), 1212 1213 PINMUX_IPSR_MSEL(IP10_8_6, SD2_DAT0_A, SEL_SD2_A), 1214 PINMUX_IPSR_DATA(IP10_8_6, DU1_DISP), 1215 PINMUX_IPSR_DATA(IP10_8_6, ATACS01), 1216 PINMUX_IPSR_MSEL(IP10_8_6, DREQ1_B, SEL_DREQ1_B), 1217 PINMUX_IPSR_DATA(IP10_8_6, ETH_LINK), 1218 PINMUX_IPSR_MSEL(IP10_8_6, CAN1_RX_A, SEL_CAN1_A), 1219 1220 PINMUX_IPSR_MSEL(IP10_12_9, SD2_DAT1_A, SEL_SD2_A), 1221 PINMUX_IPSR_DATA(IP10_12_9, DU1_CDE), 1222 PINMUX_IPSR_DATA(IP10_12_9, ATACS11), 1223 PINMUX_IPSR_DATA(IP10_12_9, DACK1_B), 1224 PINMUX_IPSR_DATA(IP10_12_9, ETH_MAGIC), 1225 PINMUX_IPSR_DATA(IP10_12_9, CAN1_TX_A), 1226 PINMUX_IPSR_DATA(IP10_12_9, PWM6), 1227 1228 PINMUX_IPSR_MSEL(IP10_15_13, SD2_DAT2_A, SEL_SD2_A), 1229 PINMUX_IPSR_DATA(IP10_15_13, VI1_DATA12), 1230 PINMUX_IPSR_MSEL(IP10_15_13, DREQ2_B, SEL_DREQ2_B), 1231 PINMUX_IPSR_DATA(IP10_15_13, ATADIR1), 1232 PINMUX_IPSR_MSEL(IP10_15_13, HSPI_CLK2_B, SEL_HSPI2_B), 1233 PINMUX_IPSR_MSEL(IP10_15_13, GPSCLK_B, SEL_GPS_B), 1234 1235 PINMUX_IPSR_MSEL(IP10_18_16, SD2_DAT3_A, SEL_SD2_A), 1236 PINMUX_IPSR_DATA(IP10_18_16, VI1_DATA13), 1237 PINMUX_IPSR_DATA(IP10_18_16, DACK2_B), 1238 PINMUX_IPSR_DATA(IP10_18_16, ATAG1), 1239 PINMUX_IPSR_MSEL(IP10_18_16, HSPI_CS2_B, SEL_HSPI2_B), 1240 PINMUX_IPSR_MSEL(IP10_18_16, GPSIN_B, SEL_GPS_B), 1241 1242 PINMUX_IPSR_MSEL(IP10_21_19, SD2_CD_A, SEL_SD2_A), 1243 PINMUX_IPSR_DATA(IP10_21_19, VI1_DATA14), 1244 PINMUX_IPSR_MSEL(IP10_21_19, EX_WAIT1_B, SEL_WAIT1_B), 1245 PINMUX_IPSR_MSEL(IP10_21_19, DREQ0_B, SEL_DREQ0_B), 1246 PINMUX_IPSR_MSEL(IP10_21_19, HSPI_RX2_B, SEL_HSPI2_B), 1247 PINMUX_IPSR_MSEL(IP10_21_19, REMOCON_A, SEL_REMOCON_A), 1248 1249 PINMUX_IPSR_MSEL(IP10_24_22, SD2_WP_A, SEL_SD2_A), 1250 PINMUX_IPSR_DATA(IP10_24_22, VI1_DATA15), 1251 PINMUX_IPSR_MSEL(IP10_24_22, EX_WAIT2_B, SEL_WAIT2_B), 1252 PINMUX_IPSR_DATA(IP10_24_22, DACK0_B), 1253 PINMUX_IPSR_DATA(IP10_24_22, HSPI_TX2_B), 1254 PINMUX_IPSR_MSEL(IP10_24_22, CAN_CLK_C, SEL_CANCLK_C), 1255 }; 1256 1257 /* Pin numbers for pins without a corresponding GPIO port number are computed 1258 * from the row and column numbers with a 1000 offset to avoid collisions with 1259 * GPIO port numbers. 1260 */ 1261 #define PIN_NUMBER(row, col) (1000+((row)-1)*25+(col)-1) 1262 1263 static const struct sh_pfc_pin pinmux_pins[] = { 1264 PINMUX_GPIO_GP_ALL(), 1265 1266 /* Pins not associated with a GPIO port */ 1267 SH_PFC_PIN_NAMED(3, 20, C20), 1268 SH_PFC_PIN_NAMED(20, 1, T1), 1269 SH_PFC_PIN_NAMED(25, 2, Y2), 1270 }; 1271 1272 /* - macro */ 1273 #define SH_PFC_PINS(name, args...) \ 1274 static const unsigned int name ##_pins[] = { args } 1275 #define SH_PFC_MUX1(name, arg1) \ 1276 static const unsigned int name ##_mux[] = { arg1##_MARK } 1277 #define SH_PFC_MUX2(name, arg1, arg2) \ 1278 static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, } 1279 #define SH_PFC_MUX3(name, arg1, arg2, arg3) \ 1280 static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \ 1281 arg3##_MARK } 1282 #define SH_PFC_MUX4(name, arg1, arg2, arg3, arg4) \ 1283 static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \ 1284 arg3##_MARK, arg4##_MARK } 1285 #define SH_PFC_MUX8(name, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8) \ 1286 static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \ 1287 arg3##_MARK, arg4##_MARK, \ 1288 arg5##_MARK, arg6##_MARK, \ 1289 arg7##_MARK, arg8##_MARK, } 1290 1291 /* - AUDIO macro -------------------------------------------------------------*/ 1292 #define AUDIO_PFC_PIN(name, pin) SH_PFC_PINS(name, pin) 1293 #define AUDIO_PFC_DAT(name, pin) SH_PFC_MUX1(name, pin) 1294 1295 /* - AUDIO clock -------------------------------------------------------------*/ 1296 AUDIO_PFC_PIN(audio_clk_a, RCAR_GP_PIN(2, 22)); 1297 AUDIO_PFC_DAT(audio_clk_a, AUDIO_CLKA); 1298 AUDIO_PFC_PIN(audio_clk_b, RCAR_GP_PIN(2, 23)); 1299 AUDIO_PFC_DAT(audio_clk_b, AUDIO_CLKB); 1300 AUDIO_PFC_PIN(audio_clk_c, RCAR_GP_PIN(2, 7)); 1301 AUDIO_PFC_DAT(audio_clk_c, AUDIO_CLKC); 1302 AUDIO_PFC_PIN(audio_clkout_a, RCAR_GP_PIN(2, 16)); 1303 AUDIO_PFC_DAT(audio_clkout_a, AUDIO_CLKOUT_A); 1304 AUDIO_PFC_PIN(audio_clkout_b, RCAR_GP_PIN(1, 16)); 1305 AUDIO_PFC_DAT(audio_clkout_b, AUDIO_CLKOUT_B); 1306 1307 /* - CAN macro --------_----------------------------------------------------- */ 1308 #define CAN_PFC_PINS(name, args...) SH_PFC_PINS(name, args) 1309 #define CAN_PFC_DATA(name, tx, rx) SH_PFC_MUX2(name, tx, rx) 1310 #define CAN_PFC_CLK(name, clk) SH_PFC_MUX1(name, clk) 1311 1312 /* - CAN0 ------------------------------------------------------------------- */ 1313 CAN_PFC_PINS(can0_data_a, RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31)); 1314 CAN_PFC_DATA(can0_data_a, CAN0_TX_A, CAN0_RX_A); 1315 CAN_PFC_PINS(can0_data_b, RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27)); 1316 CAN_PFC_DATA(can0_data_b, CAN0_TX_B, CAN0_RX_B); 1317 1318 /* - CAN1 ------------------------------------------------------------------- */ 1319 CAN_PFC_PINS(can1_data_a, RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19)); 1320 CAN_PFC_DATA(can1_data_a, CAN1_TX_A, CAN1_RX_A); 1321 CAN_PFC_PINS(can1_data_b, RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 29)); 1322 CAN_PFC_DATA(can1_data_b, CAN1_TX_B, CAN1_RX_B); 1323 1324 /* - CAN_CLK --------------------------------------------------------------- */ 1325 CAN_PFC_PINS(can_clk_a, RCAR_GP_PIN(3, 24)); 1326 CAN_PFC_CLK(can_clk_a, CAN_CLK_A); 1327 CAN_PFC_PINS(can_clk_b, RCAR_GP_PIN(1, 16)); 1328 CAN_PFC_CLK(can_clk_b, CAN_CLK_B); 1329 CAN_PFC_PINS(can_clk_c, RCAR_GP_PIN(4, 24)); 1330 CAN_PFC_CLK(can_clk_c, CAN_CLK_C); 1331 CAN_PFC_PINS(can_clk_d, RCAR_GP_PIN(2, 25)); 1332 CAN_PFC_CLK(can_clk_d, CAN_CLK_D); 1333 1334 /* - Ether ------------------------------------------------------------------ */ 1335 SH_PFC_PINS(ether_rmii, RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), 1336 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 9), 1337 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 1338 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 14), 1339 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17)); 1340 static const unsigned int ether_rmii_mux[] = { 1341 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK, 1342 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK, 1343 ETH_MDIO_MARK, ETH_MDC_MARK, 1344 }; 1345 SH_PFC_PINS(ether_link, RCAR_GP_PIN(4, 19)); 1346 SH_PFC_MUX1(ether_link, ETH_LINK); 1347 SH_PFC_PINS(ether_magic, RCAR_GP_PIN(4, 20)); 1348 SH_PFC_MUX1(ether_magic, ETH_MAGIC); 1349 1350 /* - SCIF macro ------------------------------------------------------------- */ 1351 #define SCIF_PFC_PIN(name, args...) SH_PFC_PINS(name, args) 1352 #define SCIF_PFC_DAT(name, tx, rx) SH_PFC_MUX2(name, tx, rx) 1353 #define SCIF_PFC_CTR(name, cts, rts) SH_PFC_MUX2(name, cts, rts) 1354 #define SCIF_PFC_CLK(name, sck) SH_PFC_MUX1(name, sck) 1355 1356 /* - HSCIF0 ----------------------------------------------------------------- */ 1357 SCIF_PFC_PIN(hscif0_data_a, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18)); 1358 SCIF_PFC_DAT(hscif0_data_a, HTX0_A, HRX0_A); 1359 SCIF_PFC_PIN(hscif0_data_b, RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 30)); 1360 SCIF_PFC_DAT(hscif0_data_b, HTX0_B, HRX0_B); 1361 SCIF_PFC_PIN(hscif0_ctrl_a, RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21)); 1362 SCIF_PFC_CTR(hscif0_ctrl_a, HCTS0_A, HRTS0_A); 1363 SCIF_PFC_PIN(hscif0_ctrl_b, RCAR_GP_PIN(0, 31), RCAR_GP_PIN(0, 28)); 1364 SCIF_PFC_CTR(hscif0_ctrl_b, HCTS0_B, HRTS0_B); 1365 SCIF_PFC_PIN(hscif0_clk, RCAR_GP_PIN(1, 19)); 1366 SCIF_PFC_CLK(hscif0_clk, HSCK0); 1367 1368 /* - HSCIF1 ----------------------------------------------------------------- */ 1369 SCIF_PFC_PIN(hscif1_data_a, RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20)); 1370 SCIF_PFC_DAT(hscif1_data_a, HTX1_A, HRX1_A); 1371 SCIF_PFC_PIN(hscif1_data_b, RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6)); 1372 SCIF_PFC_DAT(hscif1_data_b, HTX1_B, HRX1_B); 1373 SCIF_PFC_PIN(hscif1_ctrl_a, RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21)); 1374 SCIF_PFC_CTR(hscif1_ctrl_a, HCTS1_A, HRTS1_A); 1375 SCIF_PFC_PIN(hscif1_ctrl_b, RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7)); 1376 SCIF_PFC_CTR(hscif1_ctrl_b, HCTS1_B, HRTS1_B); 1377 SCIF_PFC_PIN(hscif1_clk_a, RCAR_GP_PIN(3, 23)); 1378 SCIF_PFC_CLK(hscif1_clk_a, HSCK1_A); 1379 SCIF_PFC_PIN(hscif1_clk_b, RCAR_GP_PIN(4, 2)); 1380 SCIF_PFC_CLK(hscif1_clk_b, HSCK1_B); 1381 1382 /* - HSPI macro --------------------------------------------------------------*/ 1383 #define HSPI_PFC_PIN(name, args...) SH_PFC_PINS(name, args) 1384 #define HSPI_PFC_DAT(name, clk, cs, rx, tx) SH_PFC_MUX4(name, clk, cs, rx, tx) 1385 1386 /* - HSPI0 -------------------------------------------------------------------*/ 1387 HSPI_PFC_PIN(hspi0_a, RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), 1388 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22)); 1389 HSPI_PFC_DAT(hspi0_a, HSPI_CLK0_A, HSPI_CS0_A, 1390 HSPI_RX0_A, HSPI_TX0); 1391 1392 HSPI_PFC_PIN(hspi0_b, RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26), 1393 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 27)); 1394 HSPI_PFC_DAT(hspi0_b, HSPI_CLK0_B, HSPI_CS0_B, 1395 HSPI_RX0_B, HSPI_TX0_B); 1396 1397 /* - HSPI1 -------------------------------------------------------------------*/ 1398 HSPI_PFC_PIN(hspi1_a, RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), 1399 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 28)); 1400 HSPI_PFC_DAT(hspi1_a, HSPI_CLK1_A, HSPI_CS1_A, 1401 HSPI_RX1_A, HSPI_TX1_A); 1402 1403 HSPI_PFC_PIN(hspi1_b, RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 26), 1404 PIN_NUMBER(20, 1), PIN_NUMBER(25, 2)); 1405 HSPI_PFC_DAT(hspi1_b, HSPI_CLK1_B, HSPI_CS1_B, 1406 HSPI_RX1_B, HSPI_TX1_B); 1407 1408 /* - HSPI2 -------------------------------------------------------------------*/ 1409 HSPI_PFC_PIN(hspi2_a, RCAR_GP_PIN(2, 29), RCAR_GP_PIN(3, 8), 1410 RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 30)); 1411 HSPI_PFC_DAT(hspi2_a, HSPI_CLK2_A, HSPI_CS2_A, 1412 HSPI_RX2_A, HSPI_TX2_A); 1413 1414 HSPI_PFC_PIN(hspi2_b, RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22), 1415 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24)); 1416 HSPI_PFC_DAT(hspi2_b, HSPI_CLK2_B, HSPI_CS2_B, 1417 HSPI_RX2_B, HSPI_TX2_B); 1418 1419 /* - I2C macro ------------------------------------------------------------- */ 1420 #define I2C_PFC_PIN(name, args...) SH_PFC_PINS(name, args) 1421 #define I2C_PFC_MUX(name, sda, scl) SH_PFC_MUX2(name, sda, scl) 1422 1423 /* - I2C1 ------------------------------------------------------------------ */ 1424 I2C_PFC_PIN(i2c1_a, RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9)); 1425 I2C_PFC_MUX(i2c1_a, SDA1_A, SCL1_A); 1426 I2C_PFC_PIN(i2c1_b, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18)); 1427 I2C_PFC_MUX(i2c1_b, SDA1_B, SCL1_B); 1428 1429 /* - I2C2 ------------------------------------------------------------------ */ 1430 I2C_PFC_PIN(i2c2_a, PIN_NUMBER(3, 20), RCAR_GP_PIN(1, 3)); 1431 I2C_PFC_MUX(i2c2_a, SDA2_A, SCL2_A); 1432 I2C_PFC_PIN(i2c2_b, RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4)); 1433 I2C_PFC_MUX(i2c2_b, SDA2_B, SCL2_B); 1434 I2C_PFC_PIN(i2c2_c, RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16)); 1435 I2C_PFC_MUX(i2c2_c, SDA2_C, SCL2_C); 1436 1437 /* - I2C3 ------------------------------------------------------------------ */ 1438 I2C_PFC_PIN(i2c3_a, RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15)); 1439 I2C_PFC_MUX(i2c3_a, SDA3_A, SCL3_A); 1440 I2C_PFC_PIN(i2c3_b, RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 19)); 1441 I2C_PFC_MUX(i2c3_b, SDA3_B, SCL3_B); 1442 I2C_PFC_PIN(i2c3_c, RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23)); 1443 I2C_PFC_MUX(i2c3_c, SDA3_C, SCL3_C); 1444 1445 /* - MMC macro -------------------------------------------------------------- */ 1446 #define MMC_PFC_PINS(name, args...) SH_PFC_PINS(name, args) 1447 #define MMC_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd) 1448 #define MMC_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0) 1449 #define MMC_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3) 1450 #define MMC_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7) \ 1451 SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7) 1452 1453 /* - MMC -------------------------------------------------------------------- */ 1454 MMC_PFC_PINS(mmc_ctrl, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6)); 1455 MMC_PFC_CTRL(mmc_ctrl, MMC_CLK, MMC_CMD); 1456 MMC_PFC_PINS(mmc_data1, RCAR_GP_PIN(1, 7)); 1457 MMC_PFC_DAT1(mmc_data1, MMC_D0); 1458 MMC_PFC_PINS(mmc_data4, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), 1459 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6)); 1460 MMC_PFC_DAT4(mmc_data4, MMC_D0, MMC_D1, 1461 MMC_D2, MMC_D3); 1462 MMC_PFC_PINS(mmc_data8, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), 1463 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), 1464 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0), 1465 RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31)); 1466 MMC_PFC_DAT8(mmc_data8, MMC_D0, MMC_D1, 1467 MMC_D2, MMC_D3, 1468 MMC_D4, MMC_D5, 1469 MMC_D6, MMC_D7); 1470 1471 /* - SCIF CLOCK ------------------------------------------------------------- */ 1472 SCIF_PFC_PIN(scif_clk, RCAR_GP_PIN(1, 16)); 1473 SCIF_PFC_CLK(scif_clk, SCIF_CLK); 1474 1475 /* - SCIF0 ------------------------------------------------------------------ */ 1476 SCIF_PFC_PIN(scif0_data_a, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18)); 1477 SCIF_PFC_DAT(scif0_data_a, TX0_A, RX0_A); 1478 SCIF_PFC_PIN(scif0_data_b, RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2)); 1479 SCIF_PFC_DAT(scif0_data_b, TX0_B, RX0_B); 1480 SCIF_PFC_PIN(scif0_data_c, RCAR_GP_PIN(4, 0), RCAR_GP_PIN(3, 31)); 1481 SCIF_PFC_DAT(scif0_data_c, TX0_C, RX0_C); 1482 SCIF_PFC_PIN(scif0_data_d, RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 1)); 1483 SCIF_PFC_DAT(scif0_data_d, TX0_D, RX0_D); 1484 SCIF_PFC_PIN(scif0_ctrl, RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21)); 1485 SCIF_PFC_CTR(scif0_ctrl, CTS0, RTS0); 1486 SCIF_PFC_PIN(scif0_clk, RCAR_GP_PIN(1, 19)); 1487 SCIF_PFC_CLK(scif0_clk, SCK0); 1488 1489 /* - SCIF1 ------------------------------------------------------------------ */ 1490 SCIF_PFC_PIN(scif1_data_a, RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1)); 1491 SCIF_PFC_DAT(scif1_data_a, TX1_A, RX1_A); 1492 SCIF_PFC_PIN(scif1_data_b, RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25)); 1493 SCIF_PFC_DAT(scif1_data_b, TX1_B, RX1_B); 1494 SCIF_PFC_PIN(scif1_data_c, RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21)); 1495 SCIF_PFC_DAT(scif1_data_c, TX1_C, RX1_C); 1496 SCIF_PFC_PIN(scif1_data_d, RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31)); 1497 SCIF_PFC_DAT(scif1_data_d, TX1_D, RX1_D); 1498 SCIF_PFC_PIN(scif1_ctrl_a, RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4)); 1499 SCIF_PFC_CTR(scif1_ctrl_a, CTS1_A, RTS1_A); 1500 SCIF_PFC_PIN(scif1_ctrl_c, RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 19)); 1501 SCIF_PFC_CTR(scif1_ctrl_c, CTS1_C, RTS1_C); 1502 SCIF_PFC_PIN(scif1_clk_a, RCAR_GP_PIN(4, 2)); 1503 SCIF_PFC_CLK(scif1_clk_a, SCK1_A); 1504 SCIF_PFC_PIN(scif1_clk_c, RCAR_GP_PIN(3, 20)); 1505 SCIF_PFC_CLK(scif1_clk_c, SCK1_C); 1506 1507 /* - SCIF2 ------------------------------------------------------------------ */ 1508 SCIF_PFC_PIN(scif2_data_a, RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27)); 1509 SCIF_PFC_DAT(scif2_data_a, TX2_A, RX2_A); 1510 SCIF_PFC_PIN(scif2_data_b, RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 28)); 1511 SCIF_PFC_DAT(scif2_data_b, TX2_B, RX2_B); 1512 SCIF_PFC_PIN(scif2_data_c, RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14)); 1513 SCIF_PFC_DAT(scif2_data_c, TX2_C, RX2_C); 1514 SCIF_PFC_PIN(scif2_data_d, RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16)); 1515 SCIF_PFC_DAT(scif2_data_d, TX2_D, RX2_D); 1516 SCIF_PFC_PIN(scif2_data_e, RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4)); 1517 SCIF_PFC_DAT(scif2_data_e, TX2_E, RX2_E); 1518 SCIF_PFC_PIN(scif2_clk_a, RCAR_GP_PIN(3, 9)); 1519 SCIF_PFC_CLK(scif2_clk_a, SCK2_A); 1520 SCIF_PFC_PIN(scif2_clk_b, PIN_NUMBER(3, 20)); 1521 SCIF_PFC_CLK(scif2_clk_b, SCK2_B); 1522 SCIF_PFC_PIN(scif2_clk_c, RCAR_GP_PIN(4, 12)); 1523 SCIF_PFC_CLK(scif2_clk_c, SCK2_C); 1524 1525 /* - SCIF3 ------------------------------------------------------------------ */ 1526 SCIF_PFC_PIN(scif3_data_a, RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9)); 1527 SCIF_PFC_DAT(scif3_data_a, TX3_A, RX3_A); 1528 SCIF_PFC_PIN(scif3_data_b, RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27)); 1529 SCIF_PFC_DAT(scif3_data_b, TX3_B, RX3_B); 1530 SCIF_PFC_PIN(scif3_data_c, RCAR_GP_PIN(1, 3), RCAR_GP_PIN(0, 31)); 1531 SCIF_PFC_DAT(scif3_data_c, TX3_C, RX3_C); 1532 SCIF_PFC_PIN(scif3_data_d, RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 29)); 1533 SCIF_PFC_DAT(scif3_data_d, TX3_D, RX3_D); 1534 1535 /* - SCIF4 ------------------------------------------------------------------ */ 1536 SCIF_PFC_PIN(scif4_data_a, RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4)); 1537 SCIF_PFC_DAT(scif4_data_a, TX4_A, RX4_A); 1538 SCIF_PFC_PIN(scif4_data_b, RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 25)); 1539 SCIF_PFC_DAT(scif4_data_b, TX4_B, RX4_B); 1540 SCIF_PFC_PIN(scif4_data_c, RCAR_GP_PIN(3, 0), RCAR_GP_PIN(2, 31)); 1541 SCIF_PFC_DAT(scif4_data_c, TX4_C, RX4_C); 1542 1543 /* - SCIF5 ------------------------------------------------------------------ */ 1544 SCIF_PFC_PIN(scif5_data_a, RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18)); 1545 SCIF_PFC_DAT(scif5_data_a, TX5_A, RX5_A); 1546 SCIF_PFC_PIN(scif5_data_b, RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14)); 1547 SCIF_PFC_DAT(scif5_data_b, TX5_B, RX5_B); 1548 1549 /* - SDHI macro ------------------------------------------------------------- */ 1550 #define SDHI_PFC_PINS(name, args...) SH_PFC_PINS(name, args) 1551 #define SDHI_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0) 1552 #define SDHI_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3) 1553 #define SDHI_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd) 1554 #define SDHI_PFC_CDPN(name, cd) SH_PFC_MUX1(name, cd) 1555 #define SDHI_PFC_WPPN(name, wp) SH_PFC_MUX1(name, wp) 1556 1557 /* - SDHI0 ------------------------------------------------------------------ */ 1558 SDHI_PFC_PINS(sdhi0_cd, RCAR_GP_PIN(3, 17)); 1559 SDHI_PFC_CDPN(sdhi0_cd, SD0_CD); 1560 SDHI_PFC_PINS(sdhi0_ctrl, RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12)); 1561 SDHI_PFC_CTRL(sdhi0_ctrl, SD0_CLK, SD0_CMD); 1562 SDHI_PFC_PINS(sdhi0_data1, RCAR_GP_PIN(3, 13)); 1563 SDHI_PFC_DAT1(sdhi0_data1, SD0_DAT0); 1564 SDHI_PFC_PINS(sdhi0_data4, RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), 1565 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16)); 1566 SDHI_PFC_DAT4(sdhi0_data4, SD0_DAT0, SD0_DAT1, 1567 SD0_DAT2, SD0_DAT3); 1568 SDHI_PFC_PINS(sdhi0_wp, RCAR_GP_PIN(3, 18)); 1569 SDHI_PFC_WPPN(sdhi0_wp, SD0_WP); 1570 1571 /* - SDHI1 ------------------------------------------------------------------ */ 1572 SDHI_PFC_PINS(sdhi1_cd_a, RCAR_GP_PIN(0, 30)); 1573 SDHI_PFC_CDPN(sdhi1_cd_a, SD1_CD_A); 1574 SDHI_PFC_PINS(sdhi1_cd_b, RCAR_GP_PIN(2, 24)); 1575 SDHI_PFC_CDPN(sdhi1_cd_b, SD1_CD_B); 1576 SDHI_PFC_PINS(sdhi1_ctrl_a, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6)); 1577 SDHI_PFC_CTRL(sdhi1_ctrl_a, SD1_CLK_A, SD1_CMD_A); 1578 SDHI_PFC_PINS(sdhi1_ctrl_b, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16)); 1579 SDHI_PFC_CTRL(sdhi1_ctrl_b, SD1_CLK_B, SD1_CMD_B); 1580 SDHI_PFC_PINS(sdhi1_data1_a, RCAR_GP_PIN(1, 7)); 1581 SDHI_PFC_DAT1(sdhi1_data1_a, SD1_DAT0_A); 1582 SDHI_PFC_PINS(sdhi1_data1_b, RCAR_GP_PIN(1, 18)); 1583 SDHI_PFC_DAT1(sdhi1_data1_b, SD1_DAT0_B); 1584 SDHI_PFC_PINS(sdhi1_data4_a, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), 1585 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6)); 1586 SDHI_PFC_DAT4(sdhi1_data4_a, SD1_DAT0_A, SD1_DAT1_A, 1587 SD1_DAT2_A, SD1_DAT3_A); 1588 SDHI_PFC_PINS(sdhi1_data4_b, RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), 1589 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21)); 1590 SDHI_PFC_DAT4(sdhi1_data4_b, SD1_DAT0_B, SD1_DAT1_B, 1591 SD1_DAT2_B, SD1_DAT3_B); 1592 SDHI_PFC_PINS(sdhi1_wp_a, RCAR_GP_PIN(0, 31)); 1593 SDHI_PFC_WPPN(sdhi1_wp_a, SD1_WP_A); 1594 SDHI_PFC_PINS(sdhi1_wp_b, RCAR_GP_PIN(2, 25)); 1595 SDHI_PFC_WPPN(sdhi1_wp_b, SD1_WP_B); 1596 1597 /* - SDH2 ------------------------------------------------------------------- */ 1598 SDHI_PFC_PINS(sdhi2_cd_a, RCAR_GP_PIN(4, 23)); 1599 SDHI_PFC_CDPN(sdhi2_cd_a, SD2_CD_A); 1600 SDHI_PFC_PINS(sdhi2_cd_b, RCAR_GP_PIN(3, 27)); 1601 SDHI_PFC_CDPN(sdhi2_cd_b, SD2_CD_B); 1602 SDHI_PFC_PINS(sdhi2_ctrl_a, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18)); 1603 SDHI_PFC_CTRL(sdhi2_ctrl_a, SD2_CLK_A, SD2_CMD_A); 1604 SDHI_PFC_PINS(sdhi2_ctrl_b, RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6)); 1605 SDHI_PFC_CTRL(sdhi2_ctrl_b, SD2_CLK_B, SD2_CMD_B); 1606 SDHI_PFC_PINS(sdhi2_data1_a, RCAR_GP_PIN(4, 19)); 1607 SDHI_PFC_DAT1(sdhi2_data1_a, SD2_DAT0_A); 1608 SDHI_PFC_PINS(sdhi2_data1_b, RCAR_GP_PIN(4, 7)); 1609 SDHI_PFC_DAT1(sdhi2_data1_b, SD2_DAT0_B); 1610 SDHI_PFC_PINS(sdhi2_data4_a, RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20), 1611 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22)); 1612 SDHI_PFC_DAT4(sdhi2_data4_a, SD2_DAT0_A, SD2_DAT1_A, 1613 SD2_DAT2_A, SD2_DAT3_A); 1614 SDHI_PFC_PINS(sdhi2_data4_b, RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), 1615 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26)); 1616 SDHI_PFC_DAT4(sdhi2_data4_b, SD2_DAT0_B, SD2_DAT1_B, 1617 SD2_DAT2_B, SD2_DAT3_B); 1618 SDHI_PFC_PINS(sdhi2_wp_a, RCAR_GP_PIN(4, 24)); 1619 SDHI_PFC_WPPN(sdhi2_wp_a, SD2_WP_A); 1620 SDHI_PFC_PINS(sdhi2_wp_b, RCAR_GP_PIN(3, 28)); 1621 SDHI_PFC_WPPN(sdhi2_wp_b, SD2_WP_B); 1622 1623 /* - SSI macro -------------------------------------------------------------- */ 1624 #define SSI_PFC_PINS(name, args...) SH_PFC_PINS(name, args) 1625 #define SSI_PFC_CTRL(name, sck, ws) SH_PFC_MUX2(name, sck, ws) 1626 #define SSI_PFC_DATA(name, d) SH_PFC_MUX1(name, d) 1627 1628 /* - SSI 0/1/2 -------------------------------------------------------------- */ 1629 SSI_PFC_PINS(ssi012_ctrl, RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7)); 1630 SSI_PFC_CTRL(ssi012_ctrl, SSI_SCK012, SSI_WS012); 1631 SSI_PFC_PINS(ssi0_data, RCAR_GP_PIN(3, 10)); 1632 SSI_PFC_DATA(ssi0_data, SSI_SDATA0); 1633 SSI_PFC_PINS(ssi1_a_ctrl, RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21)); 1634 SSI_PFC_CTRL(ssi1_a_ctrl, SSI_SCK1_A, SSI_WS1_A); 1635 SSI_PFC_PINS(ssi1_b_ctrl, PIN_NUMBER(3, 20), RCAR_GP_PIN(1, 3)); 1636 SSI_PFC_CTRL(ssi1_b_ctrl, SSI_SCK1_B, SSI_WS1_B); 1637 SSI_PFC_PINS(ssi1_data, RCAR_GP_PIN(3, 9)); 1638 SSI_PFC_DATA(ssi1_data, SSI_SDATA1); 1639 SSI_PFC_PINS(ssi2_a_ctrl, RCAR_GP_PIN(2, 26), RCAR_GP_PIN(3, 4)); 1640 SSI_PFC_CTRL(ssi2_a_ctrl, SSI_SCK2_A, SSI_WS2_A); 1641 SSI_PFC_PINS(ssi2_b_ctrl, RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 17)); 1642 SSI_PFC_CTRL(ssi2_b_ctrl, SSI_SCK2_B, SSI_WS2_B); 1643 SSI_PFC_PINS(ssi2_data, RCAR_GP_PIN(3, 8)); 1644 SSI_PFC_DATA(ssi2_data, SSI_SDATA2); 1645 1646 /* - SSI 3/4 ---------------------------------------------------------------- */ 1647 SSI_PFC_PINS(ssi34_ctrl, RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3)); 1648 SSI_PFC_CTRL(ssi34_ctrl, SSI_SCK34, SSI_WS34); 1649 SSI_PFC_PINS(ssi3_data, RCAR_GP_PIN(3, 5)); 1650 SSI_PFC_DATA(ssi3_data, SSI_SDATA3); 1651 SSI_PFC_PINS(ssi4_ctrl, RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23)); 1652 SSI_PFC_CTRL(ssi4_ctrl, SSI_SCK4, SSI_WS4); 1653 SSI_PFC_PINS(ssi4_data, RCAR_GP_PIN(3, 4)); 1654 SSI_PFC_DATA(ssi4_data, SSI_SDATA4); 1655 1656 /* - SSI 5 ------------------------------------------------------------------ */ 1657 SSI_PFC_PINS(ssi5_ctrl, RCAR_GP_PIN(2, 31), RCAR_GP_PIN(3, 0)); 1658 SSI_PFC_CTRL(ssi5_ctrl, SSI_SCK5, SSI_WS5); 1659 SSI_PFC_PINS(ssi5_data, RCAR_GP_PIN(3, 1)); 1660 SSI_PFC_DATA(ssi5_data, SSI_SDATA5); 1661 1662 /* - SSI 6 ------------------------------------------------------------------ */ 1663 SSI_PFC_PINS(ssi6_ctrl, RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 29)); 1664 SSI_PFC_CTRL(ssi6_ctrl, SSI_SCK6, SSI_WS6); 1665 SSI_PFC_PINS(ssi6_data, RCAR_GP_PIN(2, 30)); 1666 SSI_PFC_DATA(ssi6_data, SSI_SDATA6); 1667 1668 /* - SSI 7/8 --------------------------------------------------------------- */ 1669 SSI_PFC_PINS(ssi78_ctrl, RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25)); 1670 SSI_PFC_CTRL(ssi78_ctrl, SSI_SCK78, SSI_WS78); 1671 SSI_PFC_PINS(ssi7_data, RCAR_GP_PIN(2, 27)); 1672 SSI_PFC_DATA(ssi7_data, SSI_SDATA7); 1673 SSI_PFC_PINS(ssi8_data, RCAR_GP_PIN(2, 26)); 1674 SSI_PFC_DATA(ssi8_data, SSI_SDATA8); 1675 1676 /* - USB0 ------------------------------------------------------------------- */ 1677 SH_PFC_PINS(usb0, RCAR_GP_PIN(0, 1)); 1678 SH_PFC_MUX1(usb0, PENC0); 1679 SH_PFC_PINS(usb0_ovc, RCAR_GP_PIN(0, 3)); 1680 SH_PFC_MUX1(usb0_ovc, USB_OVC0); 1681 1682 /* - USB1 ------------------------------------------------------------------- */ 1683 SH_PFC_PINS(usb1, RCAR_GP_PIN(0, 2)); 1684 SH_PFC_MUX1(usb1, PENC1); 1685 SH_PFC_PINS(usb1_ovc, RCAR_GP_PIN(0, 4)); 1686 SH_PFC_MUX1(usb1_ovc, USB_OVC1); 1687 1688 /* - VIN macros ------------------------------------------------------------- */ 1689 #define VIN_PFC_PINS(name, args...) SH_PFC_PINS(name, args) 1690 #define VIN_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7) \ 1691 SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7) 1692 #define VIN_PFC_CLK(name, clk) SH_PFC_MUX1(name, clk) 1693 #define VIN_PFC_SYNC(name, hsync, vsync) SH_PFC_MUX2(name, hsync, vsync) 1694 1695 /* - VIN0 ------------------------------------------------------------------- */ 1696 VIN_PFC_PINS(vin0_data8, RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 30), 1697 RCAR_GP_PIN(3, 31), RCAR_GP_PIN(4, 0), 1698 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), 1699 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4)); 1700 VIN_PFC_DAT8(vin0_data8, VI0_DATA0_VI0_B0, VI0_DATA1_VI0_B1, 1701 VI0_DATA2_VI0_B2, VI0_DATA3_VI0_B3, 1702 VI0_DATA4_VI0_B4, VI0_DATA5_VI0_B5, 1703 VI0_DATA6_VI0_G0, VI0_DATA7_VI0_G1); 1704 VIN_PFC_PINS(vin0_clk, RCAR_GP_PIN(3, 24)); 1705 VIN_PFC_CLK(vin0_clk, VI0_CLK); 1706 VIN_PFC_PINS(vin0_sync, RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28)); 1707 VIN_PFC_SYNC(vin0_sync, VI0_HSYNC, VI0_VSYNC); 1708 /* - VIN1 ------------------------------------------------------------------- */ 1709 VIN_PFC_PINS(vin1_data8, RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), 1710 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), 1711 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6), 1712 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8)); 1713 VIN_PFC_DAT8(vin1_data8, VI1_DATA0, VI1_DATA1, 1714 VI1_DATA2, VI1_DATA3, 1715 VI1_DATA4, VI1_DATA5, 1716 VI1_DATA6, VI1_DATA7); 1717 VIN_PFC_PINS(vin1_clk, RCAR_GP_PIN(4, 9)); 1718 VIN_PFC_CLK(vin1_clk, VI1_CLK); 1719 VIN_PFC_PINS(vin1_sync, RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22)); 1720 VIN_PFC_SYNC(vin1_sync, VI1_HSYNC, VI1_VSYNC); 1721 1722 static const struct sh_pfc_pin_group pinmux_groups[] = { 1723 SH_PFC_PIN_GROUP(audio_clk_a), 1724 SH_PFC_PIN_GROUP(audio_clk_b), 1725 SH_PFC_PIN_GROUP(audio_clk_c), 1726 SH_PFC_PIN_GROUP(audio_clkout_a), 1727 SH_PFC_PIN_GROUP(audio_clkout_b), 1728 SH_PFC_PIN_GROUP(can0_data_a), 1729 SH_PFC_PIN_GROUP(can0_data_b), 1730 SH_PFC_PIN_GROUP(can1_data_a), 1731 SH_PFC_PIN_GROUP(can1_data_b), 1732 SH_PFC_PIN_GROUP(can_clk_a), 1733 SH_PFC_PIN_GROUP(can_clk_b), 1734 SH_PFC_PIN_GROUP(can_clk_c), 1735 SH_PFC_PIN_GROUP(can_clk_d), 1736 SH_PFC_PIN_GROUP(ether_rmii), 1737 SH_PFC_PIN_GROUP(ether_link), 1738 SH_PFC_PIN_GROUP(ether_magic), 1739 SH_PFC_PIN_GROUP(hscif0_data_a), 1740 SH_PFC_PIN_GROUP(hscif0_data_b), 1741 SH_PFC_PIN_GROUP(hscif0_ctrl_a), 1742 SH_PFC_PIN_GROUP(hscif0_ctrl_b), 1743 SH_PFC_PIN_GROUP(hscif0_clk), 1744 SH_PFC_PIN_GROUP(hscif1_data_a), 1745 SH_PFC_PIN_GROUP(hscif1_data_b), 1746 SH_PFC_PIN_GROUP(hscif1_ctrl_a), 1747 SH_PFC_PIN_GROUP(hscif1_ctrl_b), 1748 SH_PFC_PIN_GROUP(hscif1_clk_a), 1749 SH_PFC_PIN_GROUP(hscif1_clk_b), 1750 SH_PFC_PIN_GROUP(hspi0_a), 1751 SH_PFC_PIN_GROUP(hspi0_b), 1752 SH_PFC_PIN_GROUP(hspi1_a), 1753 SH_PFC_PIN_GROUP(hspi1_b), 1754 SH_PFC_PIN_GROUP(hspi2_a), 1755 SH_PFC_PIN_GROUP(hspi2_b), 1756 SH_PFC_PIN_GROUP(i2c1_a), 1757 SH_PFC_PIN_GROUP(i2c1_b), 1758 SH_PFC_PIN_GROUP(i2c2_a), 1759 SH_PFC_PIN_GROUP(i2c2_b), 1760 SH_PFC_PIN_GROUP(i2c2_c), 1761 SH_PFC_PIN_GROUP(i2c3_a), 1762 SH_PFC_PIN_GROUP(i2c3_b), 1763 SH_PFC_PIN_GROUP(i2c3_c), 1764 SH_PFC_PIN_GROUP(mmc_ctrl), 1765 SH_PFC_PIN_GROUP(mmc_data1), 1766 SH_PFC_PIN_GROUP(mmc_data4), 1767 SH_PFC_PIN_GROUP(mmc_data8), 1768 SH_PFC_PIN_GROUP(scif_clk), 1769 SH_PFC_PIN_GROUP(scif0_data_a), 1770 SH_PFC_PIN_GROUP(scif0_data_b), 1771 SH_PFC_PIN_GROUP(scif0_data_c), 1772 SH_PFC_PIN_GROUP(scif0_data_d), 1773 SH_PFC_PIN_GROUP(scif0_ctrl), 1774 SH_PFC_PIN_GROUP(scif0_clk), 1775 SH_PFC_PIN_GROUP(scif1_data_a), 1776 SH_PFC_PIN_GROUP(scif1_data_b), 1777 SH_PFC_PIN_GROUP(scif1_data_c), 1778 SH_PFC_PIN_GROUP(scif1_data_d), 1779 SH_PFC_PIN_GROUP(scif1_ctrl_a), 1780 SH_PFC_PIN_GROUP(scif1_ctrl_c), 1781 SH_PFC_PIN_GROUP(scif1_clk_a), 1782 SH_PFC_PIN_GROUP(scif1_clk_c), 1783 SH_PFC_PIN_GROUP(scif2_data_a), 1784 SH_PFC_PIN_GROUP(scif2_data_b), 1785 SH_PFC_PIN_GROUP(scif2_data_c), 1786 SH_PFC_PIN_GROUP(scif2_data_d), 1787 SH_PFC_PIN_GROUP(scif2_data_e), 1788 SH_PFC_PIN_GROUP(scif2_clk_a), 1789 SH_PFC_PIN_GROUP(scif2_clk_b), 1790 SH_PFC_PIN_GROUP(scif2_clk_c), 1791 SH_PFC_PIN_GROUP(scif3_data_a), 1792 SH_PFC_PIN_GROUP(scif3_data_b), 1793 SH_PFC_PIN_GROUP(scif3_data_c), 1794 SH_PFC_PIN_GROUP(scif3_data_d), 1795 SH_PFC_PIN_GROUP(scif4_data_a), 1796 SH_PFC_PIN_GROUP(scif4_data_b), 1797 SH_PFC_PIN_GROUP(scif4_data_c), 1798 SH_PFC_PIN_GROUP(scif5_data_a), 1799 SH_PFC_PIN_GROUP(scif5_data_b), 1800 SH_PFC_PIN_GROUP(sdhi0_cd), 1801 SH_PFC_PIN_GROUP(sdhi0_ctrl), 1802 SH_PFC_PIN_GROUP(sdhi0_data1), 1803 SH_PFC_PIN_GROUP(sdhi0_data4), 1804 SH_PFC_PIN_GROUP(sdhi0_wp), 1805 SH_PFC_PIN_GROUP(sdhi1_cd_a), 1806 SH_PFC_PIN_GROUP(sdhi1_cd_b), 1807 SH_PFC_PIN_GROUP(sdhi1_ctrl_a), 1808 SH_PFC_PIN_GROUP(sdhi1_ctrl_b), 1809 SH_PFC_PIN_GROUP(sdhi1_data1_a), 1810 SH_PFC_PIN_GROUP(sdhi1_data1_b), 1811 SH_PFC_PIN_GROUP(sdhi1_data4_a), 1812 SH_PFC_PIN_GROUP(sdhi1_data4_b), 1813 SH_PFC_PIN_GROUP(sdhi1_wp_a), 1814 SH_PFC_PIN_GROUP(sdhi1_wp_b), 1815 SH_PFC_PIN_GROUP(sdhi2_cd_a), 1816 SH_PFC_PIN_GROUP(sdhi2_cd_b), 1817 SH_PFC_PIN_GROUP(sdhi2_ctrl_a), 1818 SH_PFC_PIN_GROUP(sdhi2_ctrl_b), 1819 SH_PFC_PIN_GROUP(sdhi2_data1_a), 1820 SH_PFC_PIN_GROUP(sdhi2_data1_b), 1821 SH_PFC_PIN_GROUP(sdhi2_data4_a), 1822 SH_PFC_PIN_GROUP(sdhi2_data4_b), 1823 SH_PFC_PIN_GROUP(sdhi2_wp_a), 1824 SH_PFC_PIN_GROUP(sdhi2_wp_b), 1825 SH_PFC_PIN_GROUP(ssi012_ctrl), 1826 SH_PFC_PIN_GROUP(ssi0_data), 1827 SH_PFC_PIN_GROUP(ssi1_a_ctrl), 1828 SH_PFC_PIN_GROUP(ssi1_b_ctrl), 1829 SH_PFC_PIN_GROUP(ssi1_data), 1830 SH_PFC_PIN_GROUP(ssi2_a_ctrl), 1831 SH_PFC_PIN_GROUP(ssi2_b_ctrl), 1832 SH_PFC_PIN_GROUP(ssi2_data), 1833 SH_PFC_PIN_GROUP(ssi34_ctrl), 1834 SH_PFC_PIN_GROUP(ssi3_data), 1835 SH_PFC_PIN_GROUP(ssi4_ctrl), 1836 SH_PFC_PIN_GROUP(ssi4_data), 1837 SH_PFC_PIN_GROUP(ssi5_ctrl), 1838 SH_PFC_PIN_GROUP(ssi5_data), 1839 SH_PFC_PIN_GROUP(ssi6_ctrl), 1840 SH_PFC_PIN_GROUP(ssi6_data), 1841 SH_PFC_PIN_GROUP(ssi78_ctrl), 1842 SH_PFC_PIN_GROUP(ssi7_data), 1843 SH_PFC_PIN_GROUP(ssi8_data), 1844 SH_PFC_PIN_GROUP(usb0), 1845 SH_PFC_PIN_GROUP(usb0_ovc), 1846 SH_PFC_PIN_GROUP(usb1), 1847 SH_PFC_PIN_GROUP(usb1_ovc), 1848 SH_PFC_PIN_GROUP(vin0_data8), 1849 SH_PFC_PIN_GROUP(vin0_clk), 1850 SH_PFC_PIN_GROUP(vin0_sync), 1851 SH_PFC_PIN_GROUP(vin1_data8), 1852 SH_PFC_PIN_GROUP(vin1_clk), 1853 SH_PFC_PIN_GROUP(vin1_sync), 1854 }; 1855 1856 static const char * const audio_clk_groups[] = { 1857 "audio_clk_a", 1858 "audio_clk_b", 1859 "audio_clk_c", 1860 "audio_clkout_a", 1861 "audio_clkout_b", 1862 }; 1863 1864 static const char * const can0_groups[] = { 1865 "can0_data_a", 1866 "can0_data_b", 1867 "can_clk_a", 1868 "can_clk_b", 1869 "can_clk_c", 1870 "can_clk_d", 1871 }; 1872 1873 static const char * const can1_groups[] = { 1874 "can1_data_a", 1875 "can1_data_b", 1876 "can_clk_a", 1877 "can_clk_b", 1878 "can_clk_c", 1879 "can_clk_d", 1880 }; 1881 1882 static const char * const ether_groups[] = { 1883 "ether_rmii", 1884 "ether_link", 1885 "ether_magic", 1886 }; 1887 1888 static const char * const hscif0_groups[] = { 1889 "hscif0_data_a", 1890 "hscif0_data_b", 1891 "hscif0_ctrl_a", 1892 "hscif0_ctrl_b", 1893 "hscif0_clk", 1894 }; 1895 1896 static const char * const hscif1_groups[] = { 1897 "hscif1_data_a", 1898 "hscif1_data_b", 1899 "hscif1_ctrl_a", 1900 "hscif1_ctrl_b", 1901 "hscif1_clk_a", 1902 "hscif1_clk_b", 1903 }; 1904 1905 static const char * const hspi0_groups[] = { 1906 "hspi0_a", 1907 "hspi0_b", 1908 }; 1909 1910 static const char * const hspi1_groups[] = { 1911 "hspi1_a", 1912 "hspi1_b", 1913 }; 1914 1915 static const char * const hspi2_groups[] = { 1916 "hspi2_a", 1917 "hspi2_b", 1918 }; 1919 1920 static const char * const i2c1_groups[] = { 1921 "i2c1_a", 1922 "i2c1_b", 1923 }; 1924 1925 static const char * const i2c2_groups[] = { 1926 "i2c2_a", 1927 "i2c2_b", 1928 "i2c2_c", 1929 }; 1930 1931 static const char * const i2c3_groups[] = { 1932 "i2c3_a", 1933 "i2c3_b", 1934 "i2c3_c", 1935 }; 1936 1937 static const char * const mmc_groups[] = { 1938 "mmc_ctrl", 1939 "mmc_data1", 1940 "mmc_data4", 1941 "mmc_data8", 1942 }; 1943 1944 static const char * const scif_clk_groups[] = { 1945 "scif_clk", 1946 }; 1947 1948 static const char * const scif0_groups[] = { 1949 "scif0_data_a", 1950 "scif0_data_b", 1951 "scif0_data_c", 1952 "scif0_data_d", 1953 "scif0_ctrl", 1954 "scif0_clk", 1955 }; 1956 1957 static const char * const scif1_groups[] = { 1958 "scif1_data_a", 1959 "scif1_data_b", 1960 "scif1_data_c", 1961 "scif1_data_d", 1962 "scif1_ctrl_a", 1963 "scif1_ctrl_c", 1964 "scif1_clk_a", 1965 "scif1_clk_c", 1966 }; 1967 1968 static const char * const scif2_groups[] = { 1969 "scif2_data_a", 1970 "scif2_data_b", 1971 "scif2_data_c", 1972 "scif2_data_d", 1973 "scif2_data_e", 1974 "scif2_clk_a", 1975 "scif2_clk_b", 1976 "scif2_clk_c", 1977 }; 1978 1979 static const char * const scif3_groups[] = { 1980 "scif3_data_a", 1981 "scif3_data_b", 1982 "scif3_data_c", 1983 "scif3_data_d", 1984 }; 1985 1986 static const char * const scif4_groups[] = { 1987 "scif4_data_a", 1988 "scif4_data_b", 1989 "scif4_data_c", 1990 }; 1991 1992 static const char * const scif5_groups[] = { 1993 "scif5_data_a", 1994 "scif5_data_b", 1995 }; 1996 1997 1998 static const char * const sdhi0_groups[] = { 1999 "sdhi0_cd", 2000 "sdhi0_ctrl", 2001 "sdhi0_data1", 2002 "sdhi0_data4", 2003 "sdhi0_wp", 2004 }; 2005 2006 static const char * const sdhi1_groups[] = { 2007 "sdhi1_cd_a", 2008 "sdhi1_cd_b", 2009 "sdhi1_ctrl_a", 2010 "sdhi1_ctrl_b", 2011 "sdhi1_data1_a", 2012 "sdhi1_data1_b", 2013 "sdhi1_data4_a", 2014 "sdhi1_data4_b", 2015 "sdhi1_wp_a", 2016 "sdhi1_wp_b", 2017 }; 2018 2019 static const char * const sdhi2_groups[] = { 2020 "sdhi2_cd_a", 2021 "sdhi2_cd_b", 2022 "sdhi2_ctrl_a", 2023 "sdhi2_ctrl_b", 2024 "sdhi2_data1_a", 2025 "sdhi2_data1_b", 2026 "sdhi2_data4_a", 2027 "sdhi2_data4_b", 2028 "sdhi2_wp_a", 2029 "sdhi2_wp_b", 2030 }; 2031 2032 static const char * const ssi_groups[] = { 2033 "ssi012_ctrl", 2034 "ssi0_data", 2035 "ssi1_a_ctrl", 2036 "ssi1_b_ctrl", 2037 "ssi1_data", 2038 "ssi2_a_ctrl", 2039 "ssi2_b_ctrl", 2040 "ssi2_data", 2041 "ssi34_ctrl", 2042 "ssi3_data", 2043 "ssi4_ctrl", 2044 "ssi4_data", 2045 "ssi5_ctrl", 2046 "ssi5_data", 2047 "ssi6_ctrl", 2048 "ssi6_data", 2049 "ssi78_ctrl", 2050 "ssi7_data", 2051 "ssi8_data", 2052 }; 2053 2054 static const char * const usb0_groups[] = { 2055 "usb0", 2056 "usb0_ovc", 2057 }; 2058 2059 static const char * const usb1_groups[] = { 2060 "usb1", 2061 "usb1_ovc", 2062 }; 2063 2064 static const char * const vin0_groups[] = { 2065 "vin0_data8", 2066 "vin0_clk", 2067 "vin0_sync", 2068 }; 2069 2070 static const char * const vin1_groups[] = { 2071 "vin1_data8", 2072 "vin1_clk", 2073 "vin1_sync", 2074 }; 2075 2076 static const struct sh_pfc_function pinmux_functions[] = { 2077 SH_PFC_FUNCTION(audio_clk), 2078 SH_PFC_FUNCTION(can0), 2079 SH_PFC_FUNCTION(can1), 2080 SH_PFC_FUNCTION(ether), 2081 SH_PFC_FUNCTION(hscif0), 2082 SH_PFC_FUNCTION(hscif1), 2083 SH_PFC_FUNCTION(hspi0), 2084 SH_PFC_FUNCTION(hspi1), 2085 SH_PFC_FUNCTION(hspi2), 2086 SH_PFC_FUNCTION(i2c1), 2087 SH_PFC_FUNCTION(i2c2), 2088 SH_PFC_FUNCTION(i2c3), 2089 SH_PFC_FUNCTION(mmc), 2090 SH_PFC_FUNCTION(scif_clk), 2091 SH_PFC_FUNCTION(scif0), 2092 SH_PFC_FUNCTION(scif1), 2093 SH_PFC_FUNCTION(scif2), 2094 SH_PFC_FUNCTION(scif3), 2095 SH_PFC_FUNCTION(scif4), 2096 SH_PFC_FUNCTION(scif5), 2097 SH_PFC_FUNCTION(sdhi0), 2098 SH_PFC_FUNCTION(sdhi1), 2099 SH_PFC_FUNCTION(sdhi2), 2100 SH_PFC_FUNCTION(ssi), 2101 SH_PFC_FUNCTION(usb0), 2102 SH_PFC_FUNCTION(usb1), 2103 SH_PFC_FUNCTION(vin0), 2104 SH_PFC_FUNCTION(vin1), 2105 }; 2106 2107 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 2108 { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) { 2109 GP_0_31_FN, FN_IP1_14_11, 2110 GP_0_30_FN, FN_IP1_10_8, 2111 GP_0_29_FN, FN_IP1_7_5, 2112 GP_0_28_FN, FN_IP1_4_2, 2113 GP_0_27_FN, FN_IP1_1, 2114 GP_0_26_FN, FN_IP1_0, 2115 GP_0_25_FN, FN_IP0_30, 2116 GP_0_24_FN, FN_IP0_29, 2117 GP_0_23_FN, FN_IP0_28, 2118 GP_0_22_FN, FN_IP0_27, 2119 GP_0_21_FN, FN_IP0_26, 2120 GP_0_20_FN, FN_IP0_25, 2121 GP_0_19_FN, FN_IP0_24, 2122 GP_0_18_FN, FN_IP0_23, 2123 GP_0_17_FN, FN_IP0_22, 2124 GP_0_16_FN, FN_IP0_21, 2125 GP_0_15_FN, FN_IP0_20, 2126 GP_0_14_FN, FN_IP0_19, 2127 GP_0_13_FN, FN_IP0_18, 2128 GP_0_12_FN, FN_IP0_17, 2129 GP_0_11_FN, FN_IP0_16, 2130 GP_0_10_FN, FN_IP0_15, 2131 GP_0_9_FN, FN_A3, 2132 GP_0_8_FN, FN_A2, 2133 GP_0_7_FN, FN_A1, 2134 GP_0_6_FN, FN_IP0_14_12, 2135 GP_0_5_FN, FN_IP0_11_8, 2136 GP_0_4_FN, FN_IP0_7_5, 2137 GP_0_3_FN, FN_IP0_4_2, 2138 GP_0_2_FN, FN_PENC1, 2139 GP_0_1_FN, FN_PENC0, 2140 GP_0_0_FN, FN_IP0_1_0 } 2141 }, 2142 { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) { 2143 GP_1_31_FN, FN_IP4_6_4, 2144 GP_1_30_FN, FN_IP4_3_1, 2145 GP_1_29_FN, FN_IP4_0, 2146 GP_1_28_FN, FN_IP3_31, 2147 GP_1_27_FN, FN_IP3_30, 2148 GP_1_26_FN, FN_IP3_29, 2149 GP_1_25_FN, FN_IP3_28, 2150 GP_1_24_FN, FN_IP3_27, 2151 GP_1_23_FN, FN_IP3_26_24, 2152 GP_1_22_FN, FN_IP3_23_21, 2153 GP_1_21_FN, FN_IP3_20_19, 2154 GP_1_20_FN, FN_IP3_18_16, 2155 GP_1_19_FN, FN_IP3_15_13, 2156 GP_1_18_FN, FN_IP3_12_10, 2157 GP_1_17_FN, FN_IP3_9_8, 2158 GP_1_16_FN, FN_IP3_7_5, 2159 GP_1_15_FN, FN_IP3_4_2, 2160 GP_1_14_FN, FN_IP3_1_0, 2161 GP_1_13_FN, FN_IP2_31, 2162 GP_1_12_FN, FN_IP2_30, 2163 GP_1_11_FN, FN_IP2_17, 2164 GP_1_10_FN, FN_IP2_16_14, 2165 GP_1_9_FN, FN_IP2_13_12, 2166 GP_1_8_FN, FN_IP2_11_9, 2167 GP_1_7_FN, FN_IP2_8_6, 2168 GP_1_6_FN, FN_IP2_5_3, 2169 GP_1_5_FN, FN_IP2_2_0, 2170 GP_1_4_FN, FN_IP1_29_28, 2171 GP_1_3_FN, FN_IP1_27_25, 2172 GP_1_2_FN, FN_IP1_24, 2173 GP_1_1_FN, FN_WE0, 2174 GP_1_0_FN, FN_IP1_23_21 } 2175 }, 2176 { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) { 2177 GP_2_31_FN, FN_IP6_7, 2178 GP_2_30_FN, FN_IP6_6_5, 2179 GP_2_29_FN, FN_IP6_4_2, 2180 GP_2_28_FN, FN_IP6_1_0, 2181 GP_2_27_FN, FN_IP5_30_29, 2182 GP_2_26_FN, FN_IP5_28_26, 2183 GP_2_25_FN, FN_IP5_25_23, 2184 GP_2_24_FN, FN_IP5_22_21, 2185 GP_2_23_FN, FN_AUDIO_CLKB, 2186 GP_2_22_FN, FN_AUDIO_CLKA, 2187 GP_2_21_FN, FN_IP5_20_18, 2188 GP_2_20_FN, FN_IP5_17_15, 2189 GP_2_19_FN, FN_IP5_14_13, 2190 GP_2_18_FN, FN_IP5_12, 2191 GP_2_17_FN, FN_IP5_11_10, 2192 GP_2_16_FN, FN_IP5_9_8, 2193 GP_2_15_FN, FN_IP5_7, 2194 GP_2_14_FN, FN_IP5_6, 2195 GP_2_13_FN, FN_IP5_5_4, 2196 GP_2_12_FN, FN_IP5_3_2, 2197 GP_2_11_FN, FN_IP5_1_0, 2198 GP_2_10_FN, FN_IP4_30_29, 2199 GP_2_9_FN, FN_IP4_28_27, 2200 GP_2_8_FN, FN_IP4_26_25, 2201 GP_2_7_FN, FN_IP4_24_21, 2202 GP_2_6_FN, FN_IP4_20_17, 2203 GP_2_5_FN, FN_IP4_16_15, 2204 GP_2_4_FN, FN_IP4_14_13, 2205 GP_2_3_FN, FN_IP4_12_11, 2206 GP_2_2_FN, FN_IP4_10_9, 2207 GP_2_1_FN, FN_IP4_8, 2208 GP_2_0_FN, FN_IP4_7 } 2209 }, 2210 { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) { 2211 GP_3_31_FN, FN_IP8_10_9, 2212 GP_3_30_FN, FN_IP8_8_6, 2213 GP_3_29_FN, FN_IP8_5_3, 2214 GP_3_28_FN, FN_IP8_2_0, 2215 GP_3_27_FN, FN_IP7_31_29, 2216 GP_3_26_FN, FN_IP7_28_25, 2217 GP_3_25_FN, FN_IP7_24_22, 2218 GP_3_24_FN, FN_IP7_21, 2219 GP_3_23_FN, FN_IP7_20_18, 2220 GP_3_22_FN, FN_IP7_17_15, 2221 GP_3_21_FN, FN_IP7_14_12, 2222 GP_3_20_FN, FN_IP7_11_9, 2223 GP_3_19_FN, FN_IP7_8_6, 2224 GP_3_18_FN, FN_IP7_5_4, 2225 GP_3_17_FN, FN_IP7_3_2, 2226 GP_3_16_FN, FN_IP7_1_0, 2227 GP_3_15_FN, FN_IP6_31_30, 2228 GP_3_14_FN, FN_IP6_29_28, 2229 GP_3_13_FN, FN_IP6_27_26, 2230 GP_3_12_FN, FN_IP6_25_24, 2231 GP_3_11_FN, FN_IP6_23_22, 2232 GP_3_10_FN, FN_IP6_21, 2233 GP_3_9_FN, FN_IP6_20_19, 2234 GP_3_8_FN, FN_IP6_18_17, 2235 GP_3_7_FN, FN_IP6_16, 2236 GP_3_6_FN, FN_IP6_15_14, 2237 GP_3_5_FN, FN_IP6_13, 2238 GP_3_4_FN, FN_IP6_12_11, 2239 GP_3_3_FN, FN_IP6_10, 2240 GP_3_2_FN, FN_SSI_SCK34, 2241 GP_3_1_FN, FN_IP6_9, 2242 GP_3_0_FN, FN_IP6_8 } 2243 }, 2244 { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) { 2245 0, 0, 2246 0, 0, 2247 0, 0, 2248 0, 0, 2249 0, 0, 2250 GP_4_26_FN, FN_AVS2, 2251 GP_4_25_FN, FN_AVS1, 2252 GP_4_24_FN, FN_IP10_24_22, 2253 GP_4_23_FN, FN_IP10_21_19, 2254 GP_4_22_FN, FN_IP10_18_16, 2255 GP_4_21_FN, FN_IP10_15_13, 2256 GP_4_20_FN, FN_IP10_12_9, 2257 GP_4_19_FN, FN_IP10_8_6, 2258 GP_4_18_FN, FN_IP10_5_3, 2259 GP_4_17_FN, FN_IP10_2_0, 2260 GP_4_16_FN, FN_IP9_29_27, 2261 GP_4_15_FN, FN_IP9_26_24, 2262 GP_4_14_FN, FN_IP9_23_21, 2263 GP_4_13_FN, FN_IP9_20_18, 2264 GP_4_12_FN, FN_IP9_17_15, 2265 GP_4_11_FN, FN_IP9_14_12, 2266 GP_4_10_FN, FN_IP9_11_9, 2267 GP_4_9_FN, FN_IP9_8_6, 2268 GP_4_8_FN, FN_IP9_5_3, 2269 GP_4_7_FN, FN_IP9_2_0, 2270 GP_4_6_FN, FN_IP8_29_27, 2271 GP_4_5_FN, FN_IP8_26_24, 2272 GP_4_4_FN, FN_IP8_23_22, 2273 GP_4_3_FN, FN_IP8_21_19, 2274 GP_4_2_FN, FN_IP8_18_16, 2275 GP_4_1_FN, FN_IP8_15_14, 2276 GP_4_0_FN, FN_IP8_13_11 } 2277 }, 2278 2279 { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32, 2280 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2281 1, 1, 1, 1, 1, 1, 3, 4, 3, 3, 2) { 2282 /* IP0_31 [1] */ 2283 0, 0, 2284 /* IP0_30 [1] */ 2285 FN_A19, 0, 2286 /* IP0_29 [1] */ 2287 FN_A18, 0, 2288 /* IP0_28 [1] */ 2289 FN_A17, 0, 2290 /* IP0_27 [1] */ 2291 FN_A16, 0, 2292 /* IP0_26 [1] */ 2293 FN_A15, 0, 2294 /* IP0_25 [1] */ 2295 FN_A14, 0, 2296 /* IP0_24 [1] */ 2297 FN_A13, 0, 2298 /* IP0_23 [1] */ 2299 FN_A12, 0, 2300 /* IP0_22 [1] */ 2301 FN_A11, 0, 2302 /* IP0_21 [1] */ 2303 FN_A10, 0, 2304 /* IP0_20 [1] */ 2305 FN_A9, 0, 2306 /* IP0_19 [1] */ 2307 FN_A8, 0, 2308 /* IP0_18 [1] */ 2309 FN_A7, 0, 2310 /* IP0_17 [1] */ 2311 FN_A6, 0, 2312 /* IP0_16 [1] */ 2313 FN_A5, 0, 2314 /* IP0_15 [1] */ 2315 FN_A4, 0, 2316 /* IP0_14_12 [3] */ 2317 FN_SD1_DAT3_A, FN_MMC_D3, 0, FN_A0, 2318 FN_ATAG0_A, 0, FN_REMOCON_B, 0, 2319 /* IP0_11_8 [4] */ 2320 FN_SD1_DAT2_A, FN_MMC_D2, 0, FN_BS, 2321 FN_ATADIR0_A, 0, FN_SDSELF_B, 0, 2322 FN_PWM4_B, 0, 0, 0, 2323 0, 0, 0, 0, 2324 /* IP0_7_5 [3] */ 2325 FN_AUDATA1, FN_ARM_TRACEDATA_1, FN_GPSIN_C, FN_USB_OVC1, 2326 FN_RX2_E, FN_SCL2_B, 0, 0, 2327 /* IP0_4_2 [3] */ 2328 FN_AUDATA0, FN_ARM_TRACEDATA_0, FN_GPSCLK_C, FN_USB_OVC0, 2329 FN_TX2_E, FN_SDA2_B, 0, 0, 2330 /* IP0_1_0 [2] */ 2331 FN_PRESETOUT, 0, FN_PWM1, 0, 2332 } 2333 }, 2334 { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32, 2335 1, 1, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3, 3, 1, 1) { 2336 /* IP1_31 [1] */ 2337 0, 0, 2338 /* IP1_30 [1] */ 2339 0, 0, 2340 /* IP1_29_28 [2] */ 2341 FN_EX_CS1, FN_MMC_D4, 0, 0, 2342 /* IP1_27_25 [3] */ 2343 FN_SSI_WS1_B, FN_EX_CS0, FN_SCL2_A, FN_TX3_C, 2344 FN_TS_SCK0_A, 0, 0, 0, 2345 /* IP1_24 [1] */ 2346 FN_WE1, FN_ATAWR0_B, 2347 /* IP1_23_21 [3] */ 2348 FN_MMC_D5, FN_ATADIR0_B, 0, FN_RD_WR, 2349 0, 0, 0, 0, 2350 /* IP1_20_18 [3] */ 2351 FN_SSI_SCK1_B, FN_ATAG0_B, FN_CS1_A26, FN_SDA2_A, 2352 FN_SCK2_B, 0, 0, 0, 2353 /* IP1_17 [1] */ 2354 FN_CS0, FN_HSPI_RX1_B, 2355 /* IP1_16_15 [2] */ 2356 FN_CLKOUT, FN_HSPI_TX1_B, FN_PWM0_B, 0, 2357 /* IP1_14_11 [4] */ 2358 FN_SD1_WP_A, FN_MMC_D7, 0, FN_A25, 2359 FN_DACK1_A, 0, FN_HCTS0_B, FN_RX3_C, 2360 FN_TS_SDAT0_A, 0, 0, 0, 2361 0, 0, 0, 0, 2362 /* IP1_10_8 [3] */ 2363 FN_SD1_CLK_B, FN_MMC_D6, 0, FN_A24, 2364 FN_DREQ1_A, 0, FN_HRX0_B, FN_TS_SPSYNC0_A, 2365 /* IP1_7_5 [3] */ 2366 FN_A23, FN_HTX0_B, FN_TX2_B, FN_DACK2_A, 2367 FN_TS_SDEN0_A, 0, 0, 0, 2368 /* IP1_4_2 [3] */ 2369 FN_A22, FN_HRTS0_B, FN_RX2_B, FN_DREQ2_A, 2370 0, 0, 0, 0, 2371 /* IP1_1 [1] */ 2372 FN_A21, FN_HSPI_CLK1_B, 2373 /* IP1_0 [1] */ 2374 FN_A20, FN_HSPI_CS1_B, 2375 } 2376 }, 2377 { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32, 2378 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2379 1, 1, 1, 1, 3, 2, 3, 3, 3, 3) { 2380 /* IP2_31 [1] */ 2381 FN_MLB_CLK, FN_IRQ1_A, 2382 /* IP2_30 [1] */ 2383 FN_RD_WR_B, FN_IRQ0, 2384 /* IP2_29 [1] */ 2385 FN_D11, 0, 2386 /* IP2_28 [1] */ 2387 FN_D10, 0, 2388 /* IP2_27 [1] */ 2389 FN_D9, 0, 2390 /* IP2_26 [1] */ 2391 FN_D8, 0, 2392 /* IP2_25 [1] */ 2393 FN_D7, 0, 2394 /* IP2_24 [1] */ 2395 FN_D6, 0, 2396 /* IP2_23 [1] */ 2397 FN_D5, 0, 2398 /* IP2_22 [1] */ 2399 FN_D4, 0, 2400 /* IP2_21 [1] */ 2401 FN_D3, 0, 2402 /* IP2_20 [1] */ 2403 FN_D2, 0, 2404 /* IP2_19 [1] */ 2405 FN_D1, 0, 2406 /* IP2_18 [1] */ 2407 FN_D0, 0, 2408 /* IP2_17 [1] */ 2409 FN_EX_WAIT0, FN_PWM0_C, 2410 /* IP2_16_14 [3] */ 2411 FN_DACK0, 0, 0, FN_TX3_A, 2412 FN_DRACK0, 0, 0, 0, 2413 /* IP2_13_12 [2] */ 2414 FN_DREQ0_A, 0, 0, FN_RX3_A, 2415 /* IP2_11_9 [3] */ 2416 FN_SD1_DAT1_A, FN_MMC_D1, 0, FN_ATAWR0_A, 2417 FN_EX_CS5, FN_EX_WAIT2_A, 0, 0, 2418 /* IP2_8_6 [3] */ 2419 FN_SD1_DAT0_A, FN_MMC_D0, 0, FN_ATARD0, 2420 FN_EX_CS4, FN_EX_WAIT1_A, 0, 0, 2421 /* IP2_5_3 [3] */ 2422 FN_SD1_CMD_A, FN_MMC_CMD, 0, FN_ATACS10, 2423 FN_EX_CS3, 0, 0, 0, 2424 /* IP2_2_0 [3] */ 2425 FN_SD1_CLK_A, FN_MMC_CLK, 0, FN_ATACS00, 2426 FN_EX_CS2, 0, 0, 0, 2427 } 2428 }, 2429 { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32, 2430 1, 1, 1, 1, 1, 3, 3, 2, 2431 3, 3, 3, 2, 3, 3, 2) { 2432 /* IP3_31 [1] */ 2433 FN_DU0_DR6, FN_LCDOUT6, 2434 /* IP3_30 [1] */ 2435 FN_DU0_DR5, FN_LCDOUT5, 2436 /* IP3_29 [1] */ 2437 FN_DU0_DR4, FN_LCDOUT4, 2438 /* IP3_28 [1] */ 2439 FN_DU0_DR3, FN_LCDOUT3, 2440 /* IP3_27 [1] */ 2441 FN_DU0_DR2, FN_LCDOUT2, 2442 /* IP3_26_24 [3] */ 2443 FN_SSI_WS4, FN_DU0_DR1, FN_LCDOUT1, FN_AUDATA3, 2444 FN_ARM_TRACEDATA_3, FN_SCL3_C, FN_ADICHS2, FN_TS_SPSYNC0_B, 2445 /* IP3_23_21 [3] */ 2446 FN_SSI_SCK4, FN_DU0_DR0, FN_LCDOUT0, FN_AUDATA2, 2447 FN_ARM_TRACEDATA_2, FN_SDA3_C, FN_ADICHS1, FN_TS_SDEN0_B, 2448 /* IP3_20_19 [2] */ 2449 FN_SD1_DAT3_B, FN_HRTS0_A, FN_RTS0, 0, 2450 /* IP3_18_16 [3] */ 2451 FN_SD1_DAT2_B, FN_HCTS0_A, FN_CTS0, 0, 2452 0, 0, 0, 0, 2453 /* IP3_15_13 [3] */ 2454 FN_SD1_DAT1_B, FN_HSCK0, FN_SCK0, FN_SCL3_B, 2455 0, 0, 0, 0, 2456 /* IP3_12_10 [3] */ 2457 FN_SD1_DAT0_B, FN_HRX0_A, FN_RX0_A, 0, 2458 0, 0, 0, 0, 2459 /* IP3_9_8 [2] */ 2460 FN_SD1_CLK_B, FN_HTX0_A, FN_TX0_A, 0, 2461 /* IP3_7_5 [3] */ 2462 FN_SD1_CMD_B, FN_SCIF_CLK, FN_AUDIO_CLKOUT_B, FN_CAN_CLK_B, 2463 FN_SDA3_B, 0, 0, 0, 2464 /* IP3_4_2 [3] */ 2465 FN_MLB_DAT, FN_TX5_B, FN_SCL3_A, FN_IRQ3_A, 2466 FN_SDSELF_B, 0, 0, 0, 2467 /* IP3_1_0 [2] */ 2468 FN_MLB_SIG, FN_RX5_B, FN_SDA3_A, FN_IRQ2_A, 2469 } 2470 }, 2471 { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32, 2472 1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1, 3, 3, 1) { 2473 /* IP4_31 [1] */ 2474 0, 0, 2475 /* IP4_30_29 [2] */ 2476 FN_VI0_R4_B, FN_DU0_DB4, FN_LCDOUT20, 0, 2477 /* IP4_28_27 [2] */ 2478 FN_VI0_R3_B, FN_DU0_DB3, FN_LCDOUT19, 0, 2479 /* IP4_26_25 [2] */ 2480 FN_VI0_R2_B, FN_DU0_DB2, FN_LCDOUT18, 0, 2481 /* IP4_24_21 [4] */ 2482 FN_AUDIO_CLKC, FN_VI0_R1_B, FN_DU0_DB1, FN_LCDOUT17, 2483 FN_AUDATA7, FN_ARM_TRACEDATA_7, FN_GPSIN_A, 0, 2484 FN_ADICS_SAMP, FN_TS_SCK0_B, 0, 0, 2485 0, 0, 0, 0, 2486 /* IP4_20_17 [4] */ 2487 FN_SSI_SCK2_B, FN_VI0_R0_B, FN_DU0_DB0, FN_LCDOUT16, 2488 FN_AUDATA6, FN_ARM_TRACEDATA_6, FN_GPSCLK_A, FN_PWM0_A, 2489 FN_ADICLK, FN_TS_SDAT0_B, 0, 0, 2490 0, 0, 0, 0, 2491 /* IP4_16_15 [2] */ 2492 FN_DU0_DG7, FN_LCDOUT15, FN_TX4_A, 0, 2493 /* IP4_14_13 [2] */ 2494 FN_DU0_DG6, FN_LCDOUT14, FN_RX4_A, 0, 2495 /* IP4_12_11 [2] */ 2496 FN_DU0_DG5, FN_LCDOUT13, FN_TX0_B, 0, 2497 /* IP4_10_9 [2] */ 2498 FN_DU0_DG4, FN_LCDOUT12, FN_RX0_B, 0, 2499 /* IP4_8 [1] */ 2500 FN_DU0_DG3, FN_LCDOUT11, 2501 /* IP4_7 [1] */ 2502 FN_DU0_DG2, FN_LCDOUT10, 2503 /* IP4_6_4 [3] */ 2504 FN_DU0_DG1, FN_LCDOUT9, FN_AUDATA5, FN_ARM_TRACEDATA_5, 2505 FN_RX1_D, FN_CAN0_RX_A, FN_ADIDATA, 0, 2506 /* IP4_3_1 [3] */ 2507 FN_DU0_DG0, FN_LCDOUT8, FN_AUDATA4, FN_ARM_TRACEDATA_4, 2508 FN_TX1_D, FN_CAN0_TX_A, FN_ADICHS0, 0, 2509 /* IP4_0 [1] */ 2510 FN_DU0_DR7, FN_LCDOUT7, 2511 } 2512 }, 2513 { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32, 2514 1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1, 1, 2, 2, 2) { 2515 2516 /* IP5_31 [1] */ 2517 0, 0, 2518 /* IP5_30_29 [2] */ 2519 FN_SSI_SDATA7, FN_HSPI_TX0_B, FN_RX2_A, FN_CAN0_RX_B, 2520 /* IP5_28_26 [3] */ 2521 FN_SSI_SDATA8, FN_SSI_SCK2_A, FN_HSPI_CS0_B, FN_TX2_A, 2522 FN_CAN0_TX_B, 0, 0, 0, 2523 /* IP5_25_23 [3] */ 2524 FN_SD1_WP_B, FN_SSI_WS78, FN_HSPI_CLK0_B, FN_RX1_B, 2525 FN_CAN_CLK_D, 0, 0, 0, 2526 /* IP5_22_21 [2] */ 2527 FN_SD1_CD_B, FN_SSI_SCK78, FN_HSPI_RX0_B, FN_TX1_B, 2528 /* IP5_20_18 [3] */ 2529 FN_SSI_WS1_A, FN_DU0_CDE, FN_QPOLB, FN_AUDSYNC, 2530 FN_ARM_TRACECTL, FN_FMIN_D, 0, 0, 2531 /* IP5_17_15 [3] */ 2532 FN_SSI_SCK1_A, FN_DU0_DISP, FN_QPOLA, FN_AUDCK, 2533 FN_ARM_TRACECLK, FN_BPFCLK_D, 0, 0, 2534 /* IP5_14_13 [2] */ 2535 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, 2536 FN_FMCLK_D, 0, 2537 /* IP5_12 [1] */ 2538 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 2539 /* IP5_11_10 [2] */ 2540 FN_SSI_WS2_B, FN_DU0_EXHSYNC_DU0_HSYNC, 2541 FN_QSTH_QHS, 0, 2542 /* IP5_9_8 [2] */ 2543 FN_DU0_DOTCLKO_UT1, FN_QSTVB_QVE, 2544 FN_AUDIO_CLKOUT_A, FN_REMOCON_C, 2545 /* IP5_7 [1] */ 2546 FN_DU0_DOTCLKO_UT0, FN_QCLK, 2547 /* IP5_6 [1] */ 2548 FN_DU0_DOTCLKIN, FN_QSTVA_QVS, 2549 /* IP5_5_4 [2] */ 2550 FN_VI1_DATA11_B, FN_DU0_DB7, FN_LCDOUT23, 0, 2551 /* IP5_3_2 [2] */ 2552 FN_VI1_DATA10_B, FN_DU0_DB6, FN_LCDOUT22, 0, 2553 /* IP5_1_0 [2] */ 2554 FN_VI0_R5_B, FN_DU0_DB5, FN_LCDOUT21, 0, 2555 } 2556 }, 2557 { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32, 2558 2, 2, 2, 2, 2, 1, 2, 2, 1, 2, 2559 1, 2, 1, 1, 1, 1, 2, 3, 2) { 2560 /* IP6_31_30 [2] */ 2561 FN_SD0_DAT2, 0, FN_SUB_TDI, 0, 2562 /* IP6_29_28 [2] */ 2563 FN_SD0_DAT1, 0, FN_SUB_TCK, 0, 2564 /* IP6_27_26 [2] */ 2565 FN_SD0_DAT0, 0, FN_SUB_TMS, 0, 2566 /* IP6_25_24 [2] */ 2567 FN_SD0_CMD, 0, FN_SUB_TRST, 0, 2568 /* IP6_23_22 [2] */ 2569 FN_SD0_CLK, 0, FN_SUB_TDO, 0, 2570 /* IP6_21 [1] */ 2571 FN_SSI_SDATA0, FN_ARM_TRACEDATA_15, 2572 /* IP6_20_19 [2] */ 2573 FN_SSI_SDATA1, FN_ARM_TRACEDATA_14, 2574 FN_SCL1_A, FN_SCK2_A, 2575 /* IP6_18_17 [2] */ 2576 FN_SSI_SDATA2, FN_HSPI_CS2_A, 2577 FN_ARM_TRACEDATA_13, FN_SDA1_A, 2578 /* IP6_16 [1] */ 2579 FN_SSI_WS012, FN_ARM_TRACEDATA_12, 2580 /* IP6_15_14 [2] */ 2581 FN_SSI_SCK012, FN_ARM_TRACEDATA_11, 2582 FN_TX0_D, 0, 2583 /* IP6_13 [1] */ 2584 FN_SSI_SDATA3, FN_ARM_TRACEDATA_10, 2585 /* IP6_12_11 [2] */ 2586 FN_SSI_SDATA4, FN_SSI_WS2_A, 2587 FN_ARM_TRACEDATA_9, 0, 2588 /* IP6_10 [1] */ 2589 FN_SSI_WS34, FN_ARM_TRACEDATA_8, 2590 /* IP6_9 [1] */ 2591 FN_SSI_SDATA5, FN_RX0_D, 2592 /* IP6_8 [1] */ 2593 FN_SSI_WS5, FN_TX4_C, 2594 /* IP6_7 [1] */ 2595 FN_SSI_SCK5, FN_RX4_C, 2596 /* IP6_6_5 [2] */ 2597 FN_SSI_SDATA6, FN_HSPI_TX2_A, 2598 FN_FMIN_B, 0, 2599 /* IP6_4_2 [3] */ 2600 FN_SSI_WS6, FN_HSPI_CLK2_A, 2601 FN_BPFCLK_B, FN_CAN1_RX_B, 2602 0, 0, 0, 0, 2603 /* IP6_1_0 [2] */ 2604 FN_SSI_SCK6, FN_HSPI_RX2_A, 2605 FN_FMCLK_B, FN_CAN1_TX_B, 2606 } 2607 }, 2608 { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32, 2609 3, 4, 3, 1, 3, 3, 3, 3, 3, 2, 2, 2) { 2610 2611 /* IP7_31_29 [3] */ 2612 FN_VI0_HSYNC, FN_SD2_CD_B, FN_VI1_DATA2, FN_DU1_DR2, 2613 0, FN_HSPI_CS1_A, FN_RX3_B, 0, 2614 /* IP7_28_25 [4] */ 2615 FN_VI0_FIELD, FN_SD2_DAT3_B, FN_VI0_R3_C, FN_VI1_DATA1, 2616 FN_DU1_DG7, 0, FN_HSPI_CLK1_A, FN_TX4_B, 2617 0, 0, 0, 0, 2618 0, 0, 0, 0, 2619 /* IP7_24_22 [3] */ 2620 FN_VI0_CLKENB, FN_SD2_DAT2_B, FN_VI1_DATA0, FN_DU1_DG6, 2621 0, FN_HSPI_RX1_A, FN_RX4_B, 0, 2622 /* IP7_21 [1] */ 2623 FN_VI0_CLK, FN_CAN_CLK_A, 2624 /* IP7_20_18 [3] */ 2625 FN_TCLK0, FN_HSCK1_A, FN_FMIN_A, 0, 2626 FN_IRQ2_C, FN_CTS1_C, FN_SPEEDIN, 0, 2627 /* IP7_17_15 [3] */ 2628 FN_VI1_VSYNC, FN_HSPI_TX0, FN_HCTS1_A, FN_BPFCLK_A, 2629 0, FN_TX1_C, 0, 0, 2630 /* IP7_14_12 [3] */ 2631 FN_VI1_HSYNC, FN_HSPI_RX0_A, FN_HRTS1_A, FN_FMCLK_A, 2632 0, FN_RX1_C, 0, 0, 2633 /* IP7_11_9 [3] */ 2634 FN_VI1_FIELD, FN_HSPI_CS0_A, FN_HRX1_A, 0, 2635 FN_SCK1_C, 0, 0, 0, 2636 /* IP7_8_6 [3] */ 2637 FN_VI1_CLKENB, FN_HSPI_CLK0_A, FN_HTX1_A, 0, 2638 FN_RTS1_C, 0, 0, 0, 2639 /* IP7_5_4 [2] */ 2640 FN_SD0_WP, 0, FN_RX5_A, 0, 2641 /* IP7_3_2 [2] */ 2642 FN_SD0_CD, 0, FN_TX5_A, 0, 2643 /* IP7_1_0 [2] */ 2644 FN_SD0_DAT3, 0, FN_IRQ1_B, 0, 2645 } 2646 }, 2647 { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32, 2648 1, 1, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3) { 2649 /* IP8_31 [1] */ 2650 0, 0, 2651 /* IP8_30 [1] */ 2652 0, 0, 2653 /* IP8_29_27 [3] */ 2654 FN_VI0_G3, FN_SD2_CMD_B, FN_VI1_DATA5, FN_DU1_DR5, 2655 0, FN_HRX1_B, 0, 0, 2656 /* IP8_26_24 [3] */ 2657 FN_VI0_G2, FN_SD2_CLK_B, FN_VI1_DATA4, FN_DU1_DR4, 2658 0, FN_HTX1_B, 0, 0, 2659 /* IP8_23_22 [2] */ 2660 FN_VI0_DATA7_VI0_G1, FN_DU1_DB5, 2661 FN_RTS1_A, 0, 2662 /* IP8_21_19 [3] */ 2663 FN_VI0_DATA6_VI0_G0, FN_DU1_DB4, 2664 FN_CTS1_A, FN_PWM5, 2665 0, 0, 0, 0, 2666 /* IP8_18_16 [3] */ 2667 FN_VI0_DATA5_VI0_B5, FN_DU1_DB3, FN_SCK1_A, FN_PWM4, 2668 0, FN_HSCK1_B, 0, 0, 2669 /* IP8_15_14 [2] */ 2670 FN_VI0_DATA4_VI0_B4, FN_DU1_DB2, FN_RX1_A, 0, 2671 /* IP8_13_11 [3] */ 2672 FN_VI0_DATA3_VI0_B3, FN_DU1_DG5, FN_TX1_A, FN_TX0_C, 2673 0, 0, 0, 0, 2674 /* IP8_10_9 [2] */ 2675 FN_VI0_DATA2_VI0_B2, FN_DU1_DG4, FN_RX0_C, 0, 2676 /* IP8_8_6 [3] */ 2677 FN_VI0_DATA1_VI0_B1, FN_DU1_DG3, FN_IRQ3_B, FN_TX3_D, 2678 0, 0, 0, 0, 2679 /* IP8_5_3 [3] */ 2680 FN_VI0_DATA0_VI0_B0, FN_DU1_DG2, FN_IRQ2_B, FN_RX3_D, 2681 0, 0, 0, 0, 2682 /* IP8_2_0 [3] */ 2683 FN_VI0_VSYNC, FN_SD2_WP_B, FN_VI1_DATA3, FN_DU1_DR3, 2684 0, FN_HSPI_TX1_A, FN_TX3_B, 0, 2685 } 2686 }, 2687 { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32, 2688 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { 2689 /* IP9_31 [1] */ 2690 0, 0, 2691 /* IP9_30 [1] */ 2692 0, 0, 2693 /* IP9_29_27 [3] */ 2694 FN_VI1_DATA11_A, FN_DU1_EXHSYNC_DU1_HSYNC, 2695 FN_ETH_RXD1, FN_FMIN_C, 2696 0, FN_RX2_D, 2697 FN_SCL2_C, 0, 2698 /* IP9_26_24 [3] */ 2699 FN_VI1_DATA10_A, FN_DU1_DOTCLKOUT, 2700 FN_ETH_RXD0, FN_BPFCLK_C, 2701 0, FN_TX2_D, 2702 FN_SDA2_C, 0, 2703 /* IP9_23_21 [3] */ 2704 FN_VI0_R5_A, 0, FN_ETH_RX_ER, FN_FMCLK_C, 2705 FN_IERX, FN_RX2_C, 0, 0, 2706 /* IP9_20_18 [3] */ 2707 FN_VI0_R4_A, FN_ETH_TX_EN, 0, 0, 2708 FN_IETX, FN_TX2_C, 0, 0, 2709 /* IP9_17_15 [3] */ 2710 FN_VI0_R3_A, FN_ETH_CRS_DV, 0, FN_IECLK, 2711 FN_SCK2_C, 0, 0, 0, 2712 /* IP9_14_12 [3] */ 2713 FN_VI0_R2_A, FN_VI1_DATA9, FN_DU1_DB7, FN_ETH_TXD1, 2714 0, FN_PWM3, 0, 0, 2715 /* IP9_11_9 [3] */ 2716 FN_VI0_R1_A, FN_VI1_DATA8, FN_DU1_DB6, FN_ETH_TXD0, 2717 0, FN_PWM2, FN_TCLK1, 0, 2718 /* IP9_8_6 [3] */ 2719 FN_VI0_R0_A, FN_VI1_CLK, FN_ETH_REF_CLK, FN_DU1_DOTCLKIN, 2720 0, 0, 0, 0, 2721 /* IP9_5_3 [3] */ 2722 FN_VI0_G5, FN_SD2_DAT1_B, FN_VI1_DATA7, FN_DU1_DR7, 2723 0, FN_HCTS1_B, 0, 0, 2724 /* IP9_2_0 [3] */ 2725 FN_VI0_G4, FN_SD2_DAT0_B, FN_VI1_DATA6, FN_DU1_DR6, 2726 0, FN_HRTS1_B, 0, 0, 2727 } 2728 }, 2729 { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32, 2730 1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 4, 3, 3, 3) { 2731 2732 /* IP10_31 [1] */ 2733 0, 0, 2734 /* IP10_30 [1] */ 2735 0, 0, 2736 /* IP10_29 [1] */ 2737 0, 0, 2738 /* IP10_28 [1] */ 2739 0, 0, 2740 /* IP10_27 [1] */ 2741 0, 0, 2742 /* IP10_26 [1] */ 2743 0, 0, 2744 /* IP10_25 [1] */ 2745 0, 0, 2746 /* IP10_24_22 [3] */ 2747 FN_SD2_WP_A, FN_VI1_DATA15, FN_EX_WAIT2_B, FN_DACK0_B, 2748 FN_HSPI_TX2_B, FN_CAN_CLK_C, 0, 0, 2749 /* IP10_21_19 [3] */ 2750 FN_SD2_CD_A, FN_VI1_DATA14, FN_EX_WAIT1_B, FN_DREQ0_B, 2751 FN_HSPI_RX2_B, FN_REMOCON_A, 0, 0, 2752 /* IP10_18_16 [3] */ 2753 FN_SD2_DAT3_A, FN_VI1_DATA13, FN_DACK2_B, FN_ATAG1, 2754 FN_HSPI_CS2_B, FN_GPSIN_B, 0, 0, 2755 /* IP10_15_13 [3] */ 2756 FN_SD2_DAT2_A, FN_VI1_DATA12, FN_DREQ2_B, FN_ATADIR1, 2757 FN_HSPI_CLK2_B, FN_GPSCLK_B, 0, 0, 2758 /* IP10_12_9 [4] */ 2759 FN_SD2_DAT1_A, FN_DU1_CDE, FN_ATACS11, FN_DACK1_B, 2760 FN_ETH_MAGIC, FN_CAN1_TX_A, 0, FN_PWM6, 2761 0, 0, 0, 0, 2762 0, 0, 0, 0, 2763 /* IP10_8_6 [3] */ 2764 FN_SD2_DAT0_A, FN_DU1_DISP, FN_ATACS01, FN_DREQ1_B, 2765 FN_ETH_LINK, FN_CAN1_RX_A, 0, 0, 2766 /* IP10_5_3 [3] */ 2767 FN_SD2_CMD_A, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 2768 FN_ATAWR1, FN_ETH_MDIO, 2769 FN_SCL1_B, 0, 2770 0, 0, 2771 /* IP10_2_0 [3] */ 2772 FN_SD2_CLK_A, FN_DU1_EXVSYNC_DU1_VSYNC, 2773 FN_ATARD1, FN_ETH_MDC, 2774 FN_SDA1_B, 0, 2775 0, 0, 2776 } 2777 }, 2778 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xfffc0050, 32, 2779 1, 1, 2, 2, 3, 2, 2, 1, 1, 1, 1, 2, 2780 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) { 2781 2782 /* SEL 31 [1] */ 2783 0, 0, 2784 /* SEL_30 (SCIF5) [1] */ 2785 FN_SEL_SCIF5_A, FN_SEL_SCIF5_B, 2786 /* SEL_29_28 (SCIF4) [2] */ 2787 FN_SEL_SCIF4_A, FN_SEL_SCIF4_B, 2788 FN_SEL_SCIF4_C, 0, 2789 /* SEL_27_26 (SCIF3) [2] */ 2790 FN_SEL_SCIF3_A, FN_SEL_SCIF3_B, 2791 FN_SEL_SCIF3_C, FN_SEL_SCIF3_D, 2792 /* SEL_25_23 (SCIF2) [3] */ 2793 FN_SEL_SCIF2_A, FN_SEL_SCIF2_B, 2794 FN_SEL_SCIF2_C, FN_SEL_SCIF2_D, 2795 FN_SEL_SCIF2_E, 0, 2796 0, 0, 2797 /* SEL_22_21 (SCIF1) [2] */ 2798 FN_SEL_SCIF1_A, FN_SEL_SCIF1_B, 2799 FN_SEL_SCIF1_C, FN_SEL_SCIF1_D, 2800 /* SEL_20_19 (SCIF0) [2] */ 2801 FN_SEL_SCIF0_A, FN_SEL_SCIF0_B, 2802 FN_SEL_SCIF0_C, FN_SEL_SCIF0_D, 2803 /* SEL_18 [1] */ 2804 0, 0, 2805 /* SEL_17 (SSI2) [1] */ 2806 FN_SEL_SSI2_A, FN_SEL_SSI2_B, 2807 /* SEL_16 (SSI1) [1] */ 2808 FN_SEL_SSI1_A, FN_SEL_SSI1_B, 2809 /* SEL_15 (VI1) [1] */ 2810 FN_SEL_VI1_A, FN_SEL_VI1_B, 2811 /* SEL_14_13 (VI0) [2] */ 2812 FN_SEL_VI0_A, FN_SEL_VI0_B, 2813 FN_SEL_VI0_C, FN_SEL_VI0_D, 2814 /* SEL_12 [1] */ 2815 0, 0, 2816 /* SEL_11 (SD2) [1] */ 2817 FN_SEL_SD2_A, FN_SEL_SD2_B, 2818 /* SEL_10 (SD1) [1] */ 2819 FN_SEL_SD1_A, FN_SEL_SD1_B, 2820 /* SEL_9 (IRQ3) [1] */ 2821 FN_SEL_IRQ3_A, FN_SEL_IRQ3_B, 2822 /* SEL_8_7 (IRQ2) [2] */ 2823 FN_SEL_IRQ2_A, FN_SEL_IRQ2_B, 2824 FN_SEL_IRQ2_C, 0, 2825 /* SEL_6 (IRQ1) [1] */ 2826 FN_SEL_IRQ1_A, FN_SEL_IRQ1_B, 2827 /* SEL_5 [1] */ 2828 0, 0, 2829 /* SEL_4 (DREQ2) [1] */ 2830 FN_SEL_DREQ2_A, FN_SEL_DREQ2_B, 2831 /* SEL_3 (DREQ1) [1] */ 2832 FN_SEL_DREQ1_A, FN_SEL_DREQ1_B, 2833 /* SEL_2 (DREQ0) [1] */ 2834 FN_SEL_DREQ0_A, FN_SEL_DREQ0_B, 2835 /* SEL_1 (WAIT2) [1] */ 2836 FN_SEL_WAIT2_A, FN_SEL_WAIT2_B, 2837 /* SEL_0 (WAIT1) [1] */ 2838 FN_SEL_WAIT1_A, FN_SEL_WAIT1_B, 2839 } 2840 }, 2841 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xfffc0054, 32, 2842 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 2843 1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1) { 2844 2845 /* SEL_31 [1] */ 2846 0, 0, 2847 /* SEL_30 [1] */ 2848 0, 0, 2849 /* SEL_29 [1] */ 2850 0, 0, 2851 /* SEL_28 [1] */ 2852 0, 0, 2853 /* SEL_27 (CAN1) [1] */ 2854 FN_SEL_CAN1_A, FN_SEL_CAN1_B, 2855 /* SEL_26 (CAN0) [1] */ 2856 FN_SEL_CAN0_A, FN_SEL_CAN0_B, 2857 /* SEL_25_24 (CANCLK) [2] */ 2858 FN_SEL_CANCLK_A, FN_SEL_CANCLK_B, 2859 FN_SEL_CANCLK_C, FN_SEL_CANCLK_D, 2860 /* SEL_23 (HSCIF1) [1] */ 2861 FN_SEL_HSCIF1_A, FN_SEL_HSCIF1_B, 2862 /* SEL_22 (HSCIF0) [1] */ 2863 FN_SEL_HSCIF0_A, FN_SEL_HSCIF0_B, 2864 /* SEL_21 [1] */ 2865 0, 0, 2866 /* SEL_20 [1] */ 2867 0, 0, 2868 /* SEL_19 [1] */ 2869 0, 0, 2870 /* SEL_18 [1] */ 2871 0, 0, 2872 /* SEL_17 [1] */ 2873 0, 0, 2874 /* SEL_16 [1] */ 2875 0, 0, 2876 /* SEL_15 [1] */ 2877 0, 0, 2878 /* SEL_14_13 (REMOCON) [2] */ 2879 FN_SEL_REMOCON_A, FN_SEL_REMOCON_B, 2880 FN_SEL_REMOCON_C, 0, 2881 /* SEL_12_11 (FM) [2] */ 2882 FN_SEL_FM_A, FN_SEL_FM_B, 2883 FN_SEL_FM_C, FN_SEL_FM_D, 2884 /* SEL_10_9 (GPS) [2] */ 2885 FN_SEL_GPS_A, FN_SEL_GPS_B, 2886 FN_SEL_GPS_C, 0, 2887 /* SEL_8 (TSIF0) [1] */ 2888 FN_SEL_TSIF0_A, FN_SEL_TSIF0_B, 2889 /* SEL_7 (HSPI2) [1] */ 2890 FN_SEL_HSPI2_A, FN_SEL_HSPI2_B, 2891 /* SEL_6 (HSPI1) [1] */ 2892 FN_SEL_HSPI1_A, FN_SEL_HSPI1_B, 2893 /* SEL_5 (HSPI0) [1] */ 2894 FN_SEL_HSPI0_A, FN_SEL_HSPI0_B, 2895 /* SEL_4_3 (I2C3) [2] */ 2896 FN_SEL_I2C3_A, FN_SEL_I2C3_B, 2897 FN_SEL_I2C3_C, 0, 2898 /* SEL_2_1 (I2C2) [2] */ 2899 FN_SEL_I2C2_A, FN_SEL_I2C2_B, 2900 FN_SEL_I2C2_C, 0, 2901 /* SEL_0 (I2C1) [1] */ 2902 FN_SEL_I2C1_A, FN_SEL_I2C1_B, 2903 } 2904 }, 2905 { }, 2906 }; 2907 2908 const struct sh_pfc_soc_info r8a7778_pinmux_info = { 2909 .name = "r8a7778_pfc", 2910 2911 .unlock_reg = 0xfffc0000, /* PMMR */ 2912 2913 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 2914 2915 .pins = pinmux_pins, 2916 .nr_pins = ARRAY_SIZE(pinmux_pins), 2917 2918 .groups = pinmux_groups, 2919 .nr_groups = ARRAY_SIZE(pinmux_groups), 2920 2921 .functions = pinmux_functions, 2922 .nr_functions = ARRAY_SIZE(pinmux_functions), 2923 2924 .cfg_regs = pinmux_config_regs, 2925 2926 .gpio_data = pinmux_data, 2927 .gpio_data_size = ARRAY_SIZE(pinmux_data), 2928 }; 2929