1 /*
2 * sh7372 processor support - PFC hardware block
3 *
4 * Copyright (C) 2010 Kuninori Morimoto <morimoto.kuninori@renesas.com>
5 *
6 * Based on
7 * sh7367 processor support - PFC hardware block
8 * Copyright (C) 2010 Magnus Damm
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23 #include <linux/io.h>
24 #include <linux/kernel.h>
25 #include <linux/pinctrl/pinconf-generic.h>
26 #include <linux/sh_intc.h>
27
28 #include "core.h"
29 #include "sh_pfc.h"
30
31 #define CPU_ALL_PORT(fn, pfx, sfx) \
32 PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
33 PORT_10(100, fn, pfx##10, sfx), PORT_10(110, fn, pfx##11, sfx), \
34 PORT_10(120, fn, pfx##12, sfx), PORT_10(130, fn, pfx##13, sfx), \
35 PORT_10(140, fn, pfx##14, sfx), PORT_10(150, fn, pfx##15, sfx), \
36 PORT_10(160, fn, pfx##16, sfx), PORT_10(170, fn, pfx##17, sfx), \
37 PORT_10(180, fn, pfx##18, sfx), PORT_1(190, fn, pfx##190, sfx)
38
39 #define IRQC_PIN_MUX(irq, pin) \
40 static const unsigned int intc_irq##irq##_pins[] = { \
41 pin, \
42 }; \
43 static const unsigned int intc_irq##irq##_mux[] = { \
44 IRQ##irq##_MARK, \
45 }
46
47 #define IRQC_PINS_MUX(irq, pin0, pin1) \
48 static const unsigned int intc_irq##irq##_0_pins[] = { \
49 pin0, \
50 }; \
51 static const unsigned int intc_irq##irq##_0_mux[] = { \
52 IRQ##irq##_##pin0##_MARK, \
53 }; \
54 static const unsigned int intc_irq##irq##_1_pins[] = { \
55 pin1, \
56 }; \
57 static const unsigned int intc_irq##irq##_1_mux[] = { \
58 IRQ##irq##_##pin1##_MARK, \
59 }
60
61 enum {
62 PINMUX_RESERVED = 0,
63
64 /* PORT0_DATA -> PORT190_DATA */
65 PINMUX_DATA_BEGIN,
66 PORT_ALL(DATA),
67 PINMUX_DATA_END,
68
69 /* PORT0_IN -> PORT190_IN */
70 PINMUX_INPUT_BEGIN,
71 PORT_ALL(IN),
72 PINMUX_INPUT_END,
73
74 /* PORT0_OUT -> PORT190_OUT */
75 PINMUX_OUTPUT_BEGIN,
76 PORT_ALL(OUT),
77 PINMUX_OUTPUT_END,
78
79 PINMUX_FUNCTION_BEGIN,
80 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT190_FN_IN */
81 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT190_FN_OUT */
82 PORT_ALL(FN0), /* PORT0_FN0 -> PORT190_FN0 */
83 PORT_ALL(FN1), /* PORT0_FN1 -> PORT190_FN1 */
84 PORT_ALL(FN2), /* PORT0_FN2 -> PORT190_FN2 */
85 PORT_ALL(FN3), /* PORT0_FN3 -> PORT190_FN3 */
86 PORT_ALL(FN4), /* PORT0_FN4 -> PORT190_FN4 */
87 PORT_ALL(FN5), /* PORT0_FN5 -> PORT190_FN5 */
88 PORT_ALL(FN6), /* PORT0_FN6 -> PORT190_FN6 */
89 PORT_ALL(FN7), /* PORT0_FN7 -> PORT190_FN7 */
90
91 MSEL1CR_31_0, MSEL1CR_31_1,
92 MSEL1CR_30_0, MSEL1CR_30_1,
93 MSEL1CR_29_0, MSEL1CR_29_1,
94 MSEL1CR_28_0, MSEL1CR_28_1,
95 MSEL1CR_27_0, MSEL1CR_27_1,
96 MSEL1CR_26_0, MSEL1CR_26_1,
97 MSEL1CR_16_0, MSEL1CR_16_1,
98 MSEL1CR_15_0, MSEL1CR_15_1,
99 MSEL1CR_14_0, MSEL1CR_14_1,
100 MSEL1CR_13_0, MSEL1CR_13_1,
101 MSEL1CR_12_0, MSEL1CR_12_1,
102 MSEL1CR_9_0, MSEL1CR_9_1,
103 MSEL1CR_8_0, MSEL1CR_8_1,
104 MSEL1CR_7_0, MSEL1CR_7_1,
105 MSEL1CR_6_0, MSEL1CR_6_1,
106 MSEL1CR_4_0, MSEL1CR_4_1,
107 MSEL1CR_3_0, MSEL1CR_3_1,
108 MSEL1CR_2_0, MSEL1CR_2_1,
109 MSEL1CR_0_0, MSEL1CR_0_1,
110
111 MSEL3CR_27_0, MSEL3CR_27_1,
112 MSEL3CR_26_0, MSEL3CR_26_1,
113 MSEL3CR_21_0, MSEL3CR_21_1,
114 MSEL3CR_20_0, MSEL3CR_20_1,
115 MSEL3CR_15_0, MSEL3CR_15_1,
116 MSEL3CR_9_0, MSEL3CR_9_1,
117 MSEL3CR_6_0, MSEL3CR_6_1,
118
119 MSEL4CR_19_0, MSEL4CR_19_1,
120 MSEL4CR_18_0, MSEL4CR_18_1,
121 MSEL4CR_17_0, MSEL4CR_17_1,
122 MSEL4CR_16_0, MSEL4CR_16_1,
123 MSEL4CR_15_0, MSEL4CR_15_1,
124 MSEL4CR_14_0, MSEL4CR_14_1,
125 MSEL4CR_10_0, MSEL4CR_10_1,
126 MSEL4CR_6_0, MSEL4CR_6_1,
127 MSEL4CR_4_0, MSEL4CR_4_1,
128 MSEL4CR_1_0, MSEL4CR_1_1,
129 PINMUX_FUNCTION_END,
130
131 PINMUX_MARK_BEGIN,
132
133 /* IRQ */
134 IRQ0_6_MARK, IRQ0_162_MARK, IRQ1_MARK, IRQ2_4_MARK,
135 IRQ2_5_MARK, IRQ3_8_MARK, IRQ3_16_MARK, IRQ4_17_MARK,
136 IRQ4_163_MARK, IRQ5_MARK, IRQ6_39_MARK, IRQ6_164_MARK,
137 IRQ7_40_MARK, IRQ7_167_MARK, IRQ8_41_MARK, IRQ8_168_MARK,
138 IRQ9_42_MARK, IRQ9_169_MARK, IRQ10_MARK, IRQ11_MARK,
139 IRQ12_80_MARK, IRQ12_137_MARK, IRQ13_81_MARK, IRQ13_145_MARK,
140 IRQ14_82_MARK, IRQ14_146_MARK, IRQ15_83_MARK, IRQ15_147_MARK,
141 IRQ16_84_MARK, IRQ16_170_MARK, IRQ17_MARK, IRQ18_MARK,
142 IRQ19_MARK, IRQ20_MARK, IRQ21_MARK, IRQ22_MARK,
143 IRQ23_MARK, IRQ24_MARK, IRQ25_MARK, IRQ26_121_MARK,
144 IRQ26_172_MARK, IRQ27_122_MARK, IRQ27_180_MARK, IRQ28_123_MARK,
145 IRQ28_181_MARK, IRQ29_129_MARK, IRQ29_182_MARK, IRQ30_130_MARK,
146 IRQ30_183_MARK, IRQ31_138_MARK, IRQ31_184_MARK,
147
148 /* MSIOF0 */
149 MSIOF0_TSYNC_MARK, MSIOF0_TSCK_MARK, MSIOF0_RXD_MARK,
150 MSIOF0_RSCK_MARK, MSIOF0_RSYNC_MARK, MSIOF0_MCK0_MARK,
151 MSIOF0_MCK1_MARK, MSIOF0_SS1_MARK, MSIOF0_SS2_MARK,
152 MSIOF0_TXD_MARK,
153
154 /* MSIOF1 */
155 MSIOF1_TSCK_39_MARK, MSIOF1_TSYNC_40_MARK,
156 MSIOF1_TSCK_88_MARK, MSIOF1_TSYNC_89_MARK,
157 MSIOF1_TXD_41_MARK, MSIOF1_RXD_42_MARK,
158 MSIOF1_TXD_90_MARK, MSIOF1_RXD_91_MARK,
159 MSIOF1_SS1_43_MARK, MSIOF1_SS2_44_MARK,
160 MSIOF1_SS1_92_MARK, MSIOF1_SS2_93_MARK,
161 MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK,
162 MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
163
164 /* MSIOF2 */
165 MSIOF2_RSCK_MARK, MSIOF2_RSYNC_MARK, MSIOF2_MCK0_MARK,
166 MSIOF2_MCK1_MARK, MSIOF2_SS1_MARK, MSIOF2_SS2_MARK,
167 MSIOF2_TSYNC_MARK, MSIOF2_TSCK_MARK, MSIOF2_RXD_MARK,
168 MSIOF2_TXD_MARK,
169
170 /* BBIF1 */
171 BBIF1_RXD_MARK, BBIF1_TSYNC_MARK, BBIF1_TSCK_MARK,
172 BBIF1_TXD_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK,
173 BBIF1_FLOW_MARK, BB_RX_FLOW_N_MARK,
174
175 /* BBIF2 */
176 BBIF2_TSCK1_MARK, BBIF2_TSYNC1_MARK,
177 BBIF2_TXD1_MARK, BBIF2_RXD_MARK,
178
179 /* FSI */
180 FSIACK_MARK, FSIBCK_MARK, FSIAILR_MARK, FSIAIBT_MARK,
181 FSIAISLD_MARK, FSIAOMC_MARK, FSIAOLR_MARK, FSIAOBT_MARK,
182 FSIAOSLD_MARK, FSIASPDIF_11_MARK, FSIASPDIF_15_MARK,
183
184 /* FMSI */
185 FMSOCK_MARK, FMSOOLR_MARK, FMSIOLR_MARK, FMSOOBT_MARK,
186 FMSIOBT_MARK, FMSOSLD_MARK, FMSOILR_MARK, FMSIILR_MARK,
187 FMSOIBT_MARK, FMSIIBT_MARK, FMSISLD_MARK, FMSICK_MARK,
188
189 /* SCIFA0 */
190 SCIFA0_TXD_MARK, SCIFA0_RXD_MARK, SCIFA0_SCK_MARK,
191 SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
192
193 /* SCIFA1 */
194 SCIFA1_TXD_MARK, SCIFA1_RXD_MARK, SCIFA1_SCK_MARK,
195 SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
196
197 /* SCIFA2 */
198 SCIFA2_CTS1_MARK, SCIFA2_RTS1_MARK, SCIFA2_TXD1_MARK,
199 SCIFA2_RXD1_MARK, SCIFA2_SCK1_MARK,
200
201 /* SCIFA3 */
202 SCIFA3_CTS_43_MARK, SCIFA3_CTS_140_MARK, SCIFA3_RTS_44_MARK,
203 SCIFA3_RTS_141_MARK, SCIFA3_SCK_MARK, SCIFA3_TXD_MARK,
204 SCIFA3_RXD_MARK,
205
206 /* SCIFA4 */
207 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
208
209 /* SCIFA5 */
210 SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
211
212 /* SCIFB */
213 SCIFB_SCK_MARK, SCIFB_RTS_MARK, SCIFB_CTS_MARK,
214 SCIFB_TXD_MARK, SCIFB_RXD_MARK,
215
216 /* CEU */
217 VIO_HD_MARK, VIO_CKO1_MARK, VIO_CKO2_MARK, VIO_VD_MARK,
218 VIO_CLK_MARK, VIO_FIELD_MARK, VIO_CKO_MARK,
219 VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK, VIO_D3_MARK,
220 VIO_D4_MARK, VIO_D5_MARK, VIO_D6_MARK, VIO_D7_MARK,
221 VIO_D8_MARK, VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK,
222 VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK, VIO_D15_MARK,
223
224 /* USB0 */
225 IDIN_0_MARK, EXTLP_0_MARK, OVCN2_0_MARK, PWEN_0_MARK,
226 OVCN_0_MARK, VBUS0_0_MARK,
227
228 /* USB1 */
229 IDIN_1_18_MARK, IDIN_1_113_MARK,
230 PWEN_1_115_MARK, PWEN_1_138_MARK,
231 OVCN_1_114_MARK, OVCN_1_162_MARK,
232 EXTLP_1_MARK, OVCN2_1_MARK,
233 VBUS0_1_MARK,
234
235 /* GPIO */
236 GPI0_MARK, GPI1_MARK, GPO0_MARK, GPO1_MARK,
237
238 /* BSC */
239 BS_MARK, WE1_MARK,
240 CKO_MARK, WAIT_MARK, RDWR_MARK,
241
242 A0_MARK, A1_MARK, A2_MARK, A3_MARK,
243 A6_MARK, A7_MARK, A8_MARK, A9_MARK,
244 A10_MARK, A11_MARK, A12_MARK, A13_MARK,
245 A14_MARK, A15_MARK, A16_MARK, A17_MARK,
246 A18_MARK, A19_MARK, A20_MARK, A21_MARK,
247 A22_MARK, A23_MARK, A24_MARK, A25_MARK,
248 A26_MARK,
249
250 CS0_MARK, CS2_MARK, CS4_MARK,
251 CS5A_MARK, CS5B_MARK, CS6A_MARK,
252
253 /* BSC/FLCTL */
254 RD_FSC_MARK, WE0_FWE_MARK, A4_FOE_MARK, A5_FCDE_MARK,
255 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
256 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
257 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
258 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
259
260 /* MMCIF(1) */
261 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
262 MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
263 MMCCMD0_MARK, MMCCLK0_MARK,
264
265 /* MMCIF(2) */
266 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
267 MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
268 MMCCLK1_MARK, MMCCMD1_MARK,
269
270 /* SPU2 */
271 VINT_I_MARK,
272
273 /* FLCTL */
274 FCE1_MARK, FCE0_MARK, FRB_MARK,
275
276 /* HSI */
277 GP_RX_FLAG_MARK, GP_RX_DATA_MARK, GP_TX_READY_MARK,
278 GP_RX_WAKE_MARK, MP_TX_FLAG_MARK, MP_TX_DATA_MARK,
279 MP_RX_READY_MARK, MP_TX_WAKE_MARK,
280
281 /* MFI */
282 MFIv6_MARK,
283 MFIv4_MARK,
284
285 MEMC_CS0_MARK, MEMC_BUSCLK_MEMC_A0_MARK,
286 MEMC_CS1_MEMC_A1_MARK, MEMC_ADV_MEMC_DREQ0_MARK,
287 MEMC_WAIT_MEMC_DREQ1_MARK, MEMC_NOE_MARK,
288 MEMC_NWE_MARK, MEMC_INT_MARK,
289
290 MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK,
291 MEMC_AD3_MARK, MEMC_AD4_MARK, MEMC_AD5_MARK,
292 MEMC_AD6_MARK, MEMC_AD7_MARK, MEMC_AD8_MARK,
293 MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK,
294 MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK,
295 MEMC_AD15_MARK,
296
297 /* SIM */
298 SIM_RST_MARK, SIM_CLK_MARK, SIM_D_MARK,
299
300 /* TPU */
301 TPU0TO0_MARK, TPU0TO1_MARK,
302 TPU0TO2_93_MARK, TPU0TO2_99_MARK,
303 TPU0TO3_MARK,
304
305 /* I2C2 */
306 I2C_SCL2_MARK, I2C_SDA2_MARK,
307
308 /* I2C3(1) */
309 I2C_SCL3_MARK, I2C_SDA3_MARK,
310
311 /* I2C3(2) */
312 I2C_SCL3S_MARK, I2C_SDA3S_MARK,
313
314 /* I2C4(2) */
315 I2C_SCL4_MARK, I2C_SDA4_MARK,
316
317 /* I2C4(2) */
318 I2C_SCL4S_MARK, I2C_SDA4S_MARK,
319
320 /* KEYSC */
321 KEYOUT0_MARK, KEYIN0_121_MARK, KEYIN0_136_MARK,
322 KEYOUT1_MARK, KEYIN1_122_MARK, KEYIN1_135_MARK,
323 KEYOUT2_MARK, KEYIN2_123_MARK, KEYIN2_134_MARK,
324 KEYOUT3_MARK, KEYIN3_124_MARK, KEYIN3_133_MARK,
325 KEYOUT4_MARK, KEYIN4_MARK,
326 KEYOUT5_MARK, KEYIN5_MARK,
327 KEYOUT6_MARK, KEYIN6_MARK,
328 KEYOUT7_MARK, KEYIN7_MARK,
329
330 /* LCDC */
331 LCDC0_SELECT_MARK,
332 LCDC1_SELECT_MARK,
333 LCDHSYN_MARK, LCDCS_MARK, LCDVSYN_MARK, LCDDCK_MARK,
334 LCDWR_MARK, LCDRD_MARK, LCDDISP_MARK, LCDRS_MARK,
335 LCDLCLK_MARK, LCDDON_MARK,
336
337 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
338 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
339 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
340 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
341 LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
342 LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
343
344 /* IRDA */
345 IRDA_OUT_MARK, IRDA_IN_MARK, IRDA_FIRSEL_MARK,
346 IROUT_139_MARK, IROUT_140_MARK,
347
348 /* TSIF1 */
349 TS0_1SELECT_MARK,
350 TS0_2SELECT_MARK,
351 TS1_1SELECT_MARK,
352 TS1_2SELECT_MARK,
353
354 TS_SPSYNC1_MARK, TS_SDAT1_MARK,
355 TS_SDEN1_MARK, TS_SCK1_MARK,
356
357 /* TSIF2 */
358 TS_SPSYNC2_MARK, TS_SDAT2_MARK,
359 TS_SDEN2_MARK, TS_SCK2_MARK,
360
361 /* HDMI */
362 HDMI_HPD_MARK, HDMI_CEC_MARK,
363
364 /* SDHI0 */
365 SDHICLK0_MARK, SDHICD0_MARK,
366 SDHICMD0_MARK, SDHIWP0_MARK,
367 SDHID0_0_MARK, SDHID0_1_MARK,
368 SDHID0_2_MARK, SDHID0_3_MARK,
369
370 /* SDHI1 */
371 SDHICLK1_MARK, SDHICMD1_MARK, SDHID1_0_MARK,
372 SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
373
374 /* SDHI2 */
375 SDHICLK2_MARK, SDHICMD2_MARK, SDHID2_0_MARK,
376 SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
377
378 /* SDENC */
379 SDENC_CPG_MARK,
380 SDENC_DV_CLKI_MARK,
381
382 PINMUX_MARK_END,
383 };
384
385 static const u16 pinmux_data[] = {
386 PINMUX_DATA_ALL(),
387
388 /* IRQ */
389 PINMUX_DATA(IRQ0_6_MARK, PORT6_FN0, MSEL1CR_0_0),
390 PINMUX_DATA(IRQ0_162_MARK, PORT162_FN0, MSEL1CR_0_1),
391 PINMUX_DATA(IRQ1_MARK, PORT12_FN0),
392 PINMUX_DATA(IRQ2_4_MARK, PORT4_FN0, MSEL1CR_2_0),
393 PINMUX_DATA(IRQ2_5_MARK, PORT5_FN0, MSEL1CR_2_1),
394 PINMUX_DATA(IRQ3_8_MARK, PORT8_FN0, MSEL1CR_3_0),
395 PINMUX_DATA(IRQ3_16_MARK, PORT16_FN0, MSEL1CR_3_1),
396 PINMUX_DATA(IRQ4_17_MARK, PORT17_FN0, MSEL1CR_4_0),
397 PINMUX_DATA(IRQ4_163_MARK, PORT163_FN0, MSEL1CR_4_1),
398 PINMUX_DATA(IRQ5_MARK, PORT18_FN0),
399 PINMUX_DATA(IRQ6_39_MARK, PORT39_FN0, MSEL1CR_6_0),
400 PINMUX_DATA(IRQ6_164_MARK, PORT164_FN0, MSEL1CR_6_1),
401 PINMUX_DATA(IRQ7_40_MARK, PORT40_FN0, MSEL1CR_7_1),
402 PINMUX_DATA(IRQ7_167_MARK, PORT167_FN0, MSEL1CR_7_0),
403 PINMUX_DATA(IRQ8_41_MARK, PORT41_FN0, MSEL1CR_8_1),
404 PINMUX_DATA(IRQ8_168_MARK, PORT168_FN0, MSEL1CR_8_0),
405 PINMUX_DATA(IRQ9_42_MARK, PORT42_FN0, MSEL1CR_9_0),
406 PINMUX_DATA(IRQ9_169_MARK, PORT169_FN0, MSEL1CR_9_1),
407 PINMUX_DATA(IRQ10_MARK, PORT65_FN0, MSEL1CR_9_1),
408 PINMUX_DATA(IRQ11_MARK, PORT67_FN0),
409 PINMUX_DATA(IRQ12_80_MARK, PORT80_FN0, MSEL1CR_12_0),
410 PINMUX_DATA(IRQ12_137_MARK, PORT137_FN0, MSEL1CR_12_1),
411 PINMUX_DATA(IRQ13_81_MARK, PORT81_FN0, MSEL1CR_13_0),
412 PINMUX_DATA(IRQ13_145_MARK, PORT145_FN0, MSEL1CR_13_1),
413 PINMUX_DATA(IRQ14_82_MARK, PORT82_FN0, MSEL1CR_14_0),
414 PINMUX_DATA(IRQ14_146_MARK, PORT146_FN0, MSEL1CR_14_1),
415 PINMUX_DATA(IRQ15_83_MARK, PORT83_FN0, MSEL1CR_15_0),
416 PINMUX_DATA(IRQ15_147_MARK, PORT147_FN0, MSEL1CR_15_1),
417 PINMUX_DATA(IRQ16_84_MARK, PORT84_FN0, MSEL1CR_16_0),
418 PINMUX_DATA(IRQ16_170_MARK, PORT170_FN0, MSEL1CR_16_1),
419 PINMUX_DATA(IRQ17_MARK, PORT85_FN0),
420 PINMUX_DATA(IRQ18_MARK, PORT86_FN0),
421 PINMUX_DATA(IRQ19_MARK, PORT87_FN0),
422 PINMUX_DATA(IRQ20_MARK, PORT92_FN0),
423 PINMUX_DATA(IRQ21_MARK, PORT93_FN0),
424 PINMUX_DATA(IRQ22_MARK, PORT94_FN0),
425 PINMUX_DATA(IRQ23_MARK, PORT95_FN0),
426 PINMUX_DATA(IRQ24_MARK, PORT112_FN0),
427 PINMUX_DATA(IRQ25_MARK, PORT119_FN0),
428 PINMUX_DATA(IRQ26_121_MARK, PORT121_FN0, MSEL1CR_26_1),
429 PINMUX_DATA(IRQ26_172_MARK, PORT172_FN0, MSEL1CR_26_0),
430 PINMUX_DATA(IRQ27_122_MARK, PORT122_FN0, MSEL1CR_27_1),
431 PINMUX_DATA(IRQ27_180_MARK, PORT180_FN0, MSEL1CR_27_0),
432 PINMUX_DATA(IRQ28_123_MARK, PORT123_FN0, MSEL1CR_28_1),
433 PINMUX_DATA(IRQ28_181_MARK, PORT181_FN0, MSEL1CR_28_0),
434 PINMUX_DATA(IRQ29_129_MARK, PORT129_FN0, MSEL1CR_29_1),
435 PINMUX_DATA(IRQ29_182_MARK, PORT182_FN0, MSEL1CR_29_0),
436 PINMUX_DATA(IRQ30_130_MARK, PORT130_FN0, MSEL1CR_30_1),
437 PINMUX_DATA(IRQ30_183_MARK, PORT183_FN0, MSEL1CR_30_0),
438 PINMUX_DATA(IRQ31_138_MARK, PORT138_FN0, MSEL1CR_31_1),
439 PINMUX_DATA(IRQ31_184_MARK, PORT184_FN0, MSEL1CR_31_0),
440
441 /* Function 1 */
442 PINMUX_DATA(BBIF2_TSCK1_MARK, PORT0_FN1),
443 PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT1_FN1),
444 PINMUX_DATA(BBIF2_TXD1_MARK, PORT2_FN1),
445 PINMUX_DATA(BBIF2_RXD_MARK, PORT3_FN1),
446 PINMUX_DATA(FSIACK_MARK, PORT4_FN1),
447 PINMUX_DATA(FSIAILR_MARK, PORT5_FN1),
448 PINMUX_DATA(FSIAIBT_MARK, PORT6_FN1),
449 PINMUX_DATA(FSIAISLD_MARK, PORT7_FN1),
450 PINMUX_DATA(FSIAOMC_MARK, PORT8_FN1),
451 PINMUX_DATA(FSIAOLR_MARK, PORT9_FN1),
452 PINMUX_DATA(FSIAOBT_MARK, PORT10_FN1),
453 PINMUX_DATA(FSIAOSLD_MARK, PORT11_FN1),
454 PINMUX_DATA(FMSOCK_MARK, PORT12_FN1),
455 PINMUX_DATA(FMSOOLR_MARK, PORT13_FN1),
456 PINMUX_DATA(FMSOOBT_MARK, PORT14_FN1),
457 PINMUX_DATA(FMSOSLD_MARK, PORT15_FN1),
458 PINMUX_DATA(FMSOILR_MARK, PORT16_FN1),
459 PINMUX_DATA(FMSOIBT_MARK, PORT17_FN1),
460 PINMUX_DATA(FMSISLD_MARK, PORT18_FN1),
461 PINMUX_DATA(A0_MARK, PORT19_FN1),
462 PINMUX_DATA(A1_MARK, PORT20_FN1),
463 PINMUX_DATA(A2_MARK, PORT21_FN1),
464 PINMUX_DATA(A3_MARK, PORT22_FN1),
465 PINMUX_DATA(A4_FOE_MARK, PORT23_FN1),
466 PINMUX_DATA(A5_FCDE_MARK, PORT24_FN1),
467 PINMUX_DATA(A6_MARK, PORT25_FN1),
468 PINMUX_DATA(A7_MARK, PORT26_FN1),
469 PINMUX_DATA(A8_MARK, PORT27_FN1),
470 PINMUX_DATA(A9_MARK, PORT28_FN1),
471 PINMUX_DATA(A10_MARK, PORT29_FN1),
472 PINMUX_DATA(A11_MARK, PORT30_FN1),
473 PINMUX_DATA(A12_MARK, PORT31_FN1),
474 PINMUX_DATA(A13_MARK, PORT32_FN1),
475 PINMUX_DATA(A14_MARK, PORT33_FN1),
476 PINMUX_DATA(A15_MARK, PORT34_FN1),
477 PINMUX_DATA(A16_MARK, PORT35_FN1),
478 PINMUX_DATA(A17_MARK, PORT36_FN1),
479 PINMUX_DATA(A18_MARK, PORT37_FN1),
480 PINMUX_DATA(A19_MARK, PORT38_FN1),
481 PINMUX_DATA(A20_MARK, PORT39_FN1),
482 PINMUX_DATA(A21_MARK, PORT40_FN1),
483 PINMUX_DATA(A22_MARK, PORT41_FN1),
484 PINMUX_DATA(A23_MARK, PORT42_FN1),
485 PINMUX_DATA(A24_MARK, PORT43_FN1),
486 PINMUX_DATA(A25_MARK, PORT44_FN1),
487 PINMUX_DATA(A26_MARK, PORT45_FN1),
488 PINMUX_DATA(D0_NAF0_MARK, PORT46_FN1),
489 PINMUX_DATA(D1_NAF1_MARK, PORT47_FN1),
490 PINMUX_DATA(D2_NAF2_MARK, PORT48_FN1),
491 PINMUX_DATA(D3_NAF3_MARK, PORT49_FN1),
492 PINMUX_DATA(D4_NAF4_MARK, PORT50_FN1),
493 PINMUX_DATA(D5_NAF5_MARK, PORT51_FN1),
494 PINMUX_DATA(D6_NAF6_MARK, PORT52_FN1),
495 PINMUX_DATA(D7_NAF7_MARK, PORT53_FN1),
496 PINMUX_DATA(D8_NAF8_MARK, PORT54_FN1),
497 PINMUX_DATA(D9_NAF9_MARK, PORT55_FN1),
498 PINMUX_DATA(D10_NAF10_MARK, PORT56_FN1),
499 PINMUX_DATA(D11_NAF11_MARK, PORT57_FN1),
500 PINMUX_DATA(D12_NAF12_MARK, PORT58_FN1),
501 PINMUX_DATA(D13_NAF13_MARK, PORT59_FN1),
502 PINMUX_DATA(D14_NAF14_MARK, PORT60_FN1),
503 PINMUX_DATA(D15_NAF15_MARK, PORT61_FN1),
504 PINMUX_DATA(CS0_MARK, PORT62_FN1),
505 PINMUX_DATA(CS2_MARK, PORT63_FN1),
506 PINMUX_DATA(CS4_MARK, PORT64_FN1),
507 PINMUX_DATA(CS5A_MARK, PORT65_FN1),
508 PINMUX_DATA(CS5B_MARK, PORT66_FN1),
509 PINMUX_DATA(CS6A_MARK, PORT67_FN1),
510 PINMUX_DATA(FCE0_MARK, PORT68_FN1),
511 PINMUX_DATA(RD_FSC_MARK, PORT69_FN1),
512 PINMUX_DATA(WE0_FWE_MARK, PORT70_FN1),
513 PINMUX_DATA(WE1_MARK, PORT71_FN1),
514 PINMUX_DATA(CKO_MARK, PORT72_FN1),
515 PINMUX_DATA(FRB_MARK, PORT73_FN1),
516 PINMUX_DATA(WAIT_MARK, PORT74_FN1),
517 PINMUX_DATA(RDWR_MARK, PORT75_FN1),
518 PINMUX_DATA(MEMC_AD0_MARK, PORT76_FN1),
519 PINMUX_DATA(MEMC_AD1_MARK, PORT77_FN1),
520 PINMUX_DATA(MEMC_AD2_MARK, PORT78_FN1),
521 PINMUX_DATA(MEMC_AD3_MARK, PORT79_FN1),
522 PINMUX_DATA(MEMC_AD4_MARK, PORT80_FN1),
523 PINMUX_DATA(MEMC_AD5_MARK, PORT81_FN1),
524 PINMUX_DATA(MEMC_AD6_MARK, PORT82_FN1),
525 PINMUX_DATA(MEMC_AD7_MARK, PORT83_FN1),
526 PINMUX_DATA(MEMC_AD8_MARK, PORT84_FN1),
527 PINMUX_DATA(MEMC_AD9_MARK, PORT85_FN1),
528 PINMUX_DATA(MEMC_AD10_MARK, PORT86_FN1),
529 PINMUX_DATA(MEMC_AD11_MARK, PORT87_FN1),
530 PINMUX_DATA(MEMC_AD12_MARK, PORT88_FN1),
531 PINMUX_DATA(MEMC_AD13_MARK, PORT89_FN1),
532 PINMUX_DATA(MEMC_AD14_MARK, PORT90_FN1),
533 PINMUX_DATA(MEMC_AD15_MARK, PORT91_FN1),
534 PINMUX_DATA(MEMC_CS0_MARK, PORT92_FN1),
535 PINMUX_DATA(MEMC_BUSCLK_MEMC_A0_MARK, PORT93_FN1),
536 PINMUX_DATA(MEMC_CS1_MEMC_A1_MARK, PORT94_FN1),
537 PINMUX_DATA(MEMC_ADV_MEMC_DREQ0_MARK, PORT95_FN1),
538 PINMUX_DATA(MEMC_WAIT_MEMC_DREQ1_MARK, PORT96_FN1),
539 PINMUX_DATA(MEMC_NOE_MARK, PORT97_FN1),
540 PINMUX_DATA(MEMC_NWE_MARK, PORT98_FN1),
541 PINMUX_DATA(MEMC_INT_MARK, PORT99_FN1),
542 PINMUX_DATA(VIO_VD_MARK, PORT100_FN1),
543 PINMUX_DATA(VIO_HD_MARK, PORT101_FN1),
544 PINMUX_DATA(VIO_D0_MARK, PORT102_FN1),
545 PINMUX_DATA(VIO_D1_MARK, PORT103_FN1),
546 PINMUX_DATA(VIO_D2_MARK, PORT104_FN1),
547 PINMUX_DATA(VIO_D3_MARK, PORT105_FN1),
548 PINMUX_DATA(VIO_D4_MARK, PORT106_FN1),
549 PINMUX_DATA(VIO_D5_MARK, PORT107_FN1),
550 PINMUX_DATA(VIO_D6_MARK, PORT108_FN1),
551 PINMUX_DATA(VIO_D7_MARK, PORT109_FN1),
552 PINMUX_DATA(VIO_D8_MARK, PORT110_FN1),
553 PINMUX_DATA(VIO_D9_MARK, PORT111_FN1),
554 PINMUX_DATA(VIO_D10_MARK, PORT112_FN1),
555 PINMUX_DATA(VIO_D11_MARK, PORT113_FN1),
556 PINMUX_DATA(VIO_D12_MARK, PORT114_FN1),
557 PINMUX_DATA(VIO_D13_MARK, PORT115_FN1),
558 PINMUX_DATA(VIO_D14_MARK, PORT116_FN1),
559 PINMUX_DATA(VIO_D15_MARK, PORT117_FN1),
560 PINMUX_DATA(VIO_CLK_MARK, PORT118_FN1),
561 PINMUX_DATA(VIO_FIELD_MARK, PORT119_FN1),
562 PINMUX_DATA(VIO_CKO_MARK, PORT120_FN1),
563 PINMUX_DATA(LCDD0_MARK, PORT121_FN1),
564 PINMUX_DATA(LCDD1_MARK, PORT122_FN1),
565 PINMUX_DATA(LCDD2_MARK, PORT123_FN1),
566 PINMUX_DATA(LCDD3_MARK, PORT124_FN1),
567 PINMUX_DATA(LCDD4_MARK, PORT125_FN1),
568 PINMUX_DATA(LCDD5_MARK, PORT126_FN1),
569 PINMUX_DATA(LCDD6_MARK, PORT127_FN1),
570 PINMUX_DATA(LCDD7_MARK, PORT128_FN1),
571 PINMUX_DATA(LCDD8_MARK, PORT129_FN1),
572 PINMUX_DATA(LCDD9_MARK, PORT130_FN1),
573 PINMUX_DATA(LCDD10_MARK, PORT131_FN1),
574 PINMUX_DATA(LCDD11_MARK, PORT132_FN1),
575 PINMUX_DATA(LCDD12_MARK, PORT133_FN1),
576 PINMUX_DATA(LCDD13_MARK, PORT134_FN1),
577 PINMUX_DATA(LCDD14_MARK, PORT135_FN1),
578 PINMUX_DATA(LCDD15_MARK, PORT136_FN1),
579 PINMUX_DATA(LCDD16_MARK, PORT137_FN1),
580 PINMUX_DATA(LCDD17_MARK, PORT138_FN1),
581 PINMUX_DATA(LCDD18_MARK, PORT139_FN1),
582 PINMUX_DATA(LCDD19_MARK, PORT140_FN1),
583 PINMUX_DATA(LCDD20_MARK, PORT141_FN1),
584 PINMUX_DATA(LCDD21_MARK, PORT142_FN1),
585 PINMUX_DATA(LCDD22_MARK, PORT143_FN1),
586 PINMUX_DATA(LCDD23_MARK, PORT144_FN1),
587 PINMUX_DATA(LCDHSYN_MARK, PORT145_FN1),
588 PINMUX_DATA(LCDVSYN_MARK, PORT146_FN1),
589 PINMUX_DATA(LCDDCK_MARK, PORT147_FN1),
590 PINMUX_DATA(LCDRD_MARK, PORT148_FN1),
591 PINMUX_DATA(LCDDISP_MARK, PORT149_FN1),
592 PINMUX_DATA(LCDLCLK_MARK, PORT150_FN1),
593 PINMUX_DATA(LCDDON_MARK, PORT151_FN1),
594 PINMUX_DATA(SCIFA0_TXD_MARK, PORT152_FN1),
595 PINMUX_DATA(SCIFA0_RXD_MARK, PORT153_FN1),
596 PINMUX_DATA(SCIFA1_TXD_MARK, PORT154_FN1),
597 PINMUX_DATA(SCIFA1_RXD_MARK, PORT155_FN1),
598 PINMUX_DATA(TS_SPSYNC1_MARK, PORT156_FN1),
599 PINMUX_DATA(TS_SDAT1_MARK, PORT157_FN1),
600 PINMUX_DATA(TS_SDEN1_MARK, PORT158_FN1),
601 PINMUX_DATA(TS_SCK1_MARK, PORT159_FN1),
602 PINMUX_DATA(TPU0TO0_MARK, PORT160_FN1),
603 PINMUX_DATA(TPU0TO1_MARK, PORT161_FN1),
604 PINMUX_DATA(SCIFB_SCK_MARK, PORT162_FN1),
605 PINMUX_DATA(SCIFB_RTS_MARK, PORT163_FN1),
606 PINMUX_DATA(SCIFB_CTS_MARK, PORT164_FN1),
607 PINMUX_DATA(SCIFB_TXD_MARK, PORT165_FN1),
608 PINMUX_DATA(SCIFB_RXD_MARK, PORT166_FN1),
609 PINMUX_DATA(VBUS0_0_MARK, PORT167_FN1),
610 PINMUX_DATA(VBUS0_1_MARK, PORT168_FN1),
611 PINMUX_DATA(HDMI_HPD_MARK, PORT169_FN1),
612 PINMUX_DATA(HDMI_CEC_MARK, PORT170_FN1),
613 PINMUX_DATA(SDHICLK0_MARK, PORT171_FN1),
614 PINMUX_DATA(SDHICD0_MARK, PORT172_FN1),
615 PINMUX_DATA(SDHID0_0_MARK, PORT173_FN1),
616 PINMUX_DATA(SDHID0_1_MARK, PORT174_FN1),
617 PINMUX_DATA(SDHID0_2_MARK, PORT175_FN1),
618 PINMUX_DATA(SDHID0_3_MARK, PORT176_FN1),
619 PINMUX_DATA(SDHICMD0_MARK, PORT177_FN1),
620 PINMUX_DATA(SDHIWP0_MARK, PORT178_FN1),
621 PINMUX_DATA(SDHICLK1_MARK, PORT179_FN1),
622 PINMUX_DATA(SDHID1_0_MARK, PORT180_FN1),
623 PINMUX_DATA(SDHID1_1_MARK, PORT181_FN1),
624 PINMUX_DATA(SDHID1_2_MARK, PORT182_FN1),
625 PINMUX_DATA(SDHID1_3_MARK, PORT183_FN1),
626 PINMUX_DATA(SDHICMD1_MARK, PORT184_FN1),
627 PINMUX_DATA(SDHICLK2_MARK, PORT185_FN1),
628 PINMUX_DATA(SDHID2_0_MARK, PORT186_FN1),
629 PINMUX_DATA(SDHID2_1_MARK, PORT187_FN1),
630 PINMUX_DATA(SDHID2_2_MARK, PORT188_FN1),
631 PINMUX_DATA(SDHID2_3_MARK, PORT189_FN1),
632 PINMUX_DATA(SDHICMD2_MARK, PORT190_FN1),
633
634 /* Function 2 */
635 PINMUX_DATA(FSIBCK_MARK, PORT4_FN2),
636 PINMUX_DATA(SCIFA4_RXD_MARK, PORT5_FN2),
637 PINMUX_DATA(SCIFA4_TXD_MARK, PORT6_FN2),
638 PINMUX_DATA(SCIFA5_RXD_MARK, PORT8_FN2),
639 PINMUX_DATA(FSIASPDIF_11_MARK, PORT11_FN2),
640 PINMUX_DATA(SCIFA5_TXD_MARK, PORT12_FN2),
641 PINMUX_DATA(FMSIOLR_MARK, PORT13_FN2),
642 PINMUX_DATA(FMSIOBT_MARK, PORT14_FN2),
643 PINMUX_DATA(FSIASPDIF_15_MARK, PORT15_FN2),
644 PINMUX_DATA(FMSIILR_MARK, PORT16_FN2),
645 PINMUX_DATA(FMSIIBT_MARK, PORT17_FN2),
646 PINMUX_DATA(BS_MARK, PORT19_FN2),
647 PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT36_FN2),
648 PINMUX_DATA(MSIOF0_TSCK_MARK, PORT37_FN2),
649 PINMUX_DATA(MSIOF0_RXD_MARK, PORT38_FN2),
650 PINMUX_DATA(MSIOF0_RSCK_MARK, PORT39_FN2),
651 PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT40_FN2),
652 PINMUX_DATA(MSIOF0_MCK0_MARK, PORT41_FN2),
653 PINMUX_DATA(MSIOF0_MCK1_MARK, PORT42_FN2),
654 PINMUX_DATA(MSIOF0_SS1_MARK, PORT43_FN2),
655 PINMUX_DATA(MSIOF0_SS2_MARK, PORT44_FN2),
656 PINMUX_DATA(MSIOF0_TXD_MARK, PORT45_FN2),
657 PINMUX_DATA(FMSICK_MARK, PORT65_FN2),
658 PINMUX_DATA(FCE1_MARK, PORT66_FN2),
659 PINMUX_DATA(BBIF1_RXD_MARK, PORT76_FN2),
660 PINMUX_DATA(BBIF1_TSYNC_MARK, PORT77_FN2),
661 PINMUX_DATA(BBIF1_TSCK_MARK, PORT78_FN2),
662 PINMUX_DATA(BBIF1_TXD_MARK, PORT79_FN2),
663 PINMUX_DATA(BBIF1_RSCK_MARK, PORT80_FN2),
664 PINMUX_DATA(BBIF1_RSYNC_MARK, PORT81_FN2),
665 PINMUX_DATA(BBIF1_FLOW_MARK, PORT82_FN2),
666 PINMUX_DATA(BB_RX_FLOW_N_MARK, PORT83_FN2),
667 PINMUX_DATA(MSIOF1_RSCK_MARK, PORT84_FN2),
668 PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT85_FN2),
669 PINMUX_DATA(MSIOF1_MCK0_MARK, PORT86_FN2),
670 PINMUX_DATA(MSIOF1_MCK1_MARK, PORT87_FN2),
671 PINMUX_DATA(MSIOF1_TSCK_88_MARK, PORT88_FN2, MSEL4CR_10_1),
672 PINMUX_DATA(MSIOF1_TSYNC_89_MARK, PORT89_FN2, MSEL4CR_10_1),
673 PINMUX_DATA(MSIOF1_TXD_90_MARK, PORT90_FN2, MSEL4CR_10_1),
674 PINMUX_DATA(MSIOF1_RXD_91_MARK, PORT91_FN2, MSEL4CR_10_1),
675 PINMUX_DATA(MSIOF1_SS1_92_MARK, PORT92_FN2, MSEL4CR_10_1),
676 PINMUX_DATA(MSIOF1_SS2_93_MARK, PORT93_FN2, MSEL4CR_10_1),
677 PINMUX_DATA(SCIFA2_CTS1_MARK, PORT94_FN2),
678 PINMUX_DATA(SCIFA2_RTS1_MARK, PORT95_FN2),
679 PINMUX_DATA(SCIFA2_TXD1_MARK, PORT96_FN2),
680 PINMUX_DATA(SCIFA2_RXD1_MARK, PORT97_FN2),
681 PINMUX_DATA(SCIFA2_SCK1_MARK, PORT98_FN2),
682 PINMUX_DATA(I2C_SCL2_MARK, PORT110_FN2),
683 PINMUX_DATA(I2C_SDA2_MARK, PORT111_FN2),
684 PINMUX_DATA(I2C_SCL3_MARK, PORT114_FN2, MSEL4CR_16_1),
685 PINMUX_DATA(I2C_SDA3_MARK, PORT115_FN2, MSEL4CR_16_1),
686 PINMUX_DATA(I2C_SCL4_MARK, PORT116_FN2, MSEL4CR_17_1),
687 PINMUX_DATA(I2C_SDA4_MARK, PORT117_FN2, MSEL4CR_17_1),
688 PINMUX_DATA(MSIOF2_RSCK_MARK, PORT134_FN2),
689 PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT135_FN2),
690 PINMUX_DATA(MSIOF2_MCK0_MARK, PORT136_FN2),
691 PINMUX_DATA(MSIOF2_MCK1_MARK, PORT137_FN2),
692 PINMUX_DATA(MSIOF2_SS1_MARK, PORT138_FN2),
693 PINMUX_DATA(MSIOF2_SS2_MARK, PORT139_FN2),
694 PINMUX_DATA(SCIFA3_CTS_140_MARK, PORT140_FN2, MSEL3CR_9_1),
695 PINMUX_DATA(SCIFA3_RTS_141_MARK, PORT141_FN2),
696 PINMUX_DATA(SCIFA3_SCK_MARK, PORT142_FN2),
697 PINMUX_DATA(SCIFA3_TXD_MARK, PORT143_FN2),
698 PINMUX_DATA(SCIFA3_RXD_MARK, PORT144_FN2),
699 PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT148_FN2),
700 PINMUX_DATA(MSIOF2_TSCK_MARK, PORT149_FN2),
701 PINMUX_DATA(MSIOF2_RXD_MARK, PORT150_FN2),
702 PINMUX_DATA(MSIOF2_TXD_MARK, PORT151_FN2),
703 PINMUX_DATA(SCIFA0_SCK_MARK, PORT156_FN2),
704 PINMUX_DATA(SCIFA0_RTS_MARK, PORT157_FN2),
705 PINMUX_DATA(SCIFA0_CTS_MARK, PORT158_FN2),
706 PINMUX_DATA(SCIFA1_SCK_MARK, PORT159_FN2),
707 PINMUX_DATA(SCIFA1_RTS_MARK, PORT160_FN2),
708 PINMUX_DATA(SCIFA1_CTS_MARK, PORT161_FN2),
709
710 /* Function 3 */
711 PINMUX_DATA(VIO_CKO1_MARK, PORT16_FN3),
712 PINMUX_DATA(VIO_CKO2_MARK, PORT17_FN3),
713 PINMUX_DATA(IDIN_1_18_MARK, PORT18_FN3, MSEL4CR_14_1),
714 PINMUX_DATA(MSIOF1_TSCK_39_MARK, PORT39_FN3, MSEL4CR_10_0),
715 PINMUX_DATA(MSIOF1_TSYNC_40_MARK, PORT40_FN3, MSEL4CR_10_0),
716 PINMUX_DATA(MSIOF1_TXD_41_MARK, PORT41_FN3, MSEL4CR_10_0),
717 PINMUX_DATA(MSIOF1_RXD_42_MARK, PORT42_FN3, MSEL4CR_10_0),
718 PINMUX_DATA(MSIOF1_SS1_43_MARK, PORT43_FN3, MSEL4CR_10_0),
719 PINMUX_DATA(MSIOF1_SS2_44_MARK, PORT44_FN3, MSEL4CR_10_0),
720 PINMUX_DATA(MMCD1_0_MARK, PORT54_FN3, MSEL4CR_15_1),
721 PINMUX_DATA(MMCD1_1_MARK, PORT55_FN3, MSEL4CR_15_1),
722 PINMUX_DATA(MMCD1_2_MARK, PORT56_FN3, MSEL4CR_15_1),
723 PINMUX_DATA(MMCD1_3_MARK, PORT57_FN3, MSEL4CR_15_1),
724 PINMUX_DATA(MMCD1_4_MARK, PORT58_FN3, MSEL4CR_15_1),
725 PINMUX_DATA(MMCD1_5_MARK, PORT59_FN3, MSEL4CR_15_1),
726 PINMUX_DATA(MMCD1_6_MARK, PORT60_FN3, MSEL4CR_15_1),
727 PINMUX_DATA(MMCD1_7_MARK, PORT61_FN3, MSEL4CR_15_1),
728 PINMUX_DATA(VINT_I_MARK, PORT65_FN3),
729 PINMUX_DATA(MMCCLK1_MARK, PORT66_FN3, MSEL4CR_15_1),
730 PINMUX_DATA(MMCCMD1_MARK, PORT67_FN3, MSEL4CR_15_1),
731 PINMUX_DATA(TPU0TO2_93_MARK, PORT93_FN3),
732 PINMUX_DATA(TPU0TO2_99_MARK, PORT99_FN3),
733 PINMUX_DATA(TPU0TO3_MARK, PORT112_FN3),
734 PINMUX_DATA(IDIN_0_MARK, PORT113_FN3),
735 PINMUX_DATA(EXTLP_0_MARK, PORT114_FN3),
736 PINMUX_DATA(OVCN2_0_MARK, PORT115_FN3),
737 PINMUX_DATA(PWEN_0_MARK, PORT116_FN3),
738 PINMUX_DATA(OVCN_0_MARK, PORT117_FN3),
739 PINMUX_DATA(KEYOUT7_MARK, PORT121_FN3),
740 PINMUX_DATA(KEYOUT6_MARK, PORT122_FN3),
741 PINMUX_DATA(KEYOUT5_MARK, PORT123_FN3),
742 PINMUX_DATA(KEYOUT4_MARK, PORT124_FN3),
743 PINMUX_DATA(KEYOUT3_MARK, PORT125_FN3),
744 PINMUX_DATA(KEYOUT2_MARK, PORT126_FN3),
745 PINMUX_DATA(KEYOUT1_MARK, PORT127_FN3),
746 PINMUX_DATA(KEYOUT0_MARK, PORT128_FN3),
747 PINMUX_DATA(KEYIN7_MARK, PORT129_FN3),
748 PINMUX_DATA(KEYIN6_MARK, PORT130_FN3),
749 PINMUX_DATA(KEYIN5_MARK, PORT131_FN3),
750 PINMUX_DATA(KEYIN4_MARK, PORT132_FN3),
751 PINMUX_DATA(KEYIN3_133_MARK, PORT133_FN3, MSEL4CR_18_0),
752 PINMUX_DATA(KEYIN2_134_MARK, PORT134_FN3, MSEL4CR_18_0),
753 PINMUX_DATA(KEYIN1_135_MARK, PORT135_FN3, MSEL4CR_18_0),
754 PINMUX_DATA(KEYIN0_136_MARK, PORT136_FN3, MSEL4CR_18_0),
755 PINMUX_DATA(TS_SPSYNC2_MARK, PORT137_FN3),
756 PINMUX_DATA(IROUT_139_MARK, PORT139_FN3),
757 PINMUX_DATA(IRDA_OUT_MARK, PORT140_FN3),
758 PINMUX_DATA(IRDA_IN_MARK, PORT141_FN3),
759 PINMUX_DATA(IRDA_FIRSEL_MARK, PORT142_FN3),
760 PINMUX_DATA(TS_SDAT2_MARK, PORT145_FN3),
761 PINMUX_DATA(TS_SDEN2_MARK, PORT146_FN3),
762 PINMUX_DATA(TS_SCK2_MARK, PORT147_FN3),
763
764 /* Function 4 */
765 PINMUX_DATA(SCIFA3_CTS_43_MARK, PORT43_FN4, MSEL3CR_9_0),
766 PINMUX_DATA(SCIFA3_RTS_44_MARK, PORT44_FN4),
767 PINMUX_DATA(GP_RX_FLAG_MARK, PORT76_FN4),
768 PINMUX_DATA(GP_RX_DATA_MARK, PORT77_FN4),
769 PINMUX_DATA(GP_TX_READY_MARK, PORT78_FN4),
770 PINMUX_DATA(GP_RX_WAKE_MARK, PORT79_FN4),
771 PINMUX_DATA(MP_TX_FLAG_MARK, PORT80_FN4),
772 PINMUX_DATA(MP_TX_DATA_MARK, PORT81_FN4),
773 PINMUX_DATA(MP_RX_READY_MARK, PORT82_FN4),
774 PINMUX_DATA(MP_TX_WAKE_MARK, PORT83_FN4),
775 PINMUX_DATA(MMCD0_0_MARK, PORT84_FN4, MSEL4CR_15_0),
776 PINMUX_DATA(MMCD0_1_MARK, PORT85_FN4, MSEL4CR_15_0),
777 PINMUX_DATA(MMCD0_2_MARK, PORT86_FN4, MSEL4CR_15_0),
778 PINMUX_DATA(MMCD0_3_MARK, PORT87_FN4, MSEL4CR_15_0),
779 PINMUX_DATA(MMCD0_4_MARK, PORT88_FN4, MSEL4CR_15_0),
780 PINMUX_DATA(MMCD0_5_MARK, PORT89_FN4, MSEL4CR_15_0),
781 PINMUX_DATA(MMCD0_6_MARK, PORT90_FN4, MSEL4CR_15_0),
782 PINMUX_DATA(MMCD0_7_MARK, PORT91_FN4, MSEL4CR_15_0),
783 PINMUX_DATA(MMCCMD0_MARK, PORT92_FN4, MSEL4CR_15_0),
784 PINMUX_DATA(SIM_RST_MARK, PORT94_FN4),
785 PINMUX_DATA(SIM_CLK_MARK, PORT95_FN4),
786 PINMUX_DATA(SIM_D_MARK, PORT98_FN4),
787 PINMUX_DATA(MMCCLK0_MARK, PORT99_FN4, MSEL4CR_15_0),
788 PINMUX_DATA(IDIN_1_113_MARK, PORT113_FN4, MSEL4CR_14_0),
789 PINMUX_DATA(OVCN_1_114_MARK, PORT114_FN4, MSEL4CR_14_0),
790 PINMUX_DATA(PWEN_1_115_MARK, PORT115_FN4),
791 PINMUX_DATA(EXTLP_1_MARK, PORT116_FN4),
792 PINMUX_DATA(OVCN2_1_MARK, PORT117_FN4),
793 PINMUX_DATA(KEYIN0_121_MARK, PORT121_FN4, MSEL4CR_18_1),
794 PINMUX_DATA(KEYIN1_122_MARK, PORT122_FN4, MSEL4CR_18_1),
795 PINMUX_DATA(KEYIN2_123_MARK, PORT123_FN4, MSEL4CR_18_1),
796 PINMUX_DATA(KEYIN3_124_MARK, PORT124_FN4, MSEL4CR_18_1),
797 PINMUX_DATA(PWEN_1_138_MARK, PORT138_FN4),
798 PINMUX_DATA(IROUT_140_MARK, PORT140_FN4),
799 PINMUX_DATA(LCDCS_MARK, PORT145_FN4),
800 PINMUX_DATA(LCDWR_MARK, PORT147_FN4),
801 PINMUX_DATA(LCDRS_MARK, PORT149_FN4),
802 PINMUX_DATA(OVCN_1_162_MARK, PORT162_FN4, MSEL4CR_14_1),
803
804 /* Function 5 */
805 PINMUX_DATA(GPI0_MARK, PORT41_FN5),
806 PINMUX_DATA(GPI1_MARK, PORT42_FN5),
807 PINMUX_DATA(GPO0_MARK, PORT43_FN5),
808 PINMUX_DATA(GPO1_MARK, PORT44_FN5),
809 PINMUX_DATA(I2C_SCL3S_MARK, PORT137_FN5, MSEL4CR_16_0),
810 PINMUX_DATA(I2C_SDA3S_MARK, PORT145_FN5, MSEL4CR_16_0),
811 PINMUX_DATA(I2C_SCL4S_MARK, PORT146_FN5, MSEL4CR_17_0),
812 PINMUX_DATA(I2C_SDA4S_MARK, PORT147_FN5, MSEL4CR_17_0),
813
814 /* Function select */
815 PINMUX_DATA(LCDC0_SELECT_MARK, MSEL3CR_6_0),
816 PINMUX_DATA(LCDC1_SELECT_MARK, MSEL3CR_6_1),
817
818 PINMUX_DATA(TS0_1SELECT_MARK, MSEL3CR_21_0, MSEL3CR_20_0),
819 PINMUX_DATA(TS0_2SELECT_MARK, MSEL3CR_21_0, MSEL3CR_20_1),
820 PINMUX_DATA(TS1_1SELECT_MARK, MSEL3CR_27_0, MSEL3CR_26_0),
821 PINMUX_DATA(TS1_2SELECT_MARK, MSEL3CR_27_0, MSEL3CR_26_1),
822
823 PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0),
824 PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1),
825
826 PINMUX_DATA(MFIv6_MARK, MSEL4CR_6_0),
827 PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1),
828 };
829
830 #define __I (SH_PFC_PIN_CFG_INPUT)
831 #define __O (SH_PFC_PIN_CFG_OUTPUT)
832 #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
833 #define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
834 #define __PU (SH_PFC_PIN_CFG_PULL_UP)
835 #define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
836
837 #define SH7372_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD)
838 #define SH7372_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU)
839 #define SH7372_PIN_I_PU_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PUD)
840 #define SH7372_PIN_IO(pin) SH_PFC_PIN_CFG(pin, __IO)
841 #define SH7372_PIN_IO_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PD)
842 #define SH7372_PIN_IO_PU(pin) SH_PFC_PIN_CFG(pin, __IO | __PU)
843 #define SH7372_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
844 #define SH7372_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
845 #define SH7372_PIN_O_PU_PD(pin) SH_PFC_PIN_CFG(pin, __O | __PUD)
846
847 static const struct sh_pfc_pin pinmux_pins[] = {
848 /* Table 57-1 (I/O and Pull U/D) */
849 SH7372_PIN_IO_PD(0), SH7372_PIN_IO_PD(1),
850 SH7372_PIN_O(2), SH7372_PIN_I_PD(3),
851 SH7372_PIN_I_PD(4), SH7372_PIN_I_PD(5),
852 SH7372_PIN_IO_PU_PD(6), SH7372_PIN_I_PD(7),
853 SH7372_PIN_IO_PD(8), SH7372_PIN_O(9),
854 SH7372_PIN_O(10), SH7372_PIN_O(11),
855 SH7372_PIN_IO_PU_PD(12), SH7372_PIN_IO_PD(13),
856 SH7372_PIN_IO_PD(14), SH7372_PIN_O(15),
857 SH7372_PIN_IO_PD(16), SH7372_PIN_IO_PD(17),
858 SH7372_PIN_I_PD(18), SH7372_PIN_IO(19),
859 SH7372_PIN_IO(20), SH7372_PIN_IO(21),
860 SH7372_PIN_IO(22), SH7372_PIN_IO(23),
861 SH7372_PIN_IO(24), SH7372_PIN_IO(25),
862 SH7372_PIN_IO(26), SH7372_PIN_IO(27),
863 SH7372_PIN_IO(28), SH7372_PIN_IO(29),
864 SH7372_PIN_IO(30), SH7372_PIN_IO(31),
865 SH7372_PIN_IO(32), SH7372_PIN_IO(33),
866 SH7372_PIN_IO(34), SH7372_PIN_IO(35),
867 SH7372_PIN_IO(36), SH7372_PIN_IO(37),
868 SH7372_PIN_IO(38), SH7372_PIN_IO(39),
869 SH7372_PIN_IO(40), SH7372_PIN_IO(41),
870 SH7372_PIN_IO(42), SH7372_PIN_IO(43),
871 SH7372_PIN_IO(44), SH7372_PIN_IO(45),
872 SH7372_PIN_IO_PU(46), SH7372_PIN_IO_PU(47),
873 SH7372_PIN_IO_PU(48), SH7372_PIN_IO_PU(49),
874 SH7372_PIN_IO_PU(50), SH7372_PIN_IO_PU(51),
875 SH7372_PIN_IO_PU(52), SH7372_PIN_IO_PU(53),
876 SH7372_PIN_IO_PU(54), SH7372_PIN_IO_PU(55),
877 SH7372_PIN_IO_PU(56), SH7372_PIN_IO_PU(57),
878 SH7372_PIN_IO_PU(58), SH7372_PIN_IO_PU(59),
879 SH7372_PIN_IO_PU(60), SH7372_PIN_IO_PU(61),
880 SH7372_PIN_IO(62), SH7372_PIN_O(63),
881 SH7372_PIN_O(64), SH7372_PIN_IO_PU(65),
882 SH7372_PIN_O_PU_PD(66), SH7372_PIN_IO_PU(67),
883 SH7372_PIN_O(68), SH7372_PIN_IO(69),
884 SH7372_PIN_IO(70), SH7372_PIN_IO(71),
885 SH7372_PIN_O(72), SH7372_PIN_I_PU(73),
886 SH7372_PIN_I_PU_PD(74), SH7372_PIN_IO_PU_PD(75),
887 SH7372_PIN_IO_PU_PD(76), SH7372_PIN_IO_PU_PD(77),
888 SH7372_PIN_IO_PU_PD(78), SH7372_PIN_IO_PU_PD(79),
889 SH7372_PIN_IO_PU_PD(80), SH7372_PIN_IO_PU_PD(81),
890 SH7372_PIN_IO_PU_PD(82), SH7372_PIN_IO_PU_PD(83),
891 SH7372_PIN_IO_PU_PD(84), SH7372_PIN_IO_PU_PD(85),
892 SH7372_PIN_IO_PU_PD(86), SH7372_PIN_IO_PU_PD(87),
893 SH7372_PIN_IO_PU_PD(88), SH7372_PIN_IO_PU_PD(89),
894 SH7372_PIN_IO_PU_PD(90), SH7372_PIN_IO_PU_PD(91),
895 SH7372_PIN_IO_PU_PD(92), SH7372_PIN_IO_PU_PD(93),
896 SH7372_PIN_IO_PU_PD(94), SH7372_PIN_IO_PU_PD(95),
897 SH7372_PIN_IO_PU(96), SH7372_PIN_IO_PU_PD(97),
898 SH7372_PIN_IO_PU_PD(98), SH7372_PIN_O_PU_PD(99),
899 SH7372_PIN_IO_PD(100), SH7372_PIN_IO_PD(101),
900 SH7372_PIN_IO_PD(102), SH7372_PIN_IO_PD(103),
901 SH7372_PIN_IO_PD(104), SH7372_PIN_IO_PD(105),
902 SH7372_PIN_IO_PU(106), SH7372_PIN_IO_PU(107),
903 SH7372_PIN_IO_PU(108), SH7372_PIN_IO_PU(109),
904 SH7372_PIN_IO_PU(110), SH7372_PIN_IO_PU(111),
905 SH7372_PIN_IO_PD(112), SH7372_PIN_IO_PD(113),
906 SH7372_PIN_IO_PU(114), SH7372_PIN_IO_PU(115),
907 SH7372_PIN_IO_PU(116), SH7372_PIN_IO_PU(117),
908 SH7372_PIN_IO_PU(118), SH7372_PIN_IO_PU(119),
909 SH7372_PIN_IO_PU(120), SH7372_PIN_IO_PD(121),
910 SH7372_PIN_IO_PD(122), SH7372_PIN_IO_PD(123),
911 SH7372_PIN_IO_PD(124), SH7372_PIN_IO_PD(125),
912 SH7372_PIN_IO_PD(126), SH7372_PIN_IO_PD(127),
913 SH7372_PIN_IO_PD(128), SH7372_PIN_IO_PU_PD(129),
914 SH7372_PIN_IO_PU_PD(130), SH7372_PIN_IO_PU_PD(131),
915 SH7372_PIN_IO_PU_PD(132), SH7372_PIN_IO_PU_PD(133),
916 SH7372_PIN_IO_PU_PD(134), SH7372_PIN_IO_PU_PD(135),
917 SH7372_PIN_IO_PD(136), SH7372_PIN_IO_PD(137),
918 SH7372_PIN_IO_PD(138), SH7372_PIN_IO_PD(139),
919 SH7372_PIN_IO_PD(140), SH7372_PIN_IO_PD(141),
920 SH7372_PIN_IO_PD(142), SH7372_PIN_IO_PU_PD(143),
921 SH7372_PIN_IO_PD(144), SH7372_PIN_IO_PD(145),
922 SH7372_PIN_IO_PD(146), SH7372_PIN_IO_PD(147),
923 SH7372_PIN_IO_PD(148), SH7372_PIN_IO_PD(149),
924 SH7372_PIN_IO_PD(150), SH7372_PIN_IO_PD(151),
925 SH7372_PIN_IO_PU_PD(152), SH7372_PIN_I_PD(153),
926 SH7372_PIN_IO_PU_PD(154), SH7372_PIN_I_PD(155),
927 SH7372_PIN_IO_PD(156), SH7372_PIN_IO_PD(157),
928 SH7372_PIN_I_PD(158), SH7372_PIN_IO_PD(159),
929 SH7372_PIN_O(160), SH7372_PIN_IO_PD(161),
930 SH7372_PIN_IO_PD(162), SH7372_PIN_IO_PD(163),
931 SH7372_PIN_I_PD(164), SH7372_PIN_IO_PD(165),
932 SH7372_PIN_I_PD(166), SH7372_PIN_I_PD(167),
933 SH7372_PIN_I_PD(168), SH7372_PIN_I_PD(169),
934 SH7372_PIN_I_PD(170), SH7372_PIN_O(171),
935 SH7372_PIN_IO_PU_PD(172), SH7372_PIN_IO_PU_PD(173),
936 SH7372_PIN_IO_PU_PD(174), SH7372_PIN_IO_PU_PD(175),
937 SH7372_PIN_IO_PU_PD(176), SH7372_PIN_IO_PU_PD(177),
938 SH7372_PIN_IO_PU_PD(178), SH7372_PIN_O(179),
939 SH7372_PIN_IO_PU_PD(180), SH7372_PIN_IO_PU_PD(181),
940 SH7372_PIN_IO_PU_PD(182), SH7372_PIN_IO_PU_PD(183),
941 SH7372_PIN_IO_PU_PD(184), SH7372_PIN_O(185),
942 SH7372_PIN_IO_PU_PD(186), SH7372_PIN_IO_PU_PD(187),
943 SH7372_PIN_IO_PU_PD(188), SH7372_PIN_IO_PU_PD(189),
944 SH7372_PIN_IO_PU_PD(190),
945 };
946
947 /* - BSC -------------------------------------------------------------------- */
948 static const unsigned int bsc_data8_pins[] = {
949 /* D[0:7] */
950 46, 47, 48, 49, 50, 51, 52, 53,
951 };
952 static const unsigned int bsc_data8_mux[] = {
953 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
954 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
955 };
956 static const unsigned int bsc_data16_pins[] = {
957 /* D[0:15] */
958 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
959 };
960 static const unsigned int bsc_data16_mux[] = {
961 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
962 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
963 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
964 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
965 };
966 static const unsigned int bsc_cs0_pins[] = {
967 /* CS */
968 62,
969 };
970 static const unsigned int bsc_cs0_mux[] = {
971 CS0_MARK,
972 };
973 static const unsigned int bsc_cs2_pins[] = {
974 /* CS */
975 63,
976 };
977 static const unsigned int bsc_cs2_mux[] = {
978 CS2_MARK,
979 };
980 static const unsigned int bsc_cs4_pins[] = {
981 /* CS */
982 64,
983 };
984 static const unsigned int bsc_cs4_mux[] = {
985 CS4_MARK,
986 };
987 static const unsigned int bsc_cs5a_pins[] = {
988 /* CS */
989 65,
990 };
991 static const unsigned int bsc_cs5a_mux[] = {
992 CS5A_MARK,
993 };
994 static const unsigned int bsc_cs5b_pins[] = {
995 /* CS */
996 66,
997 };
998 static const unsigned int bsc_cs5b_mux[] = {
999 CS5B_MARK,
1000 };
1001 static const unsigned int bsc_cs6a_pins[] = {
1002 /* CS */
1003 67,
1004 };
1005 static const unsigned int bsc_cs6a_mux[] = {
1006 CS6A_MARK,
1007 };
1008 static const unsigned int bsc_rd_we8_pins[] = {
1009 /* RD, WE[0] */
1010 69, 70,
1011 };
1012 static const unsigned int bsc_rd_we8_mux[] = {
1013 RD_FSC_MARK, WE0_FWE_MARK,
1014 };
1015 static const unsigned int bsc_rd_we16_pins[] = {
1016 /* RD, WE[0:1] */
1017 69, 70, 71,
1018 };
1019 static const unsigned int bsc_rd_we16_mux[] = {
1020 RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
1021 };
1022 static const unsigned int bsc_bs_pins[] = {
1023 /* BS */
1024 19,
1025 };
1026 static const unsigned int bsc_bs_mux[] = {
1027 BS_MARK,
1028 };
1029 static const unsigned int bsc_rdwr_pins[] = {
1030 /* RDWR */
1031 75,
1032 };
1033 static const unsigned int bsc_rdwr_mux[] = {
1034 RDWR_MARK,
1035 };
1036 static const unsigned int bsc_wait_pins[] = {
1037 /* WAIT */
1038 74,
1039 };
1040 static const unsigned int bsc_wait_mux[] = {
1041 WAIT_MARK,
1042 };
1043 /* - CEU -------------------------------------------------------------------- */
1044 static const unsigned int ceu_data_0_7_pins[] = {
1045 /* D[0:7] */
1046 102, 103, 104, 105, 106, 107, 108, 109,
1047 };
1048 static const unsigned int ceu_data_0_7_mux[] = {
1049 VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK, VIO_D3_MARK,
1050 VIO_D4_MARK, VIO_D5_MARK, VIO_D6_MARK, VIO_D7_MARK,
1051 };
1052 static const unsigned int ceu_data_8_15_pins[] = {
1053 /* D[8:15] */
1054 110, 111, 112, 113, 114, 115, 116, 117,
1055 };
1056 static const unsigned int ceu_data_8_15_mux[] = {
1057 VIO_D8_MARK, VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK,
1058 VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK, VIO_D15_MARK,
1059 };
1060 static const unsigned int ceu_clk_0_pins[] = {
1061 /* CKO */
1062 120,
1063 };
1064 static const unsigned int ceu_clk_0_mux[] = {
1065 VIO_CKO_MARK,
1066 };
1067 static const unsigned int ceu_clk_1_pins[] = {
1068 /* CKO */
1069 16,
1070 };
1071 static const unsigned int ceu_clk_1_mux[] = {
1072 VIO_CKO1_MARK,
1073 };
1074 static const unsigned int ceu_clk_2_pins[] = {
1075 /* CKO */
1076 17,
1077 };
1078 static const unsigned int ceu_clk_2_mux[] = {
1079 VIO_CKO2_MARK,
1080 };
1081 static const unsigned int ceu_sync_pins[] = {
1082 /* CLK, VD, HD */
1083 118, 100, 101,
1084 };
1085 static const unsigned int ceu_sync_mux[] = {
1086 VIO_CLK_MARK, VIO_VD_MARK, VIO_HD_MARK,
1087 };
1088 static const unsigned int ceu_field_pins[] = {
1089 /* FIELD */
1090 119,
1091 };
1092 static const unsigned int ceu_field_mux[] = {
1093 VIO_FIELD_MARK,
1094 };
1095 /* - FLCTL ------------------------------------------------------------------ */
1096 static const unsigned int flctl_data_pins[] = {
1097 /* NAF[0:15] */
1098 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
1099 };
1100 static const unsigned int flctl_data_mux[] = {
1101 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1102 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1103 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1104 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1105 };
1106 static const unsigned int flctl_ce0_pins[] = {
1107 /* CE */
1108 68,
1109 };
1110 static const unsigned int flctl_ce0_mux[] = {
1111 FCE0_MARK,
1112 };
1113 static const unsigned int flctl_ce1_pins[] = {
1114 /* CE */
1115 66,
1116 };
1117 static const unsigned int flctl_ce1_mux[] = {
1118 FCE1_MARK,
1119 };
1120 static const unsigned int flctl_ctrl_pins[] = {
1121 /* FCDE, FOE, FSC, FWE, FRB */
1122 24, 23, 69, 70, 73,
1123 };
1124 static const unsigned int flctl_ctrl_mux[] = {
1125 A5_FCDE_MARK, A4_FOE_MARK, RD_FSC_MARK, WE0_FWE_MARK, FRB_MARK,
1126 };
1127 /* - FSIA ------------------------------------------------------------------- */
1128 static const unsigned int fsia_mclk_in_pins[] = {
1129 /* CK */
1130 4,
1131 };
1132 static const unsigned int fsia_mclk_in_mux[] = {
1133 FSIACK_MARK,
1134 };
1135 static const unsigned int fsia_mclk_out_pins[] = {
1136 /* OMC */
1137 8,
1138 };
1139 static const unsigned int fsia_mclk_out_mux[] = {
1140 FSIAOMC_MARK,
1141 };
1142 static const unsigned int fsia_sclk_in_pins[] = {
1143 /* ILR, IBT */
1144 5, 6,
1145 };
1146 static const unsigned int fsia_sclk_in_mux[] = {
1147 FSIAILR_MARK, FSIAIBT_MARK,
1148 };
1149 static const unsigned int fsia_sclk_out_pins[] = {
1150 /* OLR, OBT */
1151 9, 10,
1152 };
1153 static const unsigned int fsia_sclk_out_mux[] = {
1154 FSIAOLR_MARK, FSIAOBT_MARK,
1155 };
1156 static const unsigned int fsia_data_in_pins[] = {
1157 /* ISLD */
1158 7,
1159 };
1160 static const unsigned int fsia_data_in_mux[] = {
1161 FSIAISLD_MARK,
1162 };
1163 static const unsigned int fsia_data_out_pins[] = {
1164 /* OSLD */
1165 11,
1166 };
1167 static const unsigned int fsia_data_out_mux[] = {
1168 FSIAOSLD_MARK,
1169 };
1170 static const unsigned int fsia_spdif_0_pins[] = {
1171 /* SPDIF */
1172 11,
1173 };
1174 static const unsigned int fsia_spdif_0_mux[] = {
1175 FSIASPDIF_11_MARK,
1176 };
1177 static const unsigned int fsia_spdif_1_pins[] = {
1178 /* SPDIF */
1179 15,
1180 };
1181 static const unsigned int fsia_spdif_1_mux[] = {
1182 FSIASPDIF_15_MARK,
1183 };
1184 /* - FSIB ------------------------------------------------------------------- */
1185 static const unsigned int fsib_mclk_in_pins[] = {
1186 /* CK */
1187 4,
1188 };
1189 static const unsigned int fsib_mclk_in_mux[] = {
1190 FSIBCK_MARK,
1191 };
1192 /* - HDMI ------------------------------------------------------------------- */
1193 static const unsigned int hdmi_pins[] = {
1194 /* HPD, CEC */
1195 169, 170,
1196 };
1197 static const unsigned int hdmi_mux[] = {
1198 HDMI_HPD_MARK, HDMI_CEC_MARK,
1199 };
1200 /* - INTC ------------------------------------------------------------------- */
1201 IRQC_PINS_MUX(0, 6, 162);
1202 IRQC_PIN_MUX(1, 12);
1203 IRQC_PINS_MUX(2, 4, 5);
1204 IRQC_PINS_MUX(3, 8, 16);
1205 IRQC_PINS_MUX(4, 17, 163);
1206 IRQC_PIN_MUX(5, 18);
1207 IRQC_PINS_MUX(6, 39, 164);
1208 IRQC_PINS_MUX(7, 40, 167);
1209 IRQC_PINS_MUX(8, 41, 168);
1210 IRQC_PINS_MUX(9, 42, 169);
1211 IRQC_PIN_MUX(10, 65);
1212 IRQC_PIN_MUX(11, 67);
1213 IRQC_PINS_MUX(12, 80, 137);
1214 IRQC_PINS_MUX(13, 81, 145);
1215 IRQC_PINS_MUX(14, 82, 146);
1216 IRQC_PINS_MUX(15, 83, 147);
1217 IRQC_PINS_MUX(16, 84, 170);
1218 IRQC_PIN_MUX(17, 85);
1219 IRQC_PIN_MUX(18, 86);
1220 IRQC_PIN_MUX(19, 87);
1221 IRQC_PIN_MUX(20, 92);
1222 IRQC_PIN_MUX(21, 93);
1223 IRQC_PIN_MUX(22, 94);
1224 IRQC_PIN_MUX(23, 95);
1225 IRQC_PIN_MUX(24, 112);
1226 IRQC_PIN_MUX(25, 119);
1227 IRQC_PINS_MUX(26, 121, 172);
1228 IRQC_PINS_MUX(27, 122, 180);
1229 IRQC_PINS_MUX(28, 123, 181);
1230 IRQC_PINS_MUX(29, 129, 182);
1231 IRQC_PINS_MUX(30, 130, 183);
1232 IRQC_PINS_MUX(31, 138, 184);
1233 /* - KEYSC ------------------------------------------------------------------ */
1234 static const unsigned int keysc_in04_0_pins[] = {
1235 /* KEYIN[0:4] */
1236 136, 135, 134, 133, 132,
1237 };
1238 static const unsigned int keysc_in04_0_mux[] = {
1239 KEYIN0_136_MARK, KEYIN1_135_MARK, KEYIN2_134_MARK, KEYIN3_133_MARK,
1240 KEYIN4_MARK,
1241 };
1242 static const unsigned int keysc_in04_1_pins[] = {
1243 /* KEYIN[0:4] */
1244 121, 122, 123, 124, 132,
1245 };
1246 static const unsigned int keysc_in04_1_mux[] = {
1247 KEYIN0_121_MARK, KEYIN1_122_MARK, KEYIN2_123_MARK, KEYIN3_124_MARK,
1248 KEYIN4_MARK,
1249 };
1250 static const unsigned int keysc_in5_pins[] = {
1251 /* KEYIN5 */
1252 131,
1253 };
1254 static const unsigned int keysc_in5_mux[] = {
1255 KEYIN5_MARK,
1256 };
1257 static const unsigned int keysc_in6_pins[] = {
1258 /* KEYIN6 */
1259 130,
1260 };
1261 static const unsigned int keysc_in6_mux[] = {
1262 KEYIN6_MARK,
1263 };
1264 static const unsigned int keysc_in7_pins[] = {
1265 /* KEYIN7 */
1266 129,
1267 };
1268 static const unsigned int keysc_in7_mux[] = {
1269 KEYIN7_MARK,
1270 };
1271 static const unsigned int keysc_out4_pins[] = {
1272 /* KEYOUT[0:3] */
1273 128, 127, 126, 125,
1274 };
1275 static const unsigned int keysc_out4_mux[] = {
1276 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
1277 };
1278 static const unsigned int keysc_out5_pins[] = {
1279 /* KEYOUT[0:4] */
1280 128, 127, 126, 125, 124,
1281 };
1282 static const unsigned int keysc_out5_mux[] = {
1283 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
1284 KEYOUT4_MARK,
1285 };
1286 static const unsigned int keysc_out6_pins[] = {
1287 /* KEYOUT[0:5] */
1288 128, 127, 126, 125, 124, 123,
1289 };
1290 static const unsigned int keysc_out6_mux[] = {
1291 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
1292 KEYOUT4_MARK, KEYOUT5_MARK,
1293 };
1294 static const unsigned int keysc_out8_pins[] = {
1295 /* KEYOUT[0:7] */
1296 128, 127, 126, 125, 124, 123, 122, 121,
1297 };
1298 static const unsigned int keysc_out8_mux[] = {
1299 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
1300 KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
1301 };
1302 /* - LCD -------------------------------------------------------------------- */
1303 static const unsigned int lcd_data8_pins[] = {
1304 /* D[0:7] */
1305 121, 122, 123, 124, 125, 126, 127, 128,
1306 };
1307 static const unsigned int lcd_data8_mux[] = {
1308 /* LCDC */
1309 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1310 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1311 };
1312 static const unsigned int lcd_data9_pins[] = {
1313 /* D[0:8] */
1314 121, 122, 123, 124, 125, 126, 127, 128,
1315 129,
1316 137, 138, 139, 140, 141, 142, 143, 144,
1317 };
1318 static const unsigned int lcd_data9_mux[] = {
1319 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1320 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1321 LCDD8_MARK,
1322 };
1323 static const unsigned int lcd_data12_pins[] = {
1324 /* D[0:11] */
1325 121, 122, 123, 124, 125, 126, 127, 128,
1326 129, 130, 131, 132,
1327 };
1328 static const unsigned int lcd_data12_mux[] = {
1329 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1330 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1331 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1332 };
1333 static const unsigned int lcd_data16_pins[] = {
1334 /* D[0:15] */
1335 121, 122, 123, 124, 125, 126, 127, 128,
1336 129, 130, 131, 132, 133, 134, 135, 136,
1337 };
1338 static const unsigned int lcd_data16_mux[] = {
1339 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1340 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1341 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1342 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1343 };
1344 static const unsigned int lcd_data18_pins[] = {
1345 /* D[0:17] */
1346 121, 122, 123, 124, 125, 126, 127, 128,
1347 129, 130, 131, 132, 133, 134, 135, 136,
1348 137, 138,
1349 };
1350 static const unsigned int lcd_data18_mux[] = {
1351 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1352 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1353 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1354 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1355 LCDD16_MARK, LCDD17_MARK,
1356 };
1357 static const unsigned int lcd_data24_pins[] = {
1358 /* D[0:23] */
1359 121, 122, 123, 124, 125, 126, 127, 128,
1360 129, 130, 131, 132, 133, 134, 135, 136,
1361 137, 138, 139, 140, 141, 142, 143, 144,
1362 };
1363 static const unsigned int lcd_data24_mux[] = {
1364 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1365 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1366 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1367 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1368 LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
1369 LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
1370 };
1371 static const unsigned int lcd_display_pins[] = {
1372 /* DON */
1373 151,
1374 };
1375 static const unsigned int lcd_display_mux[] = {
1376 LCDDON_MARK,
1377 };
1378 static const unsigned int lcd_lclk_pins[] = {
1379 /* LCLK */
1380 150,
1381 };
1382 static const unsigned int lcd_lclk_mux[] = {
1383 LCDLCLK_MARK,
1384 };
1385 static const unsigned int lcd_sync_pins[] = {
1386 /* VSYN, HSYN, DCK, DISP */
1387 146, 145, 147, 149,
1388 };
1389 static const unsigned int lcd_sync_mux[] = {
1390 LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK,
1391 };
1392 static const unsigned int lcd_sys_pins[] = {
1393 /* CS, WR, RD, RS */
1394 145, 147, 148, 149,
1395 };
1396 static const unsigned int lcd_sys_mux[] = {
1397 LCDCS_MARK, LCDWR_MARK, LCDRD_MARK, LCDRS_MARK,
1398 };
1399 /* - MMCIF ------------------------------------------------------------------ */
1400 static const unsigned int mmc0_data1_0_pins[] = {
1401 /* D[0] */
1402 84,
1403 };
1404 static const unsigned int mmc0_data1_0_mux[] = {
1405 MMCD0_0_MARK,
1406 };
1407 static const unsigned int mmc0_data4_0_pins[] = {
1408 /* D[0:3] */
1409 84, 85, 86, 87,
1410 };
1411 static const unsigned int mmc0_data4_0_mux[] = {
1412 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
1413 };
1414 static const unsigned int mmc0_data8_0_pins[] = {
1415 /* D[0:7] */
1416 84, 85, 86, 87, 88, 89, 90, 91,
1417 };
1418 static const unsigned int mmc0_data8_0_mux[] = {
1419 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
1420 MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
1421 };
1422 static const unsigned int mmc0_ctrl_0_pins[] = {
1423 /* CMD, CLK */
1424 92, 99,
1425 };
1426 static const unsigned int mmc0_ctrl_0_mux[] = {
1427 MMCCMD0_MARK, MMCCLK0_MARK,
1428 };
1429
1430 static const unsigned int mmc0_data1_1_pins[] = {
1431 /* D[0] */
1432 54,
1433 };
1434 static const unsigned int mmc0_data1_1_mux[] = {
1435 MMCD1_0_MARK,
1436 };
1437 static const unsigned int mmc0_data4_1_pins[] = {
1438 /* D[0:3] */
1439 54, 55, 56, 57,
1440 };
1441 static const unsigned int mmc0_data4_1_mux[] = {
1442 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
1443 };
1444 static const unsigned int mmc0_data8_1_pins[] = {
1445 /* D[0:7] */
1446 54, 55, 56, 57, 58, 59, 60, 61,
1447 };
1448 static const unsigned int mmc0_data8_1_mux[] = {
1449 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
1450 MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
1451 };
1452 static const unsigned int mmc0_ctrl_1_pins[] = {
1453 /* CMD, CLK */
1454 67, 66,
1455 };
1456 static const unsigned int mmc0_ctrl_1_mux[] = {
1457 MMCCMD1_MARK, MMCCLK1_MARK,
1458 };
1459 /* - SCIFA0 ----------------------------------------------------------------- */
1460 static const unsigned int scifa0_data_pins[] = {
1461 /* RXD, TXD */
1462 153, 152,
1463 };
1464 static const unsigned int scifa0_data_mux[] = {
1465 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
1466 };
1467 static const unsigned int scifa0_clk_pins[] = {
1468 /* SCK */
1469 156,
1470 };
1471 static const unsigned int scifa0_clk_mux[] = {
1472 SCIFA0_SCK_MARK,
1473 };
1474 static const unsigned int scifa0_ctrl_pins[] = {
1475 /* RTS, CTS */
1476 157, 158,
1477 };
1478 static const unsigned int scifa0_ctrl_mux[] = {
1479 SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
1480 };
1481 /* - SCIFA1 ----------------------------------------------------------------- */
1482 static const unsigned int scifa1_data_pins[] = {
1483 /* RXD, TXD */
1484 155, 154,
1485 };
1486 static const unsigned int scifa1_data_mux[] = {
1487 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
1488 };
1489 static const unsigned int scifa1_clk_pins[] = {
1490 /* SCK */
1491 159,
1492 };
1493 static const unsigned int scifa1_clk_mux[] = {
1494 SCIFA1_SCK_MARK,
1495 };
1496 static const unsigned int scifa1_ctrl_pins[] = {
1497 /* RTS, CTS */
1498 160, 161,
1499 };
1500 static const unsigned int scifa1_ctrl_mux[] = {
1501 SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
1502 };
1503 /* - SCIFA2 ----------------------------------------------------------------- */
1504 static const unsigned int scifa2_data_pins[] = {
1505 /* RXD, TXD */
1506 97, 96,
1507 };
1508 static const unsigned int scifa2_data_mux[] = {
1509 SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK,
1510 };
1511 static const unsigned int scifa2_clk_pins[] = {
1512 /* SCK */
1513 98,
1514 };
1515 static const unsigned int scifa2_clk_mux[] = {
1516 SCIFA2_SCK1_MARK,
1517 };
1518 static const unsigned int scifa2_ctrl_pins[] = {
1519 /* RTS, CTS */
1520 95, 94,
1521 };
1522 static const unsigned int scifa2_ctrl_mux[] = {
1523 SCIFA2_RTS1_MARK, SCIFA2_CTS1_MARK,
1524 };
1525 /* - SCIFA3 ----------------------------------------------------------------- */
1526 static const unsigned int scifa3_data_pins[] = {
1527 /* RXD, TXD */
1528 144, 143,
1529 };
1530 static const unsigned int scifa3_data_mux[] = {
1531 SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
1532 };
1533 static const unsigned int scifa3_clk_pins[] = {
1534 /* SCK */
1535 142,
1536 };
1537 static const unsigned int scifa3_clk_mux[] = {
1538 SCIFA3_SCK_MARK,
1539 };
1540 static const unsigned int scifa3_ctrl_0_pins[] = {
1541 /* RTS, CTS */
1542 44, 43,
1543 };
1544 static const unsigned int scifa3_ctrl_0_mux[] = {
1545 SCIFA3_RTS_44_MARK, SCIFA3_CTS_43_MARK,
1546 };
1547 static const unsigned int scifa3_ctrl_1_pins[] = {
1548 /* RTS, CTS */
1549 141, 140,
1550 };
1551 static const unsigned int scifa3_ctrl_1_mux[] = {
1552 SCIFA3_RTS_141_MARK, SCIFA3_CTS_140_MARK,
1553 };
1554 /* - SCIFA4 ----------------------------------------------------------------- */
1555 static const unsigned int scifa4_data_pins[] = {
1556 /* RXD, TXD */
1557 5, 6,
1558 };
1559 static const unsigned int scifa4_data_mux[] = {
1560 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
1561 };
1562 /* - SCIFA5 ----------------------------------------------------------------- */
1563 static const unsigned int scifa5_data_pins[] = {
1564 /* RXD, TXD */
1565 8, 12,
1566 };
1567 static const unsigned int scifa5_data_mux[] = {
1568 SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
1569 };
1570 /* - SCIFB ------------------------------------------------------------------ */
1571 static const unsigned int scifb_data_pins[] = {
1572 /* RXD, TXD */
1573 166, 165,
1574 };
1575 static const unsigned int scifb_data_mux[] = {
1576 SCIFB_RXD_MARK, SCIFB_TXD_MARK,
1577 };
1578 static const unsigned int scifb_clk_pins[] = {
1579 /* SCK */
1580 162,
1581 };
1582 static const unsigned int scifb_clk_mux[] = {
1583 SCIFB_SCK_MARK,
1584 };
1585 static const unsigned int scifb_ctrl_pins[] = {
1586 /* RTS, CTS */
1587 163, 164,
1588 };
1589 static const unsigned int scifb_ctrl_mux[] = {
1590 SCIFB_RTS_MARK, SCIFB_CTS_MARK,
1591 };
1592 /* - SDHI0 ------------------------------------------------------------------ */
1593 static const unsigned int sdhi0_data1_pins[] = {
1594 /* D0 */
1595 173,
1596 };
1597 static const unsigned int sdhi0_data1_mux[] = {
1598 SDHID0_0_MARK,
1599 };
1600 static const unsigned int sdhi0_data4_pins[] = {
1601 /* D[0:3] */
1602 173, 174, 175, 176,
1603 };
1604 static const unsigned int sdhi0_data4_mux[] = {
1605 SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
1606 };
1607 static const unsigned int sdhi0_ctrl_pins[] = {
1608 /* CMD, CLK */
1609 177, 171,
1610 };
1611 static const unsigned int sdhi0_ctrl_mux[] = {
1612 SDHICMD0_MARK, SDHICLK0_MARK,
1613 };
1614 static const unsigned int sdhi0_cd_pins[] = {
1615 /* CD */
1616 172,
1617 };
1618 static const unsigned int sdhi0_cd_mux[] = {
1619 SDHICD0_MARK,
1620 };
1621 static const unsigned int sdhi0_wp_pins[] = {
1622 /* WP */
1623 178,
1624 };
1625 static const unsigned int sdhi0_wp_mux[] = {
1626 SDHIWP0_MARK,
1627 };
1628 /* - SDHI1 ------------------------------------------------------------------ */
1629 static const unsigned int sdhi1_data1_pins[] = {
1630 /* D0 */
1631 180,
1632 };
1633 static const unsigned int sdhi1_data1_mux[] = {
1634 SDHID1_0_MARK,
1635 };
1636 static const unsigned int sdhi1_data4_pins[] = {
1637 /* D[0:3] */
1638 180, 181, 182, 183,
1639 };
1640 static const unsigned int sdhi1_data4_mux[] = {
1641 SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
1642 };
1643 static const unsigned int sdhi1_ctrl_pins[] = {
1644 /* CMD, CLK */
1645 184, 179,
1646 };
1647 static const unsigned int sdhi1_ctrl_mux[] = {
1648 SDHICMD1_MARK, SDHICLK1_MARK,
1649 };
1650
1651 static const unsigned int sdhi2_data1_pins[] = {
1652 /* D0 */
1653 186,
1654 };
1655 static const unsigned int sdhi2_data1_mux[] = {
1656 SDHID2_0_MARK,
1657 };
1658 static const unsigned int sdhi2_data4_pins[] = {
1659 /* D[0:3] */
1660 186, 187, 188, 189,
1661 };
1662 static const unsigned int sdhi2_data4_mux[] = {
1663 SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
1664 };
1665 static const unsigned int sdhi2_ctrl_pins[] = {
1666 /* CMD, CLK */
1667 190, 185,
1668 };
1669 static const unsigned int sdhi2_ctrl_mux[] = {
1670 SDHICMD2_MARK, SDHICLK2_MARK,
1671 };
1672 /* - USB0 ------------------------------------------------------------------- */
1673 static const unsigned int usb0_vbus_pins[] = {
1674 /* VBUS */
1675 167,
1676 };
1677 static const unsigned int usb0_vbus_mux[] = {
1678 VBUS0_0_MARK,
1679 };
1680 static const unsigned int usb0_otg_id_pins[] = {
1681 /* IDIN */
1682 113,
1683 };
1684 static const unsigned int usb0_otg_id_mux[] = {
1685 IDIN_0_MARK,
1686 };
1687 static const unsigned int usb0_otg_ctrl_pins[] = {
1688 /* PWEN, EXTLP, OVCN, OVCN2 */
1689 116, 114, 117, 115,
1690 };
1691 static const unsigned int usb0_otg_ctrl_mux[] = {
1692 PWEN_0_MARK, EXTLP_0_MARK, OVCN_0_MARK, OVCN2_0_MARK,
1693 };
1694 /* - USB1 ------------------------------------------------------------------- */
1695 static const unsigned int usb1_vbus_pins[] = {
1696 /* VBUS */
1697 168,
1698 };
1699 static const unsigned int usb1_vbus_mux[] = {
1700 VBUS0_1_MARK,
1701 };
1702 static const unsigned int usb1_otg_id_0_pins[] = {
1703 /* IDIN */
1704 113,
1705 };
1706 static const unsigned int usb1_otg_id_0_mux[] = {
1707 IDIN_1_113_MARK,
1708 };
1709 static const unsigned int usb1_otg_id_1_pins[] = {
1710 /* IDIN */
1711 18,
1712 };
1713 static const unsigned int usb1_otg_id_1_mux[] = {
1714 IDIN_1_18_MARK,
1715 };
1716 static const unsigned int usb1_otg_ctrl_0_pins[] = {
1717 /* PWEN, EXTLP, OVCN, OVCN2 */
1718 115, 116, 114, 117, 113,
1719 };
1720 static const unsigned int usb1_otg_ctrl_0_mux[] = {
1721 PWEN_1_115_MARK, EXTLP_1_MARK, OVCN_1_114_MARK, OVCN2_1_MARK,
1722 };
1723 static const unsigned int usb1_otg_ctrl_1_pins[] = {
1724 /* PWEN, EXTLP, OVCN, OVCN2 */
1725 138, 116, 162, 117, 18,
1726 };
1727 static const unsigned int usb1_otg_ctrl_1_mux[] = {
1728 PWEN_1_138_MARK, EXTLP_1_MARK, OVCN_1_162_MARK, OVCN2_1_MARK,
1729 };
1730
1731 static const struct sh_pfc_pin_group pinmux_groups[] = {
1732 SH_PFC_PIN_GROUP(bsc_data8),
1733 SH_PFC_PIN_GROUP(bsc_data16),
1734 SH_PFC_PIN_GROUP(bsc_cs0),
1735 SH_PFC_PIN_GROUP(bsc_cs2),
1736 SH_PFC_PIN_GROUP(bsc_cs4),
1737 SH_PFC_PIN_GROUP(bsc_cs5a),
1738 SH_PFC_PIN_GROUP(bsc_cs5b),
1739 SH_PFC_PIN_GROUP(bsc_cs6a),
1740 SH_PFC_PIN_GROUP(bsc_rd_we8),
1741 SH_PFC_PIN_GROUP(bsc_rd_we16),
1742 SH_PFC_PIN_GROUP(bsc_bs),
1743 SH_PFC_PIN_GROUP(bsc_rdwr),
1744 SH_PFC_PIN_GROUP(ceu_data_0_7),
1745 SH_PFC_PIN_GROUP(ceu_data_8_15),
1746 SH_PFC_PIN_GROUP(ceu_clk_0),
1747 SH_PFC_PIN_GROUP(ceu_clk_1),
1748 SH_PFC_PIN_GROUP(ceu_clk_2),
1749 SH_PFC_PIN_GROUP(ceu_sync),
1750 SH_PFC_PIN_GROUP(ceu_field),
1751 SH_PFC_PIN_GROUP(flctl_data),
1752 SH_PFC_PIN_GROUP(flctl_ce0),
1753 SH_PFC_PIN_GROUP(flctl_ce1),
1754 SH_PFC_PIN_GROUP(flctl_ctrl),
1755 SH_PFC_PIN_GROUP(fsia_mclk_in),
1756 SH_PFC_PIN_GROUP(fsia_mclk_out),
1757 SH_PFC_PIN_GROUP(fsia_sclk_in),
1758 SH_PFC_PIN_GROUP(fsia_sclk_out),
1759 SH_PFC_PIN_GROUP(fsia_data_in),
1760 SH_PFC_PIN_GROUP(fsia_data_out),
1761 SH_PFC_PIN_GROUP(fsia_spdif_0),
1762 SH_PFC_PIN_GROUP(fsia_spdif_1),
1763 SH_PFC_PIN_GROUP(fsib_mclk_in),
1764 SH_PFC_PIN_GROUP(hdmi),
1765 SH_PFC_PIN_GROUP(intc_irq0_0),
1766 SH_PFC_PIN_GROUP(intc_irq0_1),
1767 SH_PFC_PIN_GROUP(intc_irq1),
1768 SH_PFC_PIN_GROUP(intc_irq2_0),
1769 SH_PFC_PIN_GROUP(intc_irq2_1),
1770 SH_PFC_PIN_GROUP(intc_irq3_0),
1771 SH_PFC_PIN_GROUP(intc_irq3_1),
1772 SH_PFC_PIN_GROUP(intc_irq4_0),
1773 SH_PFC_PIN_GROUP(intc_irq4_1),
1774 SH_PFC_PIN_GROUP(intc_irq5),
1775 SH_PFC_PIN_GROUP(intc_irq6_0),
1776 SH_PFC_PIN_GROUP(intc_irq6_1),
1777 SH_PFC_PIN_GROUP(intc_irq7_0),
1778 SH_PFC_PIN_GROUP(intc_irq7_1),
1779 SH_PFC_PIN_GROUP(intc_irq8_0),
1780 SH_PFC_PIN_GROUP(intc_irq8_1),
1781 SH_PFC_PIN_GROUP(intc_irq9_0),
1782 SH_PFC_PIN_GROUP(intc_irq9_1),
1783 SH_PFC_PIN_GROUP(intc_irq10),
1784 SH_PFC_PIN_GROUP(intc_irq11),
1785 SH_PFC_PIN_GROUP(intc_irq12_0),
1786 SH_PFC_PIN_GROUP(intc_irq12_1),
1787 SH_PFC_PIN_GROUP(intc_irq13_0),
1788 SH_PFC_PIN_GROUP(intc_irq13_1),
1789 SH_PFC_PIN_GROUP(intc_irq14_0),
1790 SH_PFC_PIN_GROUP(intc_irq14_1),
1791 SH_PFC_PIN_GROUP(intc_irq15_0),
1792 SH_PFC_PIN_GROUP(intc_irq15_1),
1793 SH_PFC_PIN_GROUP(intc_irq16_0),
1794 SH_PFC_PIN_GROUP(intc_irq16_1),
1795 SH_PFC_PIN_GROUP(intc_irq17),
1796 SH_PFC_PIN_GROUP(intc_irq18),
1797 SH_PFC_PIN_GROUP(intc_irq19),
1798 SH_PFC_PIN_GROUP(intc_irq20),
1799 SH_PFC_PIN_GROUP(intc_irq21),
1800 SH_PFC_PIN_GROUP(intc_irq22),
1801 SH_PFC_PIN_GROUP(intc_irq23),
1802 SH_PFC_PIN_GROUP(intc_irq24),
1803 SH_PFC_PIN_GROUP(intc_irq25),
1804 SH_PFC_PIN_GROUP(intc_irq26_0),
1805 SH_PFC_PIN_GROUP(intc_irq26_1),
1806 SH_PFC_PIN_GROUP(intc_irq27_0),
1807 SH_PFC_PIN_GROUP(intc_irq27_1),
1808 SH_PFC_PIN_GROUP(intc_irq28_0),
1809 SH_PFC_PIN_GROUP(intc_irq28_1),
1810 SH_PFC_PIN_GROUP(intc_irq29_0),
1811 SH_PFC_PIN_GROUP(intc_irq29_1),
1812 SH_PFC_PIN_GROUP(intc_irq30_0),
1813 SH_PFC_PIN_GROUP(intc_irq30_1),
1814 SH_PFC_PIN_GROUP(intc_irq31_0),
1815 SH_PFC_PIN_GROUP(intc_irq31_1),
1816 SH_PFC_PIN_GROUP(keysc_in04_0),
1817 SH_PFC_PIN_GROUP(keysc_in04_1),
1818 SH_PFC_PIN_GROUP(keysc_in5),
1819 SH_PFC_PIN_GROUP(keysc_in6),
1820 SH_PFC_PIN_GROUP(keysc_in7),
1821 SH_PFC_PIN_GROUP(keysc_out4),
1822 SH_PFC_PIN_GROUP(keysc_out5),
1823 SH_PFC_PIN_GROUP(keysc_out6),
1824 SH_PFC_PIN_GROUP(keysc_out8),
1825 SH_PFC_PIN_GROUP(lcd_data8),
1826 SH_PFC_PIN_GROUP(lcd_data9),
1827 SH_PFC_PIN_GROUP(lcd_data12),
1828 SH_PFC_PIN_GROUP(lcd_data16),
1829 SH_PFC_PIN_GROUP(lcd_data18),
1830 SH_PFC_PIN_GROUP(lcd_data24),
1831 SH_PFC_PIN_GROUP(lcd_display),
1832 SH_PFC_PIN_GROUP(lcd_lclk),
1833 SH_PFC_PIN_GROUP(lcd_sync),
1834 SH_PFC_PIN_GROUP(lcd_sys),
1835 SH_PFC_PIN_GROUP(mmc0_data1_0),
1836 SH_PFC_PIN_GROUP(mmc0_data4_0),
1837 SH_PFC_PIN_GROUP(mmc0_data8_0),
1838 SH_PFC_PIN_GROUP(mmc0_ctrl_0),
1839 SH_PFC_PIN_GROUP(mmc0_data1_1),
1840 SH_PFC_PIN_GROUP(mmc0_data4_1),
1841 SH_PFC_PIN_GROUP(mmc0_data8_1),
1842 SH_PFC_PIN_GROUP(mmc0_ctrl_1),
1843 SH_PFC_PIN_GROUP(scifa0_data),
1844 SH_PFC_PIN_GROUP(scifa0_clk),
1845 SH_PFC_PIN_GROUP(scifa0_ctrl),
1846 SH_PFC_PIN_GROUP(scifa1_data),
1847 SH_PFC_PIN_GROUP(scifa1_clk),
1848 SH_PFC_PIN_GROUP(scifa1_ctrl),
1849 SH_PFC_PIN_GROUP(scifa2_data),
1850 SH_PFC_PIN_GROUP(scifa2_clk),
1851 SH_PFC_PIN_GROUP(scifa2_ctrl),
1852 SH_PFC_PIN_GROUP(scifa3_data),
1853 SH_PFC_PIN_GROUP(scifa3_clk),
1854 SH_PFC_PIN_GROUP(scifa3_ctrl_0),
1855 SH_PFC_PIN_GROUP(scifa3_ctrl_1),
1856 SH_PFC_PIN_GROUP(scifa4_data),
1857 SH_PFC_PIN_GROUP(scifa5_data),
1858 SH_PFC_PIN_GROUP(scifb_data),
1859 SH_PFC_PIN_GROUP(scifb_clk),
1860 SH_PFC_PIN_GROUP(scifb_ctrl),
1861 SH_PFC_PIN_GROUP(sdhi0_data1),
1862 SH_PFC_PIN_GROUP(sdhi0_data4),
1863 SH_PFC_PIN_GROUP(sdhi0_ctrl),
1864 SH_PFC_PIN_GROUP(sdhi0_cd),
1865 SH_PFC_PIN_GROUP(sdhi0_wp),
1866 SH_PFC_PIN_GROUP(sdhi1_data1),
1867 SH_PFC_PIN_GROUP(sdhi1_data4),
1868 SH_PFC_PIN_GROUP(sdhi1_ctrl),
1869 SH_PFC_PIN_GROUP(sdhi2_data1),
1870 SH_PFC_PIN_GROUP(sdhi2_data4),
1871 SH_PFC_PIN_GROUP(sdhi2_ctrl),
1872 SH_PFC_PIN_GROUP(usb0_vbus),
1873 SH_PFC_PIN_GROUP(usb0_otg_id),
1874 SH_PFC_PIN_GROUP(usb0_otg_ctrl),
1875 SH_PFC_PIN_GROUP(usb1_vbus),
1876 SH_PFC_PIN_GROUP(usb1_otg_id_0),
1877 SH_PFC_PIN_GROUP(usb1_otg_id_1),
1878 SH_PFC_PIN_GROUP(usb1_otg_ctrl_0),
1879 SH_PFC_PIN_GROUP(usb1_otg_ctrl_1),
1880 };
1881
1882 static const char * const bsc_groups[] = {
1883 "bsc_data8",
1884 "bsc_data16",
1885 "bsc_cs0",
1886 "bsc_cs2",
1887 "bsc_cs4",
1888 "bsc_cs5a",
1889 "bsc_cs5b",
1890 "bsc_cs6a",
1891 "bsc_rd_we8",
1892 "bsc_rd_we16",
1893 "bsc_bs",
1894 "bsc_rdwr",
1895 };
1896
1897 static const char * const ceu_groups[] = {
1898 "ceu_data_0_7",
1899 "ceu_data_8_15",
1900 "ceu_clk_0",
1901 "ceu_clk_1",
1902 "ceu_clk_2",
1903 "ceu_sync",
1904 "ceu_field",
1905 };
1906
1907 static const char * const flctl_groups[] = {
1908 "flctl_data",
1909 "flctl_ce0",
1910 "flctl_ce1",
1911 "flctl_ctrl",
1912 };
1913
1914 static const char * const fsia_groups[] = {
1915 "fsia_mclk_in",
1916 "fsia_mclk_out",
1917 "fsia_sclk_in",
1918 "fsia_sclk_out",
1919 "fsia_data_in",
1920 "fsia_data_out",
1921 "fsia_spdif_0",
1922 "fsia_spdif_1",
1923 };
1924
1925 static const char * const fsib_groups[] = {
1926 "fsib_mclk_in",
1927 };
1928
1929 static const char * const hdmi_groups[] = {
1930 "hdmi",
1931 };
1932
1933 static const char * const intc_groups[] = {
1934 "intc_irq0_0",
1935 "intc_irq0_1",
1936 "intc_irq1",
1937 "intc_irq2_0",
1938 "intc_irq2_1",
1939 "intc_irq3_0",
1940 "intc_irq3_1",
1941 "intc_irq4_0",
1942 "intc_irq4_1",
1943 "intc_irq5",
1944 "intc_irq6_0",
1945 "intc_irq6_1",
1946 "intc_irq7_0",
1947 "intc_irq7_1",
1948 "intc_irq8_0",
1949 "intc_irq8_1",
1950 "intc_irq9_0",
1951 "intc_irq9_1",
1952 "intc_irq10",
1953 "intc_irq11",
1954 "intc_irq12_0",
1955 "intc_irq12_1",
1956 "intc_irq13_0",
1957 "intc_irq13_1",
1958 "intc_irq14_0",
1959 "intc_irq14_1",
1960 "intc_irq15_0",
1961 "intc_irq15_1",
1962 "intc_irq16_0",
1963 "intc_irq16_1",
1964 "intc_irq17",
1965 "intc_irq18",
1966 "intc_irq19",
1967 "intc_irq20",
1968 "intc_irq21",
1969 "intc_irq22",
1970 "intc_irq23",
1971 "intc_irq24",
1972 "intc_irq25",
1973 "intc_irq26_0",
1974 "intc_irq26_1",
1975 "intc_irq27_0",
1976 "intc_irq27_1",
1977 "intc_irq28_0",
1978 "intc_irq28_1",
1979 "intc_irq29_0",
1980 "intc_irq29_1",
1981 "intc_irq30_0",
1982 "intc_irq30_1",
1983 "intc_irq31_0",
1984 "intc_irq31_1",
1985 };
1986
1987 static const char * const keysc_groups[] = {
1988 "keysc_in04_0",
1989 "keysc_in04_1",
1990 "keysc_in5",
1991 "keysc_in6",
1992 "keysc_in7",
1993 "keysc_out4",
1994 "keysc_out5",
1995 "keysc_out6",
1996 "keysc_out8",
1997 };
1998
1999 static const char * const lcd_groups[] = {
2000 "lcd_data8",
2001 "lcd_data9",
2002 "lcd_data12",
2003 "lcd_data16",
2004 "lcd_data18",
2005 "lcd_data24",
2006 "lcd_display",
2007 "lcd_lclk",
2008 "lcd_sync",
2009 "lcd_sys",
2010 };
2011
2012 static const char * const mmc0_groups[] = {
2013 "mmc0_data1_0",
2014 "mmc0_data4_0",
2015 "mmc0_data8_0",
2016 "mmc0_ctrl_0",
2017 "mmc0_data1_1",
2018 "mmc0_data4_1",
2019 "mmc0_data8_1",
2020 "mmc0_ctrl_1",
2021 };
2022
2023 static const char * const scifa0_groups[] = {
2024 "scifa0_data",
2025 "scifa0_clk",
2026 "scifa0_ctrl",
2027 };
2028
2029 static const char * const scifa1_groups[] = {
2030 "scifa1_data",
2031 "scifa1_clk",
2032 "scifa1_ctrl",
2033 };
2034
2035 static const char * const scifa2_groups[] = {
2036 "scifa2_data",
2037 "scifa2_clk",
2038 "scifa2_ctrl",
2039 };
2040
2041 static const char * const scifa3_groups[] = {
2042 "scifa3_data",
2043 "scifa3_clk",
2044 "scifa3_ctrl_0",
2045 "scifa3_ctrl_1",
2046 };
2047
2048 static const char * const scifa4_groups[] = {
2049 "scifa4_data",
2050 };
2051
2052 static const char * const scifa5_groups[] = {
2053 "scifa5_data",
2054 };
2055
2056 static const char * const scifb_groups[] = {
2057 "scifb_data",
2058 "scifb_clk",
2059 "scifb_ctrl",
2060 };
2061
2062 static const char * const sdhi0_groups[] = {
2063 "sdhi0_data1",
2064 "sdhi0_data4",
2065 "sdhi0_ctrl",
2066 "sdhi0_cd",
2067 "sdhi0_wp",
2068 };
2069
2070 static const char * const sdhi1_groups[] = {
2071 "sdhi1_data1",
2072 "sdhi1_data4",
2073 "sdhi1_ctrl",
2074 };
2075
2076 static const char * const sdhi2_groups[] = {
2077 "sdhi2_data1",
2078 "sdhi2_data4",
2079 "sdhi2_ctrl",
2080 };
2081
2082 static const char * const usb0_groups[] = {
2083 "usb0_vbus",
2084 "usb0_otg_id",
2085 "usb0_otg_ctrl",
2086 };
2087
2088 static const char * const usb1_groups[] = {
2089 "usb1_vbus",
2090 "usb1_otg_id_0",
2091 "usb1_otg_id_1",
2092 "usb1_otg_ctrl_0",
2093 "usb1_otg_ctrl_1",
2094 };
2095
2096 static const struct sh_pfc_function pinmux_functions[] = {
2097 SH_PFC_FUNCTION(bsc),
2098 SH_PFC_FUNCTION(ceu),
2099 SH_PFC_FUNCTION(flctl),
2100 SH_PFC_FUNCTION(fsia),
2101 SH_PFC_FUNCTION(fsib),
2102 SH_PFC_FUNCTION(hdmi),
2103 SH_PFC_FUNCTION(intc),
2104 SH_PFC_FUNCTION(keysc),
2105 SH_PFC_FUNCTION(lcd),
2106 SH_PFC_FUNCTION(mmc0),
2107 SH_PFC_FUNCTION(scifa0),
2108 SH_PFC_FUNCTION(scifa1),
2109 SH_PFC_FUNCTION(scifa2),
2110 SH_PFC_FUNCTION(scifa3),
2111 SH_PFC_FUNCTION(scifa4),
2112 SH_PFC_FUNCTION(scifa5),
2113 SH_PFC_FUNCTION(scifb),
2114 SH_PFC_FUNCTION(sdhi0),
2115 SH_PFC_FUNCTION(sdhi1),
2116 SH_PFC_FUNCTION(sdhi2),
2117 SH_PFC_FUNCTION(usb0),
2118 SH_PFC_FUNCTION(usb1),
2119 };
2120
2121 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2122 PORTCR(0, 0xE6051000), /* PORT0CR */
2123 PORTCR(1, 0xE6051001), /* PORT1CR */
2124 PORTCR(2, 0xE6051002), /* PORT2CR */
2125 PORTCR(3, 0xE6051003), /* PORT3CR */
2126 PORTCR(4, 0xE6051004), /* PORT4CR */
2127 PORTCR(5, 0xE6051005), /* PORT5CR */
2128 PORTCR(6, 0xE6051006), /* PORT6CR */
2129 PORTCR(7, 0xE6051007), /* PORT7CR */
2130 PORTCR(8, 0xE6051008), /* PORT8CR */
2131 PORTCR(9, 0xE6051009), /* PORT9CR */
2132 PORTCR(10, 0xE605100A), /* PORT10CR */
2133 PORTCR(11, 0xE605100B), /* PORT11CR */
2134 PORTCR(12, 0xE605100C), /* PORT12CR */
2135 PORTCR(13, 0xE605100D), /* PORT13CR */
2136 PORTCR(14, 0xE605100E), /* PORT14CR */
2137 PORTCR(15, 0xE605100F), /* PORT15CR */
2138 PORTCR(16, 0xE6051010), /* PORT16CR */
2139 PORTCR(17, 0xE6051011), /* PORT17CR */
2140 PORTCR(18, 0xE6051012), /* PORT18CR */
2141 PORTCR(19, 0xE6051013), /* PORT19CR */
2142 PORTCR(20, 0xE6051014), /* PORT20CR */
2143 PORTCR(21, 0xE6051015), /* PORT21CR */
2144 PORTCR(22, 0xE6051016), /* PORT22CR */
2145 PORTCR(23, 0xE6051017), /* PORT23CR */
2146 PORTCR(24, 0xE6051018), /* PORT24CR */
2147 PORTCR(25, 0xE6051019), /* PORT25CR */
2148 PORTCR(26, 0xE605101A), /* PORT26CR */
2149 PORTCR(27, 0xE605101B), /* PORT27CR */
2150 PORTCR(28, 0xE605101C), /* PORT28CR */
2151 PORTCR(29, 0xE605101D), /* PORT29CR */
2152 PORTCR(30, 0xE605101E), /* PORT30CR */
2153 PORTCR(31, 0xE605101F), /* PORT31CR */
2154 PORTCR(32, 0xE6051020), /* PORT32CR */
2155 PORTCR(33, 0xE6051021), /* PORT33CR */
2156 PORTCR(34, 0xE6051022), /* PORT34CR */
2157 PORTCR(35, 0xE6051023), /* PORT35CR */
2158 PORTCR(36, 0xE6051024), /* PORT36CR */
2159 PORTCR(37, 0xE6051025), /* PORT37CR */
2160 PORTCR(38, 0xE6051026), /* PORT38CR */
2161 PORTCR(39, 0xE6051027), /* PORT39CR */
2162 PORTCR(40, 0xE6051028), /* PORT40CR */
2163 PORTCR(41, 0xE6051029), /* PORT41CR */
2164 PORTCR(42, 0xE605102A), /* PORT42CR */
2165 PORTCR(43, 0xE605102B), /* PORT43CR */
2166 PORTCR(44, 0xE605102C), /* PORT44CR */
2167 PORTCR(45, 0xE605102D), /* PORT45CR */
2168 PORTCR(46, 0xE605202E), /* PORT46CR */
2169 PORTCR(47, 0xE605202F), /* PORT47CR */
2170 PORTCR(48, 0xE6052030), /* PORT48CR */
2171 PORTCR(49, 0xE6052031), /* PORT49CR */
2172 PORTCR(50, 0xE6052032), /* PORT50CR */
2173 PORTCR(51, 0xE6052033), /* PORT51CR */
2174 PORTCR(52, 0xE6052034), /* PORT52CR */
2175 PORTCR(53, 0xE6052035), /* PORT53CR */
2176 PORTCR(54, 0xE6052036), /* PORT54CR */
2177 PORTCR(55, 0xE6052037), /* PORT55CR */
2178 PORTCR(56, 0xE6052038), /* PORT56CR */
2179 PORTCR(57, 0xE6052039), /* PORT57CR */
2180 PORTCR(58, 0xE605203A), /* PORT58CR */
2181 PORTCR(59, 0xE605203B), /* PORT59CR */
2182 PORTCR(60, 0xE605203C), /* PORT60CR */
2183 PORTCR(61, 0xE605203D), /* PORT61CR */
2184 PORTCR(62, 0xE605203E), /* PORT62CR */
2185 PORTCR(63, 0xE605203F), /* PORT63CR */
2186 PORTCR(64, 0xE6052040), /* PORT64CR */
2187 PORTCR(65, 0xE6052041), /* PORT65CR */
2188 PORTCR(66, 0xE6052042), /* PORT66CR */
2189 PORTCR(67, 0xE6052043), /* PORT67CR */
2190 PORTCR(68, 0xE6052044), /* PORT68CR */
2191 PORTCR(69, 0xE6052045), /* PORT69CR */
2192 PORTCR(70, 0xE6052046), /* PORT70CR */
2193 PORTCR(71, 0xE6052047), /* PORT71CR */
2194 PORTCR(72, 0xE6052048), /* PORT72CR */
2195 PORTCR(73, 0xE6052049), /* PORT73CR */
2196 PORTCR(74, 0xE605204A), /* PORT74CR */
2197 PORTCR(75, 0xE605204B), /* PORT75CR */
2198 PORTCR(76, 0xE605004C), /* PORT76CR */
2199 PORTCR(77, 0xE605004D), /* PORT77CR */
2200 PORTCR(78, 0xE605004E), /* PORT78CR */
2201 PORTCR(79, 0xE605004F), /* PORT79CR */
2202 PORTCR(80, 0xE6050050), /* PORT80CR */
2203 PORTCR(81, 0xE6050051), /* PORT81CR */
2204 PORTCR(82, 0xE6050052), /* PORT82CR */
2205 PORTCR(83, 0xE6050053), /* PORT83CR */
2206 PORTCR(84, 0xE6050054), /* PORT84CR */
2207 PORTCR(85, 0xE6050055), /* PORT85CR */
2208 PORTCR(86, 0xE6050056), /* PORT86CR */
2209 PORTCR(87, 0xE6050057), /* PORT87CR */
2210 PORTCR(88, 0xE6050058), /* PORT88CR */
2211 PORTCR(89, 0xE6050059), /* PORT89CR */
2212 PORTCR(90, 0xE605005A), /* PORT90CR */
2213 PORTCR(91, 0xE605005B), /* PORT91CR */
2214 PORTCR(92, 0xE605005C), /* PORT92CR */
2215 PORTCR(93, 0xE605005D), /* PORT93CR */
2216 PORTCR(94, 0xE605005E), /* PORT94CR */
2217 PORTCR(95, 0xE605005F), /* PORT95CR */
2218 PORTCR(96, 0xE6050060), /* PORT96CR */
2219 PORTCR(97, 0xE6050061), /* PORT97CR */
2220 PORTCR(98, 0xE6050062), /* PORT98CR */
2221 PORTCR(99, 0xE6050063), /* PORT99CR */
2222 PORTCR(100, 0xE6053064), /* PORT100CR */
2223 PORTCR(101, 0xE6053065), /* PORT101CR */
2224 PORTCR(102, 0xE6053066), /* PORT102CR */
2225 PORTCR(103, 0xE6053067), /* PORT103CR */
2226 PORTCR(104, 0xE6053068), /* PORT104CR */
2227 PORTCR(105, 0xE6053069), /* PORT105CR */
2228 PORTCR(106, 0xE605306A), /* PORT106CR */
2229 PORTCR(107, 0xE605306B), /* PORT107CR */
2230 PORTCR(108, 0xE605306C), /* PORT108CR */
2231 PORTCR(109, 0xE605306D), /* PORT109CR */
2232 PORTCR(110, 0xE605306E), /* PORT110CR */
2233 PORTCR(111, 0xE605306F), /* PORT111CR */
2234 PORTCR(112, 0xE6053070), /* PORT112CR */
2235 PORTCR(113, 0xE6053071), /* PORT113CR */
2236 PORTCR(114, 0xE6053072), /* PORT114CR */
2237 PORTCR(115, 0xE6053073), /* PORT115CR */
2238 PORTCR(116, 0xE6053074), /* PORT116CR */
2239 PORTCR(117, 0xE6053075), /* PORT117CR */
2240 PORTCR(118, 0xE6053076), /* PORT118CR */
2241 PORTCR(119, 0xE6053077), /* PORT119CR */
2242 PORTCR(120, 0xE6053078), /* PORT120CR */
2243 PORTCR(121, 0xE6050079), /* PORT121CR */
2244 PORTCR(122, 0xE605007A), /* PORT122CR */
2245 PORTCR(123, 0xE605007B), /* PORT123CR */
2246 PORTCR(124, 0xE605007C), /* PORT124CR */
2247 PORTCR(125, 0xE605007D), /* PORT125CR */
2248 PORTCR(126, 0xE605007E), /* PORT126CR */
2249 PORTCR(127, 0xE605007F), /* PORT127CR */
2250 PORTCR(128, 0xE6050080), /* PORT128CR */
2251 PORTCR(129, 0xE6050081), /* PORT129CR */
2252 PORTCR(130, 0xE6050082), /* PORT130CR */
2253 PORTCR(131, 0xE6050083), /* PORT131CR */
2254 PORTCR(132, 0xE6050084), /* PORT132CR */
2255 PORTCR(133, 0xE6050085), /* PORT133CR */
2256 PORTCR(134, 0xE6050086), /* PORT134CR */
2257 PORTCR(135, 0xE6050087), /* PORT135CR */
2258 PORTCR(136, 0xE6050088), /* PORT136CR */
2259 PORTCR(137, 0xE6050089), /* PORT137CR */
2260 PORTCR(138, 0xE605008A), /* PORT138CR */
2261 PORTCR(139, 0xE605008B), /* PORT139CR */
2262 PORTCR(140, 0xE605008C), /* PORT140CR */
2263 PORTCR(141, 0xE605008D), /* PORT141CR */
2264 PORTCR(142, 0xE605008E), /* PORT142CR */
2265 PORTCR(143, 0xE605008F), /* PORT143CR */
2266 PORTCR(144, 0xE6050090), /* PORT144CR */
2267 PORTCR(145, 0xE6050091), /* PORT145CR */
2268 PORTCR(146, 0xE6050092), /* PORT146CR */
2269 PORTCR(147, 0xE6050093), /* PORT147CR */
2270 PORTCR(148, 0xE6050094), /* PORT148CR */
2271 PORTCR(149, 0xE6050095), /* PORT149CR */
2272 PORTCR(150, 0xE6050096), /* PORT150CR */
2273 PORTCR(151, 0xE6050097), /* PORT151CR */
2274 PORTCR(152, 0xE6053098), /* PORT152CR */
2275 PORTCR(153, 0xE6053099), /* PORT153CR */
2276 PORTCR(154, 0xE605309A), /* PORT154CR */
2277 PORTCR(155, 0xE605309B), /* PORT155CR */
2278 PORTCR(156, 0xE605009C), /* PORT156CR */
2279 PORTCR(157, 0xE605009D), /* PORT157CR */
2280 PORTCR(158, 0xE605009E), /* PORT158CR */
2281 PORTCR(159, 0xE605009F), /* PORT159CR */
2282 PORTCR(160, 0xE60500A0), /* PORT160CR */
2283 PORTCR(161, 0xE60500A1), /* PORT161CR */
2284 PORTCR(162, 0xE60500A2), /* PORT162CR */
2285 PORTCR(163, 0xE60500A3), /* PORT163CR */
2286 PORTCR(164, 0xE60500A4), /* PORT164CR */
2287 PORTCR(165, 0xE60500A5), /* PORT165CR */
2288 PORTCR(166, 0xE60500A6), /* PORT166CR */
2289 PORTCR(167, 0xE60520A7), /* PORT167CR */
2290 PORTCR(168, 0xE60520A8), /* PORT168CR */
2291 PORTCR(169, 0xE60520A9), /* PORT169CR */
2292 PORTCR(170, 0xE60520AA), /* PORT170CR */
2293 PORTCR(171, 0xE60520AB), /* PORT171CR */
2294 PORTCR(172, 0xE60520AC), /* PORT172CR */
2295 PORTCR(173, 0xE60520AD), /* PORT173CR */
2296 PORTCR(174, 0xE60520AE), /* PORT174CR */
2297 PORTCR(175, 0xE60520AF), /* PORT175CR */
2298 PORTCR(176, 0xE60520B0), /* PORT176CR */
2299 PORTCR(177, 0xE60520B1), /* PORT177CR */
2300 PORTCR(178, 0xE60520B2), /* PORT178CR */
2301 PORTCR(179, 0xE60520B3), /* PORT179CR */
2302 PORTCR(180, 0xE60520B4), /* PORT180CR */
2303 PORTCR(181, 0xE60520B5), /* PORT181CR */
2304 PORTCR(182, 0xE60520B6), /* PORT182CR */
2305 PORTCR(183, 0xE60520B7), /* PORT183CR */
2306 PORTCR(184, 0xE60520B8), /* PORT184CR */
2307 PORTCR(185, 0xE60520B9), /* PORT185CR */
2308 PORTCR(186, 0xE60520BA), /* PORT186CR */
2309 PORTCR(187, 0xE60520BB), /* PORT187CR */
2310 PORTCR(188, 0xE60520BC), /* PORT188CR */
2311 PORTCR(189, 0xE60520BD), /* PORT189CR */
2312 PORTCR(190, 0xE60520BE), /* PORT190CR */
2313
2314 { PINMUX_CFG_REG("MSEL1CR", 0xE605800C, 32, 1) {
2315 MSEL1CR_31_0, MSEL1CR_31_1,
2316 MSEL1CR_30_0, MSEL1CR_30_1,
2317 MSEL1CR_29_0, MSEL1CR_29_1,
2318 MSEL1CR_28_0, MSEL1CR_28_1,
2319 MSEL1CR_27_0, MSEL1CR_27_1,
2320 MSEL1CR_26_0, MSEL1CR_26_1,
2321 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2322 0, 0, 0, 0, 0, 0, 0, 0,
2323 MSEL1CR_16_0, MSEL1CR_16_1,
2324 MSEL1CR_15_0, MSEL1CR_15_1,
2325 MSEL1CR_14_0, MSEL1CR_14_1,
2326 MSEL1CR_13_0, MSEL1CR_13_1,
2327 MSEL1CR_12_0, MSEL1CR_12_1,
2328 0, 0, 0, 0,
2329 MSEL1CR_9_0, MSEL1CR_9_1,
2330 MSEL1CR_8_0, MSEL1CR_8_1,
2331 MSEL1CR_7_0, MSEL1CR_7_1,
2332 MSEL1CR_6_0, MSEL1CR_6_1,
2333 0, 0,
2334 MSEL1CR_4_0, MSEL1CR_4_1,
2335 MSEL1CR_3_0, MSEL1CR_3_1,
2336 MSEL1CR_2_0, MSEL1CR_2_1,
2337 0, 0,
2338 MSEL1CR_0_0, MSEL1CR_0_1,
2339 }
2340 },
2341 { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
2342 0, 0, 0, 0,
2343 0, 0, 0, 0,
2344 MSEL3CR_27_0, MSEL3CR_27_1,
2345 MSEL3CR_26_0, MSEL3CR_26_1,
2346 0, 0, 0, 0,
2347 0, 0, 0, 0,
2348 MSEL3CR_21_0, MSEL3CR_21_1,
2349 MSEL3CR_20_0, MSEL3CR_20_1,
2350 0, 0, 0, 0,
2351 0, 0, 0, 0,
2352 MSEL3CR_15_0, MSEL3CR_15_1,
2353 0, 0, 0, 0,
2354 0, 0, 0, 0,
2355 0, 0,
2356 MSEL3CR_9_0, MSEL3CR_9_1,
2357 0, 0, 0, 0,
2358 MSEL3CR_6_0, MSEL3CR_6_1,
2359 0, 0, 0, 0,
2360 0, 0, 0, 0,
2361 0, 0, 0, 0,
2362 }
2363 },
2364 { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
2365 0, 0, 0, 0,
2366 0, 0, 0, 0,
2367 0, 0, 0, 0,
2368 0, 0, 0, 0,
2369 0, 0, 0, 0,
2370 0, 0, 0, 0,
2371 MSEL4CR_19_0, MSEL4CR_19_1,
2372 MSEL4CR_18_0, MSEL4CR_18_1,
2373 MSEL4CR_17_0, MSEL4CR_17_1,
2374 MSEL4CR_16_0, MSEL4CR_16_1,
2375 MSEL4CR_15_0, MSEL4CR_15_1,
2376 MSEL4CR_14_0, MSEL4CR_14_1,
2377 0, 0, 0, 0,
2378 0, 0,
2379 MSEL4CR_10_0, MSEL4CR_10_1,
2380 0, 0, 0, 0,
2381 0, 0,
2382 MSEL4CR_6_0, MSEL4CR_6_1,
2383 0, 0,
2384 MSEL4CR_4_0, MSEL4CR_4_1,
2385 0, 0, 0, 0,
2386 MSEL4CR_1_0, MSEL4CR_1_1,
2387 0, 0,
2388 }
2389 },
2390 { },
2391 };
2392
2393 static const struct pinmux_data_reg pinmux_data_regs[] = {
2394 { PINMUX_DATA_REG("PORTL095_064DR", 0xE6054008, 32) {
2395 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
2396 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
2397 PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
2398 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
2399 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
2400 0, 0, 0, 0,
2401 0, 0, 0, 0,
2402 0, 0, 0, 0,
2403 }
2404 },
2405 { PINMUX_DATA_REG("PORTL127_096DR", 0xE605400C, 32) {
2406 PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
2407 PORT123_DATA, PORT122_DATA, PORT121_DATA, 0,
2408 0, 0, 0, 0,
2409 0, 0, 0, 0,
2410 0, 0, 0, 0,
2411 0, 0, 0, 0,
2412 0, 0, 0, 0,
2413 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA,
2414 }
2415 },
2416 { PINMUX_DATA_REG("PORTL159_128DR", 0xE6054010, 32) {
2417 PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
2418 0, 0, 0, 0,
2419 PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
2420 PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
2421 PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
2422 PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
2423 PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
2424 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA,
2425 }
2426 },
2427 { PINMUX_DATA_REG("PORTL191_160DR", 0xE6054014, 32) {
2428 0, 0, 0, 0,
2429 0, 0, 0, 0,
2430 0, 0, 0, 0,
2431 0, 0, 0, 0,
2432 0, 0, 0, 0,
2433 0, 0, 0, 0,
2434 0, PORT166_DATA, PORT165_DATA, PORT164_DATA,
2435 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA,
2436 }
2437 },
2438 { PINMUX_DATA_REG("PORTD031_000DR", 0xE6055000, 32) {
2439 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
2440 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
2441 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
2442 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
2443 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
2444 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
2445 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
2446 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA,
2447 }
2448 },
2449 { PINMUX_DATA_REG("PORTD063_032DR", 0xE6055004, 32) {
2450 0, 0, 0, 0, 0, 0, 0, 0,
2451 0, 0, 0, 0, 0, 0, 0, 0,
2452 0, 0, PORT45_DATA, PORT44_DATA,
2453 PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
2454 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
2455 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA,
2456 }
2457 },
2458 { PINMUX_DATA_REG("PORTR063_032DR", 0xE6056004, 32) {
2459 PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
2460 PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
2461 PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
2462 PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
2463 PORT47_DATA, PORT46_DATA, 0, 0,
2464 0, 0, 0, 0,
2465 0, 0, 0, 0,
2466 0, 0, 0, 0,
2467 }
2468 },
2469 { PINMUX_DATA_REG("PORTR095_064DR", 0xE6056008, 32) {
2470 0, 0, 0, 0,
2471 0, 0, 0, 0,
2472 0, 0, 0, 0,
2473 0, 0, 0, 0,
2474 0, 0, 0, 0,
2475 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
2476 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
2477 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA,
2478 }
2479 },
2480 { PINMUX_DATA_REG("PORTR191_160DR", 0xE6056014, 32) {
2481 0, PORT190_DATA, PORT189_DATA, PORT188_DATA,
2482 PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
2483 PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
2484 PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
2485 PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
2486 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
2487 PORT167_DATA, 0, 0, 0,
2488 0, 0, 0, 0,
2489 }
2490 },
2491 { PINMUX_DATA_REG("PORTU127_096DR", 0xE605700C, 32) {
2492 0, 0, 0, 0,
2493 0, 0, 0, PORT120_DATA,
2494 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
2495 PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
2496 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
2497 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
2498 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
2499 0, 0, 0, 0,
2500 }
2501 },
2502 { PINMUX_DATA_REG("PORTU159_128DR", 0xE6057010, 32) {
2503 0, 0, 0, 0,
2504 PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
2505 0, 0, 0, 0,
2506 0, 0, 0, 0,
2507 0, 0, 0, 0,
2508 0, 0, 0, 0,
2509 0, 0, 0, 0,
2510 0, 0, 0, 0,
2511 }
2512 },
2513 { },
2514 };
2515
2516 #define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5))
2517 #define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5))
2518 static const struct pinmux_irq pinmux_irqs[] = {
2519 PINMUX_IRQ(EXT_IRQ16L(0), 6, 162),
2520 PINMUX_IRQ(EXT_IRQ16L(1), 12),
2521 PINMUX_IRQ(EXT_IRQ16L(2), 4, 5),
2522 PINMUX_IRQ(EXT_IRQ16L(3), 8, 16),
2523 PINMUX_IRQ(EXT_IRQ16L(4), 17, 163),
2524 PINMUX_IRQ(EXT_IRQ16L(5), 18),
2525 PINMUX_IRQ(EXT_IRQ16L(6), 39, 164),
2526 PINMUX_IRQ(EXT_IRQ16L(7), 40, 167),
2527 PINMUX_IRQ(EXT_IRQ16L(8), 41, 168),
2528 PINMUX_IRQ(EXT_IRQ16L(9), 42, 169),
2529 PINMUX_IRQ(EXT_IRQ16L(10), 65),
2530 PINMUX_IRQ(EXT_IRQ16L(11), 67),
2531 PINMUX_IRQ(EXT_IRQ16L(12), 80, 137),
2532 PINMUX_IRQ(EXT_IRQ16L(13), 81, 145),
2533 PINMUX_IRQ(EXT_IRQ16L(14), 82, 146),
2534 PINMUX_IRQ(EXT_IRQ16L(15), 83, 147),
2535 PINMUX_IRQ(EXT_IRQ16H(16), 84, 170),
2536 PINMUX_IRQ(EXT_IRQ16H(17), 85),
2537 PINMUX_IRQ(EXT_IRQ16H(18), 86),
2538 PINMUX_IRQ(EXT_IRQ16H(19), 87),
2539 PINMUX_IRQ(EXT_IRQ16H(20), 92),
2540 PINMUX_IRQ(EXT_IRQ16H(21), 93),
2541 PINMUX_IRQ(EXT_IRQ16H(22), 94),
2542 PINMUX_IRQ(EXT_IRQ16H(23), 95),
2543 PINMUX_IRQ(EXT_IRQ16H(24), 112),
2544 PINMUX_IRQ(EXT_IRQ16H(25), 119),
2545 PINMUX_IRQ(EXT_IRQ16H(26), 121, 172),
2546 PINMUX_IRQ(EXT_IRQ16H(27), 122, 180),
2547 PINMUX_IRQ(EXT_IRQ16H(28), 123, 181),
2548 PINMUX_IRQ(EXT_IRQ16H(29), 129, 182),
2549 PINMUX_IRQ(EXT_IRQ16H(30), 130, 183),
2550 PINMUX_IRQ(EXT_IRQ16H(31), 138, 184),
2551 };
2552
2553 #define PORTnCR_PULMD_OFF (0 << 6)
2554 #define PORTnCR_PULMD_DOWN (2 << 6)
2555 #define PORTnCR_PULMD_UP (3 << 6)
2556 #define PORTnCR_PULMD_MASK (3 << 6)
2557
2558 struct sh7372_portcr_group {
2559 unsigned int end_pin;
2560 unsigned int offset;
2561 };
2562
2563 static const struct sh7372_portcr_group sh7372_portcr_offsets[] = {
2564 { 45, 0x1000 }, { 75, 0x2000 }, { 99, 0x0000 }, { 120, 0x3000 },
2565 { 151, 0x0000 }, { 155, 0x3000 }, { 166, 0x0000 }, { 190, 0x2000 },
2566 };
2567
sh7372_pinmux_portcr(struct sh_pfc * pfc,unsigned int pin)2568 static void __iomem *sh7372_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
2569 {
2570 unsigned int i;
2571
2572 for (i = 0; i < ARRAY_SIZE(sh7372_portcr_offsets); ++i) {
2573 const struct sh7372_portcr_group *group =
2574 &sh7372_portcr_offsets[i];
2575
2576 if (pin <= group->end_pin)
2577 return pfc->windows->virt + group->offset + pin;
2578 }
2579
2580 return NULL;
2581 }
2582
sh7372_pinmux_get_bias(struct sh_pfc * pfc,unsigned int pin)2583 static unsigned int sh7372_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
2584 {
2585 void __iomem *addr = sh7372_pinmux_portcr(pfc, pin);
2586 u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
2587
2588 switch (value) {
2589 case PORTnCR_PULMD_UP:
2590 return PIN_CONFIG_BIAS_PULL_UP;
2591 case PORTnCR_PULMD_DOWN:
2592 return PIN_CONFIG_BIAS_PULL_DOWN;
2593 case PORTnCR_PULMD_OFF:
2594 default:
2595 return PIN_CONFIG_BIAS_DISABLE;
2596 }
2597 }
2598
sh7372_pinmux_set_bias(struct sh_pfc * pfc,unsigned int pin,unsigned int bias)2599 static void sh7372_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
2600 unsigned int bias)
2601 {
2602 void __iomem *addr = sh7372_pinmux_portcr(pfc, pin);
2603 u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
2604
2605 switch (bias) {
2606 case PIN_CONFIG_BIAS_PULL_UP:
2607 value |= PORTnCR_PULMD_UP;
2608 break;
2609 case PIN_CONFIG_BIAS_PULL_DOWN:
2610 value |= PORTnCR_PULMD_DOWN;
2611 break;
2612 }
2613
2614 iowrite8(value, addr);
2615 }
2616
2617 static const struct sh_pfc_soc_operations sh7372_pfc_ops = {
2618 .get_bias = sh7372_pinmux_get_bias,
2619 .set_bias = sh7372_pinmux_set_bias,
2620 };
2621
2622 const struct sh_pfc_soc_info sh7372_pinmux_info = {
2623 .name = "sh7372_pfc",
2624 .ops = &sh7372_pfc_ops,
2625
2626 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2627 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2628 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2629
2630 .pins = pinmux_pins,
2631 .nr_pins = ARRAY_SIZE(pinmux_pins),
2632 .groups = pinmux_groups,
2633 .nr_groups = ARRAY_SIZE(pinmux_groups),
2634 .functions = pinmux_functions,
2635 .nr_functions = ARRAY_SIZE(pinmux_functions),
2636
2637 .cfg_regs = pinmux_config_regs,
2638 .data_regs = pinmux_data_regs,
2639
2640 .gpio_data = pinmux_data,
2641 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2642
2643 .gpio_irq = pinmux_irqs,
2644 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
2645 };
2646