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1 /*
2  * Copyright 2012 Alexandre Pereira da Silva <aletes.xgr@gmail.com>
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License as published by
6  * the Free Software Foundation; version 2.
7  *
8  */
9 
10 #include <linux/clk.h>
11 #include <linux/err.h>
12 #include <linux/io.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/platform_device.h>
18 #include <linux/pwm.h>
19 #include <linux/slab.h>
20 
21 struct lpc32xx_pwm_chip {
22 	struct pwm_chip chip;
23 	struct clk *clk;
24 	void __iomem *base;
25 };
26 
27 #define PWM_ENABLE	(1 << 31)
28 #define PWM_RELOADV(x)	(((x) & 0xFF) << 8)
29 #define PWM_DUTY(x)	((x) & 0xFF)
30 
31 #define to_lpc32xx_pwm_chip(_chip) \
32 	container_of(_chip, struct lpc32xx_pwm_chip, chip)
33 
lpc32xx_pwm_config(struct pwm_chip * chip,struct pwm_device * pwm,int duty_ns,int period_ns)34 static int lpc32xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
35 			      int duty_ns, int period_ns)
36 {
37 	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
38 	unsigned long long c;
39 	int period_cycles, duty_cycles;
40 	u32 val;
41 
42 	c = clk_get_rate(lpc32xx->clk) / 256;
43 	c = c * period_ns;
44 	do_div(c, NSEC_PER_SEC);
45 
46 	/* Handle high and low extremes */
47 	if (c == 0)
48 		c = 1;
49 	if (c > 255)
50 		c = 0; /* 0 set division by 256 */
51 	period_cycles = c;
52 
53 	/* The duty-cycle value is as follows:
54 	 *
55 	 *  DUTY-CYCLE     HIGH LEVEL
56 	 *      1            99.9%
57 	 *      25           90.0%
58 	 *      128          50.0%
59 	 *      220          10.0%
60 	 *      255           0.1%
61 	 *      0             0.0%
62 	 *
63 	 * In other words, the register value is duty-cycle % 256 with
64 	 * duty-cycle in the range 1-256.
65 	 */
66 	c = 256 * duty_ns;
67 	do_div(c, period_ns);
68 	if (c > 255)
69 		c = 255;
70 	duty_cycles = 256 - c;
71 
72 	val = readl(lpc32xx->base + (pwm->hwpwm << 2));
73 	val &= ~0xFFFF;
74 	val |= PWM_RELOADV(period_cycles) | PWM_DUTY(duty_cycles);
75 	writel(val, lpc32xx->base + (pwm->hwpwm << 2));
76 
77 	return 0;
78 }
79 
lpc32xx_pwm_enable(struct pwm_chip * chip,struct pwm_device * pwm)80 static int lpc32xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
81 {
82 	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
83 	u32 val;
84 	int ret;
85 
86 	ret = clk_enable(lpc32xx->clk);
87 	if (ret)
88 		return ret;
89 
90 	val = readl(lpc32xx->base + (pwm->hwpwm << 2));
91 	val |= PWM_ENABLE;
92 	writel(val, lpc32xx->base + (pwm->hwpwm << 2));
93 
94 	return 0;
95 }
96 
lpc32xx_pwm_disable(struct pwm_chip * chip,struct pwm_device * pwm)97 static void lpc32xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
98 {
99 	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
100 	u32 val;
101 
102 	val = readl(lpc32xx->base + (pwm->hwpwm << 2));
103 	val &= ~PWM_ENABLE;
104 	writel(val, lpc32xx->base + (pwm->hwpwm << 2));
105 
106 	clk_disable(lpc32xx->clk);
107 }
108 
109 static const struct pwm_ops lpc32xx_pwm_ops = {
110 	.config = lpc32xx_pwm_config,
111 	.enable = lpc32xx_pwm_enable,
112 	.disable = lpc32xx_pwm_disable,
113 	.owner = THIS_MODULE,
114 };
115 
lpc32xx_pwm_probe(struct platform_device * pdev)116 static int lpc32xx_pwm_probe(struct platform_device *pdev)
117 {
118 	struct lpc32xx_pwm_chip *lpc32xx;
119 	struct resource *res;
120 	int ret;
121 
122 	lpc32xx = devm_kzalloc(&pdev->dev, sizeof(*lpc32xx), GFP_KERNEL);
123 	if (!lpc32xx)
124 		return -ENOMEM;
125 
126 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
127 	lpc32xx->base = devm_ioremap_resource(&pdev->dev, res);
128 	if (IS_ERR(lpc32xx->base))
129 		return PTR_ERR(lpc32xx->base);
130 
131 	lpc32xx->clk = devm_clk_get(&pdev->dev, NULL);
132 	if (IS_ERR(lpc32xx->clk))
133 		return PTR_ERR(lpc32xx->clk);
134 
135 	lpc32xx->chip.dev = &pdev->dev;
136 	lpc32xx->chip.ops = &lpc32xx_pwm_ops;
137 	lpc32xx->chip.npwm = 2;
138 	lpc32xx->chip.base = -1;
139 
140 	ret = pwmchip_add(&lpc32xx->chip);
141 	if (ret < 0) {
142 		dev_err(&pdev->dev, "failed to add PWM chip, error %d\n", ret);
143 		return ret;
144 	}
145 
146 	platform_set_drvdata(pdev, lpc32xx);
147 
148 	return 0;
149 }
150 
lpc32xx_pwm_remove(struct platform_device * pdev)151 static int lpc32xx_pwm_remove(struct platform_device *pdev)
152 {
153 	struct lpc32xx_pwm_chip *lpc32xx = platform_get_drvdata(pdev);
154 	unsigned int i;
155 
156 	for (i = 0; i < lpc32xx->chip.npwm; i++)
157 		pwm_disable(&lpc32xx->chip.pwms[i]);
158 
159 	return pwmchip_remove(&lpc32xx->chip);
160 }
161 
162 static const struct of_device_id lpc32xx_pwm_dt_ids[] = {
163 	{ .compatible = "nxp,lpc3220-pwm", },
164 	{ /* sentinel */ }
165 };
166 MODULE_DEVICE_TABLE(of, lpc32xx_pwm_dt_ids);
167 
168 static struct platform_driver lpc32xx_pwm_driver = {
169 	.driver = {
170 		.name = "lpc32xx-pwm",
171 		.owner = THIS_MODULE,
172 		.of_match_table = lpc32xx_pwm_dt_ids,
173 	},
174 	.probe = lpc32xx_pwm_probe,
175 	.remove = lpc32xx_pwm_remove,
176 };
177 module_platform_driver(lpc32xx_pwm_driver);
178 
179 MODULE_ALIAS("platform:lpc32xx-pwm");
180 MODULE_AUTHOR("Alexandre Pereira da Silva <aletes.xgr@gmail.com>");
181 MODULE_DESCRIPTION("LPC32XX PWM Driver");
182 MODULE_LICENSE("GPL v2");
183