1 /*
2 * Special handling for DW core on Intel MID platform
3 *
4 * Copyright (c) 2009, 2014 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16 #include <linux/dma-mapping.h>
17 #include <linux/dmaengine.h>
18 #include <linux/interrupt.h>
19 #include <linux/slab.h>
20 #include <linux/spi/spi.h>
21 #include <linux/types.h>
22
23 #include "spi-dw.h"
24
25 #ifdef CONFIG_SPI_DW_MID_DMA
26 #include <linux/intel_mid_dma.h>
27 #include <linux/pci.h>
28
29 struct mid_dma {
30 struct intel_mid_dma_slave dmas_tx;
31 struct intel_mid_dma_slave dmas_rx;
32 };
33
mid_spi_dma_chan_filter(struct dma_chan * chan,void * param)34 static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
35 {
36 struct dw_spi *dws = param;
37
38 return dws->dma_dev == chan->device->dev;
39 }
40
mid_spi_dma_init(struct dw_spi * dws)41 static int mid_spi_dma_init(struct dw_spi *dws)
42 {
43 struct mid_dma *dw_dma = dws->dma_priv;
44 struct pci_dev *dma_dev;
45 struct intel_mid_dma_slave *rxs, *txs;
46 dma_cap_mask_t mask;
47
48 /*
49 * Get pci device for DMA controller, currently it could only
50 * be the DMA controller of Medfield
51 */
52 dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
53 if (!dma_dev)
54 return -ENODEV;
55
56 dws->dma_dev = &dma_dev->dev;
57
58 dma_cap_zero(mask);
59 dma_cap_set(DMA_SLAVE, mask);
60
61 /* 1. Init rx channel */
62 dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
63 if (!dws->rxchan)
64 goto err_exit;
65 rxs = &dw_dma->dmas_rx;
66 rxs->hs_mode = LNW_DMA_HW_HS;
67 rxs->cfg_mode = LNW_DMA_PER_TO_MEM;
68 dws->rxchan->private = rxs;
69
70 /* 2. Init tx channel */
71 dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
72 if (!dws->txchan)
73 goto free_rxchan;
74 txs = &dw_dma->dmas_tx;
75 txs->hs_mode = LNW_DMA_HW_HS;
76 txs->cfg_mode = LNW_DMA_MEM_TO_PER;
77 dws->txchan->private = txs;
78
79 dws->dma_inited = 1;
80 return 0;
81
82 free_rxchan:
83 dma_release_channel(dws->rxchan);
84 err_exit:
85 return -EBUSY;
86 }
87
mid_spi_dma_exit(struct dw_spi * dws)88 static void mid_spi_dma_exit(struct dw_spi *dws)
89 {
90 if (!dws->dma_inited)
91 return;
92
93 dmaengine_terminate_all(dws->txchan);
94 dma_release_channel(dws->txchan);
95
96 dmaengine_terminate_all(dws->rxchan);
97 dma_release_channel(dws->rxchan);
98 }
99
100 /*
101 * dws->dma_chan_done is cleared before the dma transfer starts,
102 * callback for rx/tx channel will each increment it by 1.
103 * Reaching 2 means the whole spi transaction is done.
104 */
dw_spi_dma_done(void * arg)105 static void dw_spi_dma_done(void *arg)
106 {
107 struct dw_spi *dws = arg;
108
109 if (++dws->dma_chan_done != 2)
110 return;
111 dw_spi_xfer_done(dws);
112 }
113
dw_spi_dma_prepare_tx(struct dw_spi * dws)114 static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws)
115 {
116 struct dma_slave_config txconf;
117 struct dma_async_tx_descriptor *txdesc;
118
119 txconf.direction = DMA_MEM_TO_DEV;
120 txconf.dst_addr = dws->dma_addr;
121 txconf.dst_maxburst = LNW_DMA_MSIZE_16;
122 txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
123 txconf.dst_addr_width = dws->dma_width;
124 txconf.device_fc = false;
125
126 dmaengine_slave_config(dws->txchan, &txconf);
127
128 memset(&dws->tx_sgl, 0, sizeof(dws->tx_sgl));
129 dws->tx_sgl.dma_address = dws->tx_dma;
130 dws->tx_sgl.length = dws->len;
131
132 txdesc = dmaengine_prep_slave_sg(dws->txchan,
133 &dws->tx_sgl,
134 1,
135 DMA_MEM_TO_DEV,
136 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
137 if (!txdesc)
138 return NULL;
139
140 txdesc->callback = dw_spi_dma_done;
141 txdesc->callback_param = dws;
142
143 return txdesc;
144 }
145
dw_spi_dma_prepare_rx(struct dw_spi * dws)146 static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws)
147 {
148 struct dma_slave_config rxconf;
149 struct dma_async_tx_descriptor *rxdesc;
150
151 rxconf.direction = DMA_DEV_TO_MEM;
152 rxconf.src_addr = dws->dma_addr;
153 rxconf.src_maxburst = LNW_DMA_MSIZE_16;
154 rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
155 rxconf.src_addr_width = dws->dma_width;
156 rxconf.device_fc = false;
157
158 dmaengine_slave_config(dws->rxchan, &rxconf);
159
160 memset(&dws->rx_sgl, 0, sizeof(dws->rx_sgl));
161 dws->rx_sgl.dma_address = dws->rx_dma;
162 dws->rx_sgl.length = dws->len;
163
164 rxdesc = dmaengine_prep_slave_sg(dws->rxchan,
165 &dws->rx_sgl,
166 1,
167 DMA_DEV_TO_MEM,
168 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
169 if (!rxdesc)
170 return NULL;
171
172 rxdesc->callback = dw_spi_dma_done;
173 rxdesc->callback_param = dws;
174
175 return rxdesc;
176 }
177
dw_spi_dma_setup(struct dw_spi * dws)178 static void dw_spi_dma_setup(struct dw_spi *dws)
179 {
180 u16 dma_ctrl = 0;
181
182 spi_enable_chip(dws, 0);
183
184 dw_writew(dws, DW_SPI_DMARDLR, 0xf);
185 dw_writew(dws, DW_SPI_DMATDLR, 0x10);
186
187 if (dws->tx_dma)
188 dma_ctrl |= SPI_DMA_TDMAE;
189 if (dws->rx_dma)
190 dma_ctrl |= SPI_DMA_RDMAE;
191 dw_writew(dws, DW_SPI_DMACR, dma_ctrl);
192
193 spi_enable_chip(dws, 1);
194 }
195
mid_spi_dma_transfer(struct dw_spi * dws,int cs_change)196 static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
197 {
198 struct dma_async_tx_descriptor *txdesc, *rxdesc;
199
200 /* 1. setup DMA related registers */
201 if (cs_change)
202 dw_spi_dma_setup(dws);
203
204 dws->dma_chan_done = 0;
205
206 /* 2. Prepare the TX dma transfer */
207 txdesc = dw_spi_dma_prepare_tx(dws);
208
209 /* 3. Prepare the RX dma transfer */
210 rxdesc = dw_spi_dma_prepare_rx(dws);
211
212 /* rx must be started before tx due to spi instinct */
213 dmaengine_submit(rxdesc);
214 dma_async_issue_pending(dws->rxchan);
215
216 dmaengine_submit(txdesc);
217 dma_async_issue_pending(dws->txchan);
218
219 return 0;
220 }
221
222 static struct dw_spi_dma_ops mid_dma_ops = {
223 .dma_init = mid_spi_dma_init,
224 .dma_exit = mid_spi_dma_exit,
225 .dma_transfer = mid_spi_dma_transfer,
226 };
227 #endif
228
229 /* Some specific info for SPI0 controller on Intel MID */
230
231 /* HW info for MRST CLk Control Unit, one 32b reg */
232 #define MRST_SPI_CLK_BASE 100000000 /* 100m */
233 #define MRST_CLK_SPI0_REG 0xff11d86c
234 #define CLK_SPI_BDIV_OFFSET 0
235 #define CLK_SPI_BDIV_MASK 0x00000007
236 #define CLK_SPI_CDIV_OFFSET 9
237 #define CLK_SPI_CDIV_MASK 0x00000e00
238 #define CLK_SPI_DISABLE_OFFSET 8
239
dw_spi_mid_init(struct dw_spi * dws)240 int dw_spi_mid_init(struct dw_spi *dws)
241 {
242 void __iomem *clk_reg;
243 u32 clk_cdiv;
244
245 clk_reg = ioremap_nocache(MRST_CLK_SPI0_REG, 16);
246 if (!clk_reg)
247 return -ENOMEM;
248
249 /* get SPI controller operating freq info */
250 clk_cdiv = (readl(clk_reg) & CLK_SPI_CDIV_MASK) >> CLK_SPI_CDIV_OFFSET;
251 dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
252 iounmap(clk_reg);
253
254 dws->num_cs = 16;
255
256 #ifdef CONFIG_SPI_DW_MID_DMA
257 dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);
258 if (!dws->dma_priv)
259 return -ENOMEM;
260 dws->dma_ops = &mid_dma_ops;
261 #endif
262 return 0;
263 }
264