1 /*
2 * Freescale i.MX28 LRADC driver
3 *
4 * Copyright (c) 2012 DENX Software Engineering, GmbH.
5 * Marek Vasut <marex@denx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/err.h>
19 #include <linux/interrupt.h>
20 #include <linux/device.h>
21 #include <linux/kernel.h>
22 #include <linux/slab.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/sysfs.h>
26 #include <linux/list.h>
27 #include <linux/io.h>
28 #include <linux/module.h>
29 #include <linux/platform_device.h>
30 #include <linux/spinlock.h>
31 #include <linux/wait.h>
32 #include <linux/sched.h>
33 #include <linux/stmp_device.h>
34 #include <linux/bitops.h>
35 #include <linux/completion.h>
36 #include <linux/delay.h>
37 #include <linux/input.h>
38 #include <linux/clk.h>
39
40 #include <linux/iio/iio.h>
41 #include <linux/iio/sysfs.h>
42 #include <linux/iio/buffer.h>
43 #include <linux/iio/trigger.h>
44 #include <linux/iio/trigger_consumer.h>
45 #include <linux/iio/triggered_buffer.h>
46
47 #define DRIVER_NAME "mxs-lradc"
48
49 #define LRADC_MAX_DELAY_CHANS 4
50 #define LRADC_MAX_MAPPED_CHANS 8
51 #define LRADC_MAX_TOTAL_CHANS 16
52
53 #define LRADC_DELAY_TIMER_HZ 2000
54
55 /*
56 * Make this runtime configurable if necessary. Currently, if the buffered mode
57 * is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before
58 * triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000)
59 * seconds. The result is that the samples arrive every 500mS.
60 */
61 #define LRADC_DELAY_TIMER_PER 200
62 #define LRADC_DELAY_TIMER_LOOP 5
63
64 /*
65 * Once the pen touches the touchscreen, the touchscreen switches from
66 * IRQ-driven mode to polling mode to prevent interrupt storm. The polling
67 * is realized by worker thread, which is called every 20 or so milliseconds.
68 * This gives the touchscreen enough fluence and does not strain the system
69 * too much.
70 */
71 #define LRADC_TS_SAMPLE_DELAY_MS 5
72
73 /*
74 * The LRADC reads the following amount of samples from each touchscreen
75 * channel and the driver then computes avarage of these.
76 */
77 #define LRADC_TS_SAMPLE_AMOUNT 4
78
79 enum mxs_lradc_id {
80 IMX23_LRADC,
81 IMX28_LRADC,
82 };
83
84 static const char * const mx23_lradc_irq_names[] = {
85 "mxs-lradc-touchscreen",
86 "mxs-lradc-channel0",
87 "mxs-lradc-channel1",
88 "mxs-lradc-channel2",
89 "mxs-lradc-channel3",
90 "mxs-lradc-channel4",
91 "mxs-lradc-channel5",
92 "mxs-lradc-channel6",
93 "mxs-lradc-channel7",
94 };
95
96 static const char * const mx28_lradc_irq_names[] = {
97 "mxs-lradc-touchscreen",
98 "mxs-lradc-thresh0",
99 "mxs-lradc-thresh1",
100 "mxs-lradc-channel0",
101 "mxs-lradc-channel1",
102 "mxs-lradc-channel2",
103 "mxs-lradc-channel3",
104 "mxs-lradc-channel4",
105 "mxs-lradc-channel5",
106 "mxs-lradc-channel6",
107 "mxs-lradc-channel7",
108 "mxs-lradc-button0",
109 "mxs-lradc-button1",
110 };
111
112 struct mxs_lradc_of_config {
113 const int irq_count;
114 const char * const *irq_name;
115 const uint32_t *vref_mv;
116 };
117
118 #define VREF_MV_BASE 1850
119
120 static const uint32_t mx23_vref_mv[LRADC_MAX_TOTAL_CHANS] = {
121 VREF_MV_BASE, /* CH0 */
122 VREF_MV_BASE, /* CH1 */
123 VREF_MV_BASE, /* CH2 */
124 VREF_MV_BASE, /* CH3 */
125 VREF_MV_BASE, /* CH4 */
126 VREF_MV_BASE, /* CH5 */
127 VREF_MV_BASE * 2, /* CH6 VDDIO */
128 VREF_MV_BASE * 4, /* CH7 VBATT */
129 VREF_MV_BASE, /* CH8 Temp sense 0 */
130 VREF_MV_BASE, /* CH9 Temp sense 1 */
131 VREF_MV_BASE, /* CH10 */
132 VREF_MV_BASE, /* CH11 */
133 VREF_MV_BASE, /* CH12 USB_DP */
134 VREF_MV_BASE, /* CH13 USB_DN */
135 VREF_MV_BASE, /* CH14 VBG */
136 VREF_MV_BASE * 4, /* CH15 VDD5V */
137 };
138
139 static const uint32_t mx28_vref_mv[LRADC_MAX_TOTAL_CHANS] = {
140 VREF_MV_BASE, /* CH0 */
141 VREF_MV_BASE, /* CH1 */
142 VREF_MV_BASE, /* CH2 */
143 VREF_MV_BASE, /* CH3 */
144 VREF_MV_BASE, /* CH4 */
145 VREF_MV_BASE, /* CH5 */
146 VREF_MV_BASE, /* CH6 */
147 VREF_MV_BASE * 4, /* CH7 VBATT */
148 VREF_MV_BASE, /* CH8 Temp sense 0 */
149 VREF_MV_BASE, /* CH9 Temp sense 1 */
150 VREF_MV_BASE * 2, /* CH10 VDDIO */
151 VREF_MV_BASE, /* CH11 VTH */
152 VREF_MV_BASE * 2, /* CH12 VDDA */
153 VREF_MV_BASE, /* CH13 VDDD */
154 VREF_MV_BASE, /* CH14 VBG */
155 VREF_MV_BASE * 4, /* CH15 VDD5V */
156 };
157
158 static const struct mxs_lradc_of_config mxs_lradc_of_config[] = {
159 [IMX23_LRADC] = {
160 .irq_count = ARRAY_SIZE(mx23_lradc_irq_names),
161 .irq_name = mx23_lradc_irq_names,
162 .vref_mv = mx23_vref_mv,
163 },
164 [IMX28_LRADC] = {
165 .irq_count = ARRAY_SIZE(mx28_lradc_irq_names),
166 .irq_name = mx28_lradc_irq_names,
167 .vref_mv = mx28_vref_mv,
168 },
169 };
170
171 enum mxs_lradc_ts {
172 MXS_LRADC_TOUCHSCREEN_NONE = 0,
173 MXS_LRADC_TOUCHSCREEN_4WIRE,
174 MXS_LRADC_TOUCHSCREEN_5WIRE,
175 };
176
177 /*
178 * Touchscreen handling
179 */
180 enum lradc_ts_plate {
181 LRADC_TOUCH = 0,
182 LRADC_SAMPLE_X,
183 LRADC_SAMPLE_Y,
184 LRADC_SAMPLE_PRESSURE,
185 LRADC_SAMPLE_VALID,
186 };
187
188 enum mxs_lradc_divbytwo {
189 MXS_LRADC_DIV_DISABLED = 0,
190 MXS_LRADC_DIV_ENABLED,
191 };
192
193 struct mxs_lradc_scale {
194 unsigned int integer;
195 unsigned int nano;
196 };
197
198 struct mxs_lradc {
199 struct device *dev;
200 void __iomem *base;
201 int irq[13];
202
203 struct clk *clk;
204
205 uint32_t *buffer;
206 struct iio_trigger *trig;
207
208 struct mutex lock;
209
210 struct completion completion;
211
212 const uint32_t *vref_mv;
213 struct mxs_lradc_scale scale_avail[LRADC_MAX_TOTAL_CHANS][2];
214 unsigned long is_divided;
215
216 /*
217 * When the touchscreen is enabled, we give it two private virtual
218 * channels: #6 and #7. This means that only 6 virtual channels (instead
219 * of 8) will be available for buffered capture.
220 */
221 #define TOUCHSCREEN_VCHANNEL1 7
222 #define TOUCHSCREEN_VCHANNEL2 6
223 #define BUFFER_VCHANS_LIMITED 0x3f
224 #define BUFFER_VCHANS_ALL 0xff
225 u8 buffer_vchans;
226
227 /*
228 * Furthermore, certain LRADC channels are shared between touchscreen
229 * and/or touch-buttons and generic LRADC block. Therefore when using
230 * either of these, these channels are not available for the regular
231 * sampling. The shared channels are as follows:
232 *
233 * CH0 -- Touch button #0
234 * CH1 -- Touch button #1
235 * CH2 -- Touch screen XPUL
236 * CH3 -- Touch screen YPLL
237 * CH4 -- Touch screen XNUL
238 * CH5 -- Touch screen YNLR
239 * CH6 -- Touch screen WIPER (5-wire only)
240 *
241 * The bitfields below represents which parts of the LRADC block are
242 * switched into special mode of operation. These channels can not
243 * be sampled as regular LRADC channels. The driver will refuse any
244 * attempt to sample these channels.
245 */
246 #define CHAN_MASK_TOUCHBUTTON (0x3 << 0)
247 #define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 2)
248 #define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 2)
249 enum mxs_lradc_ts use_touchscreen;
250 bool use_touchbutton;
251
252 struct input_dev *ts_input;
253
254 enum mxs_lradc_id soc;
255 enum lradc_ts_plate cur_plate; /* statemachine */
256 bool ts_valid;
257 unsigned ts_x_pos;
258 unsigned ts_y_pos;
259 unsigned ts_pressure;
260
261 /* handle touchscreen's physical behaviour */
262 /* samples per coordinate */
263 unsigned over_sample_cnt;
264 /* time clocks between samples */
265 unsigned over_sample_delay;
266 /* time in clocks to wait after the plates where switched */
267 unsigned settling_delay;
268 };
269
270 #define LRADC_CTRL0 0x00
271 # define LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE (1 << 23)
272 # define LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE (1 << 22)
273 # define LRADC_CTRL0_MX28_YNNSW /* YM */ (1 << 21)
274 # define LRADC_CTRL0_MX28_YPNSW /* YP */ (1 << 20)
275 # define LRADC_CTRL0_MX28_YPPSW /* YP */ (1 << 19)
276 # define LRADC_CTRL0_MX28_XNNSW /* XM */ (1 << 18)
277 # define LRADC_CTRL0_MX28_XNPSW /* XM */ (1 << 17)
278 # define LRADC_CTRL0_MX28_XPPSW /* XP */ (1 << 16)
279
280 # define LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE (1 << 20)
281 # define LRADC_CTRL0_MX23_YM (1 << 19)
282 # define LRADC_CTRL0_MX23_XM (1 << 18)
283 # define LRADC_CTRL0_MX23_YP (1 << 17)
284 # define LRADC_CTRL0_MX23_XP (1 << 16)
285
286 # define LRADC_CTRL0_MX28_PLATE_MASK \
287 (LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE | \
288 LRADC_CTRL0_MX28_YNNSW | LRADC_CTRL0_MX28_YPNSW | \
289 LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW | \
290 LRADC_CTRL0_MX28_XNPSW | LRADC_CTRL0_MX28_XPPSW)
291
292 # define LRADC_CTRL0_MX23_PLATE_MASK \
293 (LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE | \
294 LRADC_CTRL0_MX23_YM | LRADC_CTRL0_MX23_XM | \
295 LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_XP)
296
297 #define LRADC_CTRL1 0x10
298 #define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN (1 << 24)
299 #define LRADC_CTRL1_LRADC_IRQ_EN(n) (1 << ((n) + 16))
300 #define LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK (0x1fff << 16)
301 #define LRADC_CTRL1_MX23_LRADC_IRQ_EN_MASK (0x01ff << 16)
302 #define LRADC_CTRL1_LRADC_IRQ_EN_OFFSET 16
303 #define LRADC_CTRL1_TOUCH_DETECT_IRQ (1 << 8)
304 #define LRADC_CTRL1_LRADC_IRQ(n) (1 << (n))
305 #define LRADC_CTRL1_MX28_LRADC_IRQ_MASK 0x1fff
306 #define LRADC_CTRL1_MX23_LRADC_IRQ_MASK 0x01ff
307 #define LRADC_CTRL1_LRADC_IRQ_OFFSET 0
308
309 #define LRADC_CTRL2 0x20
310 #define LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET 24
311 #define LRADC_CTRL2_TEMPSENSE_PWD (1 << 15)
312
313 #define LRADC_STATUS 0x40
314 #define LRADC_STATUS_TOUCH_DETECT_RAW (1 << 0)
315
316 #define LRADC_CH(n) (0x50 + (0x10 * (n)))
317 #define LRADC_CH_ACCUMULATE (1 << 29)
318 #define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24)
319 #define LRADC_CH_NUM_SAMPLES_OFFSET 24
320 #define LRADC_CH_NUM_SAMPLES(x) \
321 ((x) << LRADC_CH_NUM_SAMPLES_OFFSET)
322 #define LRADC_CH_VALUE_MASK 0x3ffff
323 #define LRADC_CH_VALUE_OFFSET 0
324
325 #define LRADC_DELAY(n) (0xd0 + (0x10 * (n)))
326 #define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xff << 24)
327 #define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24
328 #define LRADC_DELAY_TRIGGER(x) \
329 (((x) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) & \
330 LRADC_DELAY_TRIGGER_LRADCS_MASK)
331 #define LRADC_DELAY_KICK (1 << 20)
332 #define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16)
333 #define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16
334 #define LRADC_DELAY_TRIGGER_DELAYS(x) \
335 (((x) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) & \
336 LRADC_DELAY_TRIGGER_DELAYS_MASK)
337 #define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11)
338 #define LRADC_DELAY_LOOP_COUNT_OFFSET 11
339 #define LRADC_DELAY_LOOP(x) \
340 (((x) << LRADC_DELAY_LOOP_COUNT_OFFSET) & \
341 LRADC_DELAY_LOOP_COUNT_MASK)
342 #define LRADC_DELAY_DELAY_MASK 0x7ff
343 #define LRADC_DELAY_DELAY_OFFSET 0
344 #define LRADC_DELAY_DELAY(x) \
345 (((x) << LRADC_DELAY_DELAY_OFFSET) & \
346 LRADC_DELAY_DELAY_MASK)
347
348 #define LRADC_CTRL4 0x140
349 #define LRADC_CTRL4_LRADCSELECT_MASK(n) (0xf << ((n) * 4))
350 #define LRADC_CTRL4_LRADCSELECT_OFFSET(n) ((n) * 4)
351 #define LRADC_CTRL4_LRADCSELECT(n, x) \
352 (((x) << LRADC_CTRL4_LRADCSELECT_OFFSET(n)) & \
353 LRADC_CTRL4_LRADCSELECT_MASK(n))
354
355 #define LRADC_RESOLUTION 12
356 #define LRADC_SINGLE_SAMPLE_MASK ((1 << LRADC_RESOLUTION) - 1)
357
mxs_lradc_reg_set(struct mxs_lradc * lradc,u32 val,u32 reg)358 static void mxs_lradc_reg_set(struct mxs_lradc *lradc, u32 val, u32 reg)
359 {
360 writel(val, lradc->base + reg + STMP_OFFSET_REG_SET);
361 }
362
mxs_lradc_reg_clear(struct mxs_lradc * lradc,u32 val,u32 reg)363 static void mxs_lradc_reg_clear(struct mxs_lradc *lradc, u32 val, u32 reg)
364 {
365 writel(val, lradc->base + reg + STMP_OFFSET_REG_CLR);
366 }
367
mxs_lradc_reg_wrt(struct mxs_lradc * lradc,u32 val,u32 reg)368 static void mxs_lradc_reg_wrt(struct mxs_lradc *lradc, u32 val, u32 reg)
369 {
370 writel(val, lradc->base + reg);
371 }
372
mxs_lradc_plate_mask(struct mxs_lradc * lradc)373 static u32 mxs_lradc_plate_mask(struct mxs_lradc *lradc)
374 {
375 if (lradc->soc == IMX23_LRADC)
376 return LRADC_CTRL0_MX23_PLATE_MASK;
377 return LRADC_CTRL0_MX28_PLATE_MASK;
378 }
379
mxs_lradc_irq_en_mask(struct mxs_lradc * lradc)380 static u32 mxs_lradc_irq_en_mask(struct mxs_lradc *lradc)
381 {
382 if (lradc->soc == IMX23_LRADC)
383 return LRADC_CTRL1_MX23_LRADC_IRQ_EN_MASK;
384 return LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK;
385 }
386
mxs_lradc_irq_mask(struct mxs_lradc * lradc)387 static u32 mxs_lradc_irq_mask(struct mxs_lradc *lradc)
388 {
389 if (lradc->soc == IMX23_LRADC)
390 return LRADC_CTRL1_MX23_LRADC_IRQ_MASK;
391 return LRADC_CTRL1_MX28_LRADC_IRQ_MASK;
392 }
393
mxs_lradc_touch_detect_bit(struct mxs_lradc * lradc)394 static u32 mxs_lradc_touch_detect_bit(struct mxs_lradc *lradc)
395 {
396 if (lradc->soc == IMX23_LRADC)
397 return LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE;
398 return LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE;
399 }
400
mxs_lradc_drive_x_plate(struct mxs_lradc * lradc)401 static u32 mxs_lradc_drive_x_plate(struct mxs_lradc *lradc)
402 {
403 if (lradc->soc == IMX23_LRADC)
404 return LRADC_CTRL0_MX23_XP | LRADC_CTRL0_MX23_XM;
405 return LRADC_CTRL0_MX28_XPPSW | LRADC_CTRL0_MX28_XNNSW;
406 }
407
mxs_lradc_drive_y_plate(struct mxs_lradc * lradc)408 static u32 mxs_lradc_drive_y_plate(struct mxs_lradc *lradc)
409 {
410 if (lradc->soc == IMX23_LRADC)
411 return LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_YM;
412 return LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_YNNSW;
413 }
414
mxs_lradc_drive_pressure(struct mxs_lradc * lradc)415 static u32 mxs_lradc_drive_pressure(struct mxs_lradc *lradc)
416 {
417 if (lradc->soc == IMX23_LRADC)
418 return LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_XM;
419 return LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW;
420 }
421
mxs_lradc_check_touch_event(struct mxs_lradc * lradc)422 static bool mxs_lradc_check_touch_event(struct mxs_lradc *lradc)
423 {
424 return !!(readl(lradc->base + LRADC_STATUS) &
425 LRADC_STATUS_TOUCH_DETECT_RAW);
426 }
427
mxs_lradc_map_channel(struct mxs_lradc * lradc,unsigned vch,unsigned ch)428 static void mxs_lradc_map_channel(struct mxs_lradc *lradc, unsigned vch,
429 unsigned ch)
430 {
431 mxs_lradc_reg_clear(lradc, LRADC_CTRL4_LRADCSELECT_MASK(vch),
432 LRADC_CTRL4);
433 mxs_lradc_reg_set(lradc, LRADC_CTRL4_LRADCSELECT(vch, ch), LRADC_CTRL4);
434 }
435
mxs_lradc_setup_ts_channel(struct mxs_lradc * lradc,unsigned ch)436 static void mxs_lradc_setup_ts_channel(struct mxs_lradc *lradc, unsigned ch)
437 {
438 /*
439 * prepare for oversampling conversion
440 *
441 * from the datasheet:
442 * "The ACCUMULATE bit in the appropriate channel register
443 * HW_LRADC_CHn must be set to 1 if NUM_SAMPLES is greater then 0;
444 * otherwise, the IRQs will not fire."
445 */
446 mxs_lradc_reg_wrt(lradc, LRADC_CH_ACCUMULATE |
447 LRADC_CH_NUM_SAMPLES(lradc->over_sample_cnt - 1),
448 LRADC_CH(ch));
449
450 /* from the datasheet:
451 * "Software must clear this register in preparation for a
452 * multi-cycle accumulation.
453 */
454 mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch));
455
456 /* prepare the delay/loop unit according to the oversampling count */
457 mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(1 << ch) |
458 LRADC_DELAY_TRIGGER_DELAYS(0) |
459 LRADC_DELAY_LOOP(lradc->over_sample_cnt - 1) |
460 LRADC_DELAY_DELAY(lradc->over_sample_delay - 1),
461 LRADC_DELAY(3));
462
463 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ(ch), LRADC_CTRL1);
464
465 /*
466 * after changing the touchscreen plates setting
467 * the signals need some initial time to settle. Start the
468 * SoC's delay unit and start the conversion later
469 * and automatically.
470 */
471 mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(0) | /* don't trigger ADC */
472 LRADC_DELAY_TRIGGER_DELAYS(1 << 3) | /* trigger DELAY unit#3 */
473 LRADC_DELAY_KICK |
474 LRADC_DELAY_DELAY(lradc->settling_delay),
475 LRADC_DELAY(2));
476 }
477
478 /*
479 * Pressure detection is special:
480 * We want to do both required measurements for the pressure detection in
481 * one turn. Use the hardware features to chain both conversions and let the
482 * hardware report one interrupt if both conversions are done
483 */
mxs_lradc_setup_ts_pressure(struct mxs_lradc * lradc,unsigned ch1,unsigned ch2)484 static void mxs_lradc_setup_ts_pressure(struct mxs_lradc *lradc, unsigned ch1,
485 unsigned ch2)
486 {
487 u32 reg;
488
489 /*
490 * prepare for oversampling conversion
491 *
492 * from the datasheet:
493 * "The ACCUMULATE bit in the appropriate channel register
494 * HW_LRADC_CHn must be set to 1 if NUM_SAMPLES is greater then 0;
495 * otherwise, the IRQs will not fire."
496 */
497 reg = LRADC_CH_ACCUMULATE |
498 LRADC_CH_NUM_SAMPLES(lradc->over_sample_cnt - 1);
499 mxs_lradc_reg_wrt(lradc, reg, LRADC_CH(ch1));
500 mxs_lradc_reg_wrt(lradc, reg, LRADC_CH(ch2));
501
502 /* from the datasheet:
503 * "Software must clear this register in preparation for a
504 * multi-cycle accumulation.
505 */
506 mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch1));
507 mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch2));
508
509 /* prepare the delay/loop unit according to the oversampling count */
510 mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(1 << ch1) |
511 LRADC_DELAY_TRIGGER(1 << ch2) | /* start both channels */
512 LRADC_DELAY_TRIGGER_DELAYS(0) |
513 LRADC_DELAY_LOOP(lradc->over_sample_cnt - 1) |
514 LRADC_DELAY_DELAY(lradc->over_sample_delay - 1),
515 LRADC_DELAY(3));
516
517 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ(ch2), LRADC_CTRL1);
518
519 /*
520 * after changing the touchscreen plates setting
521 * the signals need some initial time to settle. Start the
522 * SoC's delay unit and start the conversion later
523 * and automatically.
524 */
525 mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(0) | /* don't trigger ADC */
526 LRADC_DELAY_TRIGGER_DELAYS(1 << 3) | /* trigger DELAY unit#3 */
527 LRADC_DELAY_KICK |
528 LRADC_DELAY_DELAY(lradc->settling_delay), LRADC_DELAY(2));
529 }
530
mxs_lradc_read_raw_channel(struct mxs_lradc * lradc,unsigned channel)531 static unsigned mxs_lradc_read_raw_channel(struct mxs_lradc *lradc,
532 unsigned channel)
533 {
534 u32 reg;
535 unsigned num_samples, val;
536
537 reg = readl(lradc->base + LRADC_CH(channel));
538 if (reg & LRADC_CH_ACCUMULATE)
539 num_samples = lradc->over_sample_cnt;
540 else
541 num_samples = 1;
542
543 val = (reg & LRADC_CH_VALUE_MASK) >> LRADC_CH_VALUE_OFFSET;
544 return val / num_samples;
545 }
546
mxs_lradc_read_ts_pressure(struct mxs_lradc * lradc,unsigned ch1,unsigned ch2)547 static unsigned mxs_lradc_read_ts_pressure(struct mxs_lradc *lradc,
548 unsigned ch1, unsigned ch2)
549 {
550 u32 reg, mask;
551 unsigned pressure, m1, m2;
552
553 mask = LRADC_CTRL1_LRADC_IRQ(ch1) | LRADC_CTRL1_LRADC_IRQ(ch2);
554 reg = readl(lradc->base + LRADC_CTRL1) & mask;
555
556 while (reg != mask) {
557 reg = readl(lradc->base + LRADC_CTRL1) & mask;
558 dev_dbg(lradc->dev, "One channel is still busy: %X\n", reg);
559 }
560
561 m1 = mxs_lradc_read_raw_channel(lradc, ch1);
562 m2 = mxs_lradc_read_raw_channel(lradc, ch2);
563
564 if (m2 == 0) {
565 dev_warn(lradc->dev, "Cannot calculate pressure\n");
566 return 1 << (LRADC_RESOLUTION - 1);
567 }
568
569 /* simply scale the value from 0 ... max ADC resolution */
570 pressure = m1;
571 pressure *= (1 << LRADC_RESOLUTION);
572 pressure /= m2;
573
574 dev_dbg(lradc->dev, "Pressure = %u\n", pressure);
575 return pressure;
576 }
577
578 #define TS_CH_XP 2
579 #define TS_CH_YP 3
580 #define TS_CH_XM 4
581 #define TS_CH_YM 5
582
583 /*
584 * YP(open)--+-------------+
585 * | |--+
586 * | | |
587 * YM(-)--+-------------+ |
588 * +--------------+
589 * | |
590 * XP(weak+) XM(open)
591 *
592 * "weak+" means 200k Ohm VDDIO
593 * (-) means GND
594 */
mxs_lradc_setup_touch_detection(struct mxs_lradc * lradc)595 static void mxs_lradc_setup_touch_detection(struct mxs_lradc *lradc)
596 {
597 /*
598 * In order to detect a touch event the 'touch detect enable' bit
599 * enables:
600 * - a weak pullup to the X+ connector
601 * - a strong ground at the Y- connector
602 */
603 mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
604 mxs_lradc_reg_set(lradc, mxs_lradc_touch_detect_bit(lradc),
605 LRADC_CTRL0);
606 }
607
608 /*
609 * YP(meas)--+-------------+
610 * | |--+
611 * | | |
612 * YM(open)--+-------------+ |
613 * +--------------+
614 * | |
615 * XP(+) XM(-)
616 *
617 * (+) means here 1.85 V
618 * (-) means here GND
619 */
mxs_lradc_prepare_x_pos(struct mxs_lradc * lradc)620 static void mxs_lradc_prepare_x_pos(struct mxs_lradc *lradc)
621 {
622 mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
623 mxs_lradc_reg_set(lradc, mxs_lradc_drive_x_plate(lradc), LRADC_CTRL0);
624
625 lradc->cur_plate = LRADC_SAMPLE_X;
626 mxs_lradc_map_channel(lradc, TOUCHSCREEN_VCHANNEL1, TS_CH_YP);
627 mxs_lradc_setup_ts_channel(lradc, TOUCHSCREEN_VCHANNEL1);
628 }
629
630 /*
631 * YP(+)--+-------------+
632 * | |--+
633 * | | |
634 * YM(-)--+-------------+ |
635 * +--------------+
636 * | |
637 * XP(open) XM(meas)
638 *
639 * (+) means here 1.85 V
640 * (-) means here GND
641 */
mxs_lradc_prepare_y_pos(struct mxs_lradc * lradc)642 static void mxs_lradc_prepare_y_pos(struct mxs_lradc *lradc)
643 {
644 mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
645 mxs_lradc_reg_set(lradc, mxs_lradc_drive_y_plate(lradc), LRADC_CTRL0);
646
647 lradc->cur_plate = LRADC_SAMPLE_Y;
648 mxs_lradc_map_channel(lradc, TOUCHSCREEN_VCHANNEL1, TS_CH_XM);
649 mxs_lradc_setup_ts_channel(lradc, TOUCHSCREEN_VCHANNEL1);
650 }
651
652 /*
653 * YP(+)--+-------------+
654 * | |--+
655 * | | |
656 * YM(meas)--+-------------+ |
657 * +--------------+
658 * | |
659 * XP(meas) XM(-)
660 *
661 * (+) means here 1.85 V
662 * (-) means here GND
663 */
mxs_lradc_prepare_pressure(struct mxs_lradc * lradc)664 static void mxs_lradc_prepare_pressure(struct mxs_lradc *lradc)
665 {
666 mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
667 mxs_lradc_reg_set(lradc, mxs_lradc_drive_pressure(lradc), LRADC_CTRL0);
668
669 lradc->cur_plate = LRADC_SAMPLE_PRESSURE;
670 mxs_lradc_map_channel(lradc, TOUCHSCREEN_VCHANNEL1, TS_CH_YM);
671 mxs_lradc_map_channel(lradc, TOUCHSCREEN_VCHANNEL2, TS_CH_XP);
672 mxs_lradc_setup_ts_pressure(lradc, TOUCHSCREEN_VCHANNEL2,
673 TOUCHSCREEN_VCHANNEL1);
674 }
675
mxs_lradc_enable_touch_detection(struct mxs_lradc * lradc)676 static void mxs_lradc_enable_touch_detection(struct mxs_lradc *lradc)
677 {
678 mxs_lradc_setup_touch_detection(lradc);
679
680 lradc->cur_plate = LRADC_TOUCH;
681 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ |
682 LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
683 mxs_lradc_reg_set(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
684 }
685
mxs_lradc_start_touch_event(struct mxs_lradc * lradc)686 static void mxs_lradc_start_touch_event(struct mxs_lradc *lradc)
687 {
688 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN,
689 LRADC_CTRL1);
690 mxs_lradc_reg_set(lradc,
691 LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL1), LRADC_CTRL1);
692 /*
693 * start with the Y-pos, because it uses nearly the same plate
694 * settings like the touch detection
695 */
696 mxs_lradc_prepare_y_pos(lradc);
697 }
698
mxs_lradc_report_ts_event(struct mxs_lradc * lradc)699 static void mxs_lradc_report_ts_event(struct mxs_lradc *lradc)
700 {
701 input_report_abs(lradc->ts_input, ABS_X, lradc->ts_x_pos);
702 input_report_abs(lradc->ts_input, ABS_Y, lradc->ts_y_pos);
703 input_report_abs(lradc->ts_input, ABS_PRESSURE, lradc->ts_pressure);
704 input_report_key(lradc->ts_input, BTN_TOUCH, 1);
705 input_sync(lradc->ts_input);
706 }
707
mxs_lradc_complete_touch_event(struct mxs_lradc * lradc)708 static void mxs_lradc_complete_touch_event(struct mxs_lradc *lradc)
709 {
710 mxs_lradc_setup_touch_detection(lradc);
711 lradc->cur_plate = LRADC_SAMPLE_VALID;
712 /*
713 * start a dummy conversion to burn time to settle the signals
714 * note: we are not interested in the conversion's value
715 */
716 mxs_lradc_reg_wrt(lradc, 0, LRADC_CH(TOUCHSCREEN_VCHANNEL1));
717 mxs_lradc_reg_clear(lradc,
718 LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1) |
719 LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL2), LRADC_CTRL1);
720 mxs_lradc_reg_wrt(lradc,
721 LRADC_DELAY_TRIGGER(1 << TOUCHSCREEN_VCHANNEL1) |
722 LRADC_DELAY_KICK | LRADC_DELAY_DELAY(10), /* waste 5 ms */
723 LRADC_DELAY(2));
724 }
725
726 /*
727 * in order to avoid false measurements, report only samples where
728 * the surface is still touched after the position measurement
729 */
mxs_lradc_finish_touch_event(struct mxs_lradc * lradc,bool valid)730 static void mxs_lradc_finish_touch_event(struct mxs_lradc *lradc, bool valid)
731 {
732 /* if it is still touched, report the sample */
733 if (valid && mxs_lradc_check_touch_event(lradc)) {
734 lradc->ts_valid = true;
735 mxs_lradc_report_ts_event(lradc);
736 }
737
738 /* if it is even still touched, continue with the next measurement */
739 if (mxs_lradc_check_touch_event(lradc)) {
740 mxs_lradc_prepare_y_pos(lradc);
741 return;
742 }
743
744 if (lradc->ts_valid) {
745 /* signal the release */
746 lradc->ts_valid = false;
747 input_report_key(lradc->ts_input, BTN_TOUCH, 0);
748 input_sync(lradc->ts_input);
749 }
750
751 /* if it is released, wait for the next touch via IRQ */
752 lradc->cur_plate = LRADC_TOUCH;
753 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(2));
754 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(3));
755 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ |
756 LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL1) |
757 LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1), LRADC_CTRL1);
758 mxs_lradc_reg_set(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
759 }
760
761 /* touchscreen's state machine */
mxs_lradc_handle_touch(struct mxs_lradc * lradc)762 static void mxs_lradc_handle_touch(struct mxs_lradc *lradc)
763 {
764 switch (lradc->cur_plate) {
765 case LRADC_TOUCH:
766 if (mxs_lradc_check_touch_event(lradc))
767 mxs_lradc_start_touch_event(lradc);
768 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ,
769 LRADC_CTRL1);
770 return;
771
772 case LRADC_SAMPLE_Y:
773 lradc->ts_y_pos = mxs_lradc_read_raw_channel(lradc,
774 TOUCHSCREEN_VCHANNEL1);
775 mxs_lradc_prepare_x_pos(lradc);
776 return;
777
778 case LRADC_SAMPLE_X:
779 lradc->ts_x_pos = mxs_lradc_read_raw_channel(lradc,
780 TOUCHSCREEN_VCHANNEL1);
781 mxs_lradc_prepare_pressure(lradc);
782 return;
783
784 case LRADC_SAMPLE_PRESSURE:
785 lradc->ts_pressure = mxs_lradc_read_ts_pressure(lradc,
786 TOUCHSCREEN_VCHANNEL2,
787 TOUCHSCREEN_VCHANNEL1);
788 mxs_lradc_complete_touch_event(lradc);
789 return;
790
791 case LRADC_SAMPLE_VALID:
792 mxs_lradc_finish_touch_event(lradc, 1);
793 break;
794 }
795 }
796
797 /*
798 * Raw I/O operations
799 */
mxs_lradc_read_single(struct iio_dev * iio_dev,int chan,int * val)800 static int mxs_lradc_read_single(struct iio_dev *iio_dev, int chan, int *val)
801 {
802 struct mxs_lradc *lradc = iio_priv(iio_dev);
803 int ret;
804
805 /*
806 * See if there is no buffered operation in progess. If there is, simply
807 * bail out. This can be improved to support both buffered and raw IO at
808 * the same time, yet the code becomes horribly complicated. Therefore I
809 * applied KISS principle here.
810 */
811 ret = mutex_trylock(&lradc->lock);
812 if (!ret)
813 return -EBUSY;
814
815 reinit_completion(&lradc->completion);
816
817 /*
818 * No buffered operation in progress, map the channel and trigger it.
819 * Virtual channel 0 is always used here as the others are always not
820 * used if doing raw sampling.
821 */
822 if (lradc->soc == IMX28_LRADC)
823 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0),
824 LRADC_CTRL1);
825 mxs_lradc_reg_clear(lradc, 0x1, LRADC_CTRL0);
826
827 /* Enable / disable the divider per requirement */
828 if (test_bit(chan, &lradc->is_divided))
829 mxs_lradc_reg_set(lradc, 1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
830 LRADC_CTRL2);
831 else
832 mxs_lradc_reg_clear(lradc,
833 1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET, LRADC_CTRL2);
834
835 /* Clean the slot's previous content, then set new one. */
836 mxs_lradc_reg_clear(lradc, LRADC_CTRL4_LRADCSELECT_MASK(0),
837 LRADC_CTRL4);
838 mxs_lradc_reg_set(lradc, chan, LRADC_CTRL4);
839
840 mxs_lradc_reg_wrt(lradc, 0, LRADC_CH(0));
841
842 /* Enable the IRQ and start sampling the channel. */
843 mxs_lradc_reg_set(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0), LRADC_CTRL1);
844 mxs_lradc_reg_set(lradc, 1 << 0, LRADC_CTRL0);
845
846 /* Wait for completion on the channel, 1 second max. */
847 ret = wait_for_completion_killable_timeout(&lradc->completion, HZ);
848 if (!ret)
849 ret = -ETIMEDOUT;
850 if (ret < 0)
851 goto err;
852
853 /* Read the data. */
854 *val = readl(lradc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK;
855 ret = IIO_VAL_INT;
856
857 err:
858 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0), LRADC_CTRL1);
859
860 mutex_unlock(&lradc->lock);
861
862 return ret;
863 }
864
mxs_lradc_read_temp(struct iio_dev * iio_dev,int * val)865 static int mxs_lradc_read_temp(struct iio_dev *iio_dev, int *val)
866 {
867 int ret, min, max;
868
869 ret = mxs_lradc_read_single(iio_dev, 8, &min);
870 if (ret != IIO_VAL_INT)
871 return ret;
872
873 ret = mxs_lradc_read_single(iio_dev, 9, &max);
874 if (ret != IIO_VAL_INT)
875 return ret;
876
877 *val = max - min;
878
879 return IIO_VAL_INT;
880 }
881
mxs_lradc_read_raw(struct iio_dev * iio_dev,const struct iio_chan_spec * chan,int * val,int * val2,long m)882 static int mxs_lradc_read_raw(struct iio_dev *iio_dev,
883 const struct iio_chan_spec *chan,
884 int *val, int *val2, long m)
885 {
886 struct mxs_lradc *lradc = iio_priv(iio_dev);
887
888 switch (m) {
889 case IIO_CHAN_INFO_RAW:
890 if (chan->type == IIO_TEMP)
891 return mxs_lradc_read_temp(iio_dev, val);
892
893 return mxs_lradc_read_single(iio_dev, chan->channel, val);
894
895 case IIO_CHAN_INFO_SCALE:
896 if (chan->type == IIO_TEMP) {
897 /* From the datasheet, we have to multiply by 1.012 and
898 * divide by 4
899 */
900 *val = 0;
901 *val2 = 253000;
902 return IIO_VAL_INT_PLUS_MICRO;
903 }
904
905 *val = lradc->vref_mv[chan->channel];
906 *val2 = chan->scan_type.realbits -
907 test_bit(chan->channel, &lradc->is_divided);
908 return IIO_VAL_FRACTIONAL_LOG2;
909
910 case IIO_CHAN_INFO_OFFSET:
911 if (chan->type == IIO_TEMP) {
912 /* The calculated value from the ADC is in Kelvin, we
913 * want Celsius for hwmon so the offset is -273.15
914 * The offset is applied before scaling so it is
915 * actually -213.15 * 4 / 1.012 = -1079.644268
916 */
917 *val = -1079;
918 *val2 = 644268;
919
920 return IIO_VAL_INT_PLUS_MICRO;
921 }
922
923 return -EINVAL;
924
925 default:
926 break;
927 }
928
929 return -EINVAL;
930 }
931
mxs_lradc_write_raw(struct iio_dev * iio_dev,const struct iio_chan_spec * chan,int val,int val2,long m)932 static int mxs_lradc_write_raw(struct iio_dev *iio_dev,
933 const struct iio_chan_spec *chan,
934 int val, int val2, long m)
935 {
936 struct mxs_lradc *lradc = iio_priv(iio_dev);
937 struct mxs_lradc_scale *scale_avail =
938 lradc->scale_avail[chan->channel];
939 int ret;
940
941 ret = mutex_trylock(&lradc->lock);
942 if (!ret)
943 return -EBUSY;
944
945 switch (m) {
946 case IIO_CHAN_INFO_SCALE:
947 ret = -EINVAL;
948 if (val == scale_avail[MXS_LRADC_DIV_DISABLED].integer &&
949 val2 == scale_avail[MXS_LRADC_DIV_DISABLED].nano) {
950 /* divider by two disabled */
951 clear_bit(chan->channel, &lradc->is_divided);
952 ret = 0;
953 } else if (val == scale_avail[MXS_LRADC_DIV_ENABLED].integer &&
954 val2 == scale_avail[MXS_LRADC_DIV_ENABLED].nano) {
955 /* divider by two enabled */
956 set_bit(chan->channel, &lradc->is_divided);
957 ret = 0;
958 }
959
960 break;
961 default:
962 ret = -EINVAL;
963 break;
964 }
965
966 mutex_unlock(&lradc->lock);
967
968 return ret;
969 }
970
mxs_lradc_write_raw_get_fmt(struct iio_dev * iio_dev,const struct iio_chan_spec * chan,long m)971 static int mxs_lradc_write_raw_get_fmt(struct iio_dev *iio_dev,
972 const struct iio_chan_spec *chan,
973 long m)
974 {
975 return IIO_VAL_INT_PLUS_NANO;
976 }
977
mxs_lradc_show_scale_available_ch(struct device * dev,struct device_attribute * attr,char * buf,int ch)978 static ssize_t mxs_lradc_show_scale_available_ch(struct device *dev,
979 struct device_attribute *attr,
980 char *buf,
981 int ch)
982 {
983 struct iio_dev *iio = dev_to_iio_dev(dev);
984 struct mxs_lradc *lradc = iio_priv(iio);
985 int i, len = 0;
986
987 for (i = 0; i < ARRAY_SIZE(lradc->scale_avail[ch]); i++)
988 len += sprintf(buf + len, "%d.%09u ",
989 lradc->scale_avail[ch][i].integer,
990 lradc->scale_avail[ch][i].nano);
991
992 len += sprintf(buf + len, "\n");
993
994 return len;
995 }
996
mxs_lradc_show_scale_available(struct device * dev,struct device_attribute * attr,char * buf)997 static ssize_t mxs_lradc_show_scale_available(struct device *dev,
998 struct device_attribute *attr,
999 char *buf)
1000 {
1001 struct iio_dev_attr *iio_attr = to_iio_dev_attr(attr);
1002
1003 return mxs_lradc_show_scale_available_ch(dev, attr, buf,
1004 iio_attr->address);
1005 }
1006
1007 #define SHOW_SCALE_AVAILABLE_ATTR(ch) \
1008 static IIO_DEVICE_ATTR(in_voltage##ch##_scale_available, S_IRUGO, \
1009 mxs_lradc_show_scale_available, NULL, ch)
1010
1011 SHOW_SCALE_AVAILABLE_ATTR(0);
1012 SHOW_SCALE_AVAILABLE_ATTR(1);
1013 SHOW_SCALE_AVAILABLE_ATTR(2);
1014 SHOW_SCALE_AVAILABLE_ATTR(3);
1015 SHOW_SCALE_AVAILABLE_ATTR(4);
1016 SHOW_SCALE_AVAILABLE_ATTR(5);
1017 SHOW_SCALE_AVAILABLE_ATTR(6);
1018 SHOW_SCALE_AVAILABLE_ATTR(7);
1019 SHOW_SCALE_AVAILABLE_ATTR(10);
1020 SHOW_SCALE_AVAILABLE_ATTR(11);
1021 SHOW_SCALE_AVAILABLE_ATTR(12);
1022 SHOW_SCALE_AVAILABLE_ATTR(13);
1023 SHOW_SCALE_AVAILABLE_ATTR(14);
1024 SHOW_SCALE_AVAILABLE_ATTR(15);
1025
1026 static struct attribute *mxs_lradc_attributes[] = {
1027 &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr,
1028 &iio_dev_attr_in_voltage1_scale_available.dev_attr.attr,
1029 &iio_dev_attr_in_voltage2_scale_available.dev_attr.attr,
1030 &iio_dev_attr_in_voltage3_scale_available.dev_attr.attr,
1031 &iio_dev_attr_in_voltage4_scale_available.dev_attr.attr,
1032 &iio_dev_attr_in_voltage5_scale_available.dev_attr.attr,
1033 &iio_dev_attr_in_voltage6_scale_available.dev_attr.attr,
1034 &iio_dev_attr_in_voltage7_scale_available.dev_attr.attr,
1035 &iio_dev_attr_in_voltage10_scale_available.dev_attr.attr,
1036 &iio_dev_attr_in_voltage11_scale_available.dev_attr.attr,
1037 &iio_dev_attr_in_voltage12_scale_available.dev_attr.attr,
1038 &iio_dev_attr_in_voltage13_scale_available.dev_attr.attr,
1039 &iio_dev_attr_in_voltage14_scale_available.dev_attr.attr,
1040 &iio_dev_attr_in_voltage15_scale_available.dev_attr.attr,
1041 NULL
1042 };
1043
1044 static const struct attribute_group mxs_lradc_attribute_group = {
1045 .attrs = mxs_lradc_attributes,
1046 };
1047
1048 static const struct iio_info mxs_lradc_iio_info = {
1049 .driver_module = THIS_MODULE,
1050 .read_raw = mxs_lradc_read_raw,
1051 .write_raw = mxs_lradc_write_raw,
1052 .write_raw_get_fmt = mxs_lradc_write_raw_get_fmt,
1053 .attrs = &mxs_lradc_attribute_group,
1054 };
1055
mxs_lradc_ts_open(struct input_dev * dev)1056 static int mxs_lradc_ts_open(struct input_dev *dev)
1057 {
1058 struct mxs_lradc *lradc = input_get_drvdata(dev);
1059
1060 /* Enable the touch-detect circuitry. */
1061 mxs_lradc_enable_touch_detection(lradc);
1062
1063 return 0;
1064 }
1065
mxs_lradc_disable_ts(struct mxs_lradc * lradc)1066 static void mxs_lradc_disable_ts(struct mxs_lradc *lradc)
1067 {
1068 /* stop all interrupts from firing */
1069 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN |
1070 LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL1) |
1071 LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL2), LRADC_CTRL1);
1072
1073 /* Power-down touchscreen touch-detect circuitry. */
1074 mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
1075 }
1076
mxs_lradc_ts_close(struct input_dev * dev)1077 static void mxs_lradc_ts_close(struct input_dev *dev)
1078 {
1079 struct mxs_lradc *lradc = input_get_drvdata(dev);
1080
1081 mxs_lradc_disable_ts(lradc);
1082 }
1083
mxs_lradc_ts_register(struct mxs_lradc * lradc)1084 static int mxs_lradc_ts_register(struct mxs_lradc *lradc)
1085 {
1086 struct input_dev *input;
1087 struct device *dev = lradc->dev;
1088 int ret;
1089
1090 if (!lradc->use_touchscreen)
1091 return 0;
1092
1093 input = input_allocate_device();
1094 if (!input)
1095 return -ENOMEM;
1096
1097 input->name = DRIVER_NAME;
1098 input->id.bustype = BUS_HOST;
1099 input->dev.parent = dev;
1100 input->open = mxs_lradc_ts_open;
1101 input->close = mxs_lradc_ts_close;
1102
1103 __set_bit(EV_ABS, input->evbit);
1104 __set_bit(EV_KEY, input->evbit);
1105 __set_bit(BTN_TOUCH, input->keybit);
1106 input_set_abs_params(input, ABS_X, 0, LRADC_SINGLE_SAMPLE_MASK, 0, 0);
1107 input_set_abs_params(input, ABS_Y, 0, LRADC_SINGLE_SAMPLE_MASK, 0, 0);
1108 input_set_abs_params(input, ABS_PRESSURE, 0, LRADC_SINGLE_SAMPLE_MASK,
1109 0, 0);
1110
1111 lradc->ts_input = input;
1112 input_set_drvdata(input, lradc);
1113 ret = input_register_device(input);
1114 if (ret)
1115 input_free_device(lradc->ts_input);
1116
1117 return ret;
1118 }
1119
mxs_lradc_ts_unregister(struct mxs_lradc * lradc)1120 static void mxs_lradc_ts_unregister(struct mxs_lradc *lradc)
1121 {
1122 if (!lradc->use_touchscreen)
1123 return;
1124
1125 mxs_lradc_disable_ts(lradc);
1126 input_unregister_device(lradc->ts_input);
1127 }
1128
1129 /*
1130 * IRQ Handling
1131 */
mxs_lradc_handle_irq(int irq,void * data)1132 static irqreturn_t mxs_lradc_handle_irq(int irq, void *data)
1133 {
1134 struct iio_dev *iio = data;
1135 struct mxs_lradc *lradc = iio_priv(iio);
1136 unsigned long reg = readl(lradc->base + LRADC_CTRL1);
1137 uint32_t clr_irq = mxs_lradc_irq_mask(lradc);
1138 const uint32_t ts_irq_mask =
1139 LRADC_CTRL1_TOUCH_DETECT_IRQ |
1140 LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1) |
1141 LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL2);
1142
1143 if (!(reg & mxs_lradc_irq_mask(lradc)))
1144 return IRQ_NONE;
1145
1146 if (lradc->use_touchscreen && (reg & ts_irq_mask)) {
1147 mxs_lradc_handle_touch(lradc);
1148
1149 /* Make sure we don't clear the next conversion's interrupt. */
1150 clr_irq &= ~(LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1) |
1151 LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL2));
1152 }
1153
1154 if (iio_buffer_enabled(iio)) {
1155 if (reg & lradc->buffer_vchans)
1156 iio_trigger_poll(iio->trig);
1157 } else if (reg & LRADC_CTRL1_LRADC_IRQ(0)) {
1158 complete(&lradc->completion);
1159 }
1160
1161 mxs_lradc_reg_clear(lradc, reg & clr_irq, LRADC_CTRL1);
1162
1163 return IRQ_HANDLED;
1164 }
1165
1166 /*
1167 * Trigger handling
1168 */
mxs_lradc_trigger_handler(int irq,void * p)1169 static irqreturn_t mxs_lradc_trigger_handler(int irq, void *p)
1170 {
1171 struct iio_poll_func *pf = p;
1172 struct iio_dev *iio = pf->indio_dev;
1173 struct mxs_lradc *lradc = iio_priv(iio);
1174 const uint32_t chan_value = LRADC_CH_ACCUMULATE |
1175 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
1176 unsigned int i, j = 0;
1177
1178 for_each_set_bit(i, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
1179 lradc->buffer[j] = readl(lradc->base + LRADC_CH(j));
1180 mxs_lradc_reg_wrt(lradc, chan_value, LRADC_CH(j));
1181 lradc->buffer[j] &= LRADC_CH_VALUE_MASK;
1182 lradc->buffer[j] /= LRADC_DELAY_TIMER_LOOP;
1183 j++;
1184 }
1185
1186 iio_push_to_buffers_with_timestamp(iio, lradc->buffer, pf->timestamp);
1187
1188 iio_trigger_notify_done(iio->trig);
1189
1190 return IRQ_HANDLED;
1191 }
1192
mxs_lradc_configure_trigger(struct iio_trigger * trig,bool state)1193 static int mxs_lradc_configure_trigger(struct iio_trigger *trig, bool state)
1194 {
1195 struct iio_dev *iio = iio_trigger_get_drvdata(trig);
1196 struct mxs_lradc *lradc = iio_priv(iio);
1197 const uint32_t st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;
1198
1199 mxs_lradc_reg_wrt(lradc, LRADC_DELAY_KICK, LRADC_DELAY(0) + st);
1200
1201 return 0;
1202 }
1203
1204 static const struct iio_trigger_ops mxs_lradc_trigger_ops = {
1205 .owner = THIS_MODULE,
1206 .set_trigger_state = &mxs_lradc_configure_trigger,
1207 };
1208
mxs_lradc_trigger_init(struct iio_dev * iio)1209 static int mxs_lradc_trigger_init(struct iio_dev *iio)
1210 {
1211 int ret;
1212 struct iio_trigger *trig;
1213 struct mxs_lradc *lradc = iio_priv(iio);
1214
1215 trig = iio_trigger_alloc("%s-dev%i", iio->name, iio->id);
1216 if (trig == NULL)
1217 return -ENOMEM;
1218
1219 trig->dev.parent = lradc->dev;
1220 iio_trigger_set_drvdata(trig, iio);
1221 trig->ops = &mxs_lradc_trigger_ops;
1222
1223 ret = iio_trigger_register(trig);
1224 if (ret) {
1225 iio_trigger_free(trig);
1226 return ret;
1227 }
1228
1229 lradc->trig = trig;
1230
1231 return 0;
1232 }
1233
mxs_lradc_trigger_remove(struct iio_dev * iio)1234 static void mxs_lradc_trigger_remove(struct iio_dev *iio)
1235 {
1236 struct mxs_lradc *lradc = iio_priv(iio);
1237
1238 iio_trigger_unregister(lradc->trig);
1239 iio_trigger_free(lradc->trig);
1240 }
1241
mxs_lradc_buffer_preenable(struct iio_dev * iio)1242 static int mxs_lradc_buffer_preenable(struct iio_dev *iio)
1243 {
1244 struct mxs_lradc *lradc = iio_priv(iio);
1245 int ret = 0, chan, ofs = 0;
1246 unsigned long enable = 0;
1247 uint32_t ctrl4_set = 0;
1248 uint32_t ctrl4_clr = 0;
1249 uint32_t ctrl1_irq = 0;
1250 const uint32_t chan_value = LRADC_CH_ACCUMULATE |
1251 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
1252 const int len = bitmap_weight(iio->active_scan_mask,
1253 LRADC_MAX_TOTAL_CHANS);
1254
1255 if (!len)
1256 return -EINVAL;
1257
1258 /*
1259 * Lock the driver so raw access can not be done during buffered
1260 * operation. This simplifies the code a lot.
1261 */
1262 ret = mutex_trylock(&lradc->lock);
1263 if (!ret)
1264 return -EBUSY;
1265
1266 lradc->buffer = kmalloc_array(len, sizeof(*lradc->buffer), GFP_KERNEL);
1267 if (!lradc->buffer) {
1268 ret = -ENOMEM;
1269 goto err_mem;
1270 }
1271
1272 if (lradc->soc == IMX28_LRADC)
1273 mxs_lradc_reg_clear(lradc,
1274 lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
1275 LRADC_CTRL1);
1276 mxs_lradc_reg_clear(lradc, lradc->buffer_vchans, LRADC_CTRL0);
1277
1278 for_each_set_bit(chan, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
1279 ctrl4_set |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs);
1280 ctrl4_clr |= LRADC_CTRL4_LRADCSELECT_MASK(ofs);
1281 ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs);
1282 mxs_lradc_reg_wrt(lradc, chan_value, LRADC_CH(ofs));
1283 bitmap_set(&enable, ofs, 1);
1284 ofs++;
1285 }
1286
1287 mxs_lradc_reg_clear(lradc, LRADC_DELAY_TRIGGER_LRADCS_MASK |
1288 LRADC_DELAY_KICK, LRADC_DELAY(0));
1289 mxs_lradc_reg_clear(lradc, ctrl4_clr, LRADC_CTRL4);
1290 mxs_lradc_reg_set(lradc, ctrl4_set, LRADC_CTRL4);
1291 mxs_lradc_reg_set(lradc, ctrl1_irq, LRADC_CTRL1);
1292 mxs_lradc_reg_set(lradc, enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET,
1293 LRADC_DELAY(0));
1294
1295 return 0;
1296
1297 err_mem:
1298 mutex_unlock(&lradc->lock);
1299 return ret;
1300 }
1301
mxs_lradc_buffer_postdisable(struct iio_dev * iio)1302 static int mxs_lradc_buffer_postdisable(struct iio_dev *iio)
1303 {
1304 struct mxs_lradc *lradc = iio_priv(iio);
1305
1306 mxs_lradc_reg_clear(lradc, LRADC_DELAY_TRIGGER_LRADCS_MASK |
1307 LRADC_DELAY_KICK, LRADC_DELAY(0));
1308
1309 mxs_lradc_reg_clear(lradc, lradc->buffer_vchans, LRADC_CTRL0);
1310 if (lradc->soc == IMX28_LRADC)
1311 mxs_lradc_reg_clear(lradc,
1312 lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
1313 LRADC_CTRL1);
1314
1315 kfree(lradc->buffer);
1316 mutex_unlock(&lradc->lock);
1317
1318 return 0;
1319 }
1320
mxs_lradc_validate_scan_mask(struct iio_dev * iio,const unsigned long * mask)1321 static bool mxs_lradc_validate_scan_mask(struct iio_dev *iio,
1322 const unsigned long *mask)
1323 {
1324 struct mxs_lradc *lradc = iio_priv(iio);
1325 const int map_chans = bitmap_weight(mask, LRADC_MAX_TOTAL_CHANS);
1326 int rsvd_chans = 0;
1327 unsigned long rsvd_mask = 0;
1328
1329 if (lradc->use_touchbutton)
1330 rsvd_mask |= CHAN_MASK_TOUCHBUTTON;
1331 if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_4WIRE)
1332 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_4WIRE;
1333 if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_5WIRE)
1334 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_5WIRE;
1335
1336 if (lradc->use_touchbutton)
1337 rsvd_chans++;
1338 if (lradc->use_touchscreen)
1339 rsvd_chans += 2;
1340
1341 /* Test for attempts to map channels with special mode of operation. */
1342 if (bitmap_intersects(mask, &rsvd_mask, LRADC_MAX_TOTAL_CHANS))
1343 return false;
1344
1345 /* Test for attempts to map more channels then available slots. */
1346 if (map_chans + rsvd_chans > LRADC_MAX_MAPPED_CHANS)
1347 return false;
1348
1349 return true;
1350 }
1351
1352 static const struct iio_buffer_setup_ops mxs_lradc_buffer_ops = {
1353 .preenable = &mxs_lradc_buffer_preenable,
1354 .postenable = &iio_triggered_buffer_postenable,
1355 .predisable = &iio_triggered_buffer_predisable,
1356 .postdisable = &mxs_lradc_buffer_postdisable,
1357 .validate_scan_mask = &mxs_lradc_validate_scan_mask,
1358 };
1359
1360 /*
1361 * Driver initialization
1362 */
1363
1364 #define MXS_ADC_CHAN(idx, chan_type) { \
1365 .type = (chan_type), \
1366 .indexed = 1, \
1367 .scan_index = (idx), \
1368 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1369 BIT(IIO_CHAN_INFO_SCALE), \
1370 .channel = (idx), \
1371 .address = (idx), \
1372 .scan_type = { \
1373 .sign = 'u', \
1374 .realbits = LRADC_RESOLUTION, \
1375 .storagebits = 32, \
1376 }, \
1377 }
1378
1379 static const struct iio_chan_spec mxs_lradc_chan_spec[] = {
1380 MXS_ADC_CHAN(0, IIO_VOLTAGE),
1381 MXS_ADC_CHAN(1, IIO_VOLTAGE),
1382 MXS_ADC_CHAN(2, IIO_VOLTAGE),
1383 MXS_ADC_CHAN(3, IIO_VOLTAGE),
1384 MXS_ADC_CHAN(4, IIO_VOLTAGE),
1385 MXS_ADC_CHAN(5, IIO_VOLTAGE),
1386 MXS_ADC_CHAN(6, IIO_VOLTAGE),
1387 MXS_ADC_CHAN(7, IIO_VOLTAGE), /* VBATT */
1388 /* Combined Temperature sensors */
1389 {
1390 .type = IIO_TEMP,
1391 .indexed = 1,
1392 .scan_index = 8,
1393 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1394 BIT(IIO_CHAN_INFO_OFFSET) |
1395 BIT(IIO_CHAN_INFO_SCALE),
1396 .channel = 8,
1397 .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
1398 },
1399 /* Hidden channel to keep indexes */
1400 {
1401 .type = IIO_TEMP,
1402 .indexed = 1,
1403 .scan_index = -1,
1404 .channel = 9,
1405 },
1406 MXS_ADC_CHAN(10, IIO_VOLTAGE), /* VDDIO */
1407 MXS_ADC_CHAN(11, IIO_VOLTAGE), /* VTH */
1408 MXS_ADC_CHAN(12, IIO_VOLTAGE), /* VDDA */
1409 MXS_ADC_CHAN(13, IIO_VOLTAGE), /* VDDD */
1410 MXS_ADC_CHAN(14, IIO_VOLTAGE), /* VBG */
1411 MXS_ADC_CHAN(15, IIO_VOLTAGE), /* VDD5V */
1412 };
1413
mxs_lradc_hw_init(struct mxs_lradc * lradc)1414 static int mxs_lradc_hw_init(struct mxs_lradc *lradc)
1415 {
1416 /* The ADC always uses DELAY CHANNEL 0. */
1417 const uint32_t adc_cfg =
1418 (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + 0)) |
1419 (LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET);
1420
1421 int ret = stmp_reset_block(lradc->base);
1422
1423 if (ret)
1424 return ret;
1425
1426 /* Configure DELAY CHANNEL 0 for generic ADC sampling. */
1427 mxs_lradc_reg_wrt(lradc, adc_cfg, LRADC_DELAY(0));
1428
1429 /* Disable remaining DELAY CHANNELs */
1430 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(1));
1431 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(2));
1432 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(3));
1433
1434 /* Configure the touchscreen type */
1435 if (lradc->soc == IMX28_LRADC) {
1436 mxs_lradc_reg_clear(lradc, LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE,
1437 LRADC_CTRL0);
1438
1439 if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_5WIRE)
1440 mxs_lradc_reg_set(lradc, LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE,
1441 LRADC_CTRL0);
1442 }
1443
1444 /* Start internal temperature sensing. */
1445 mxs_lradc_reg_wrt(lradc, 0, LRADC_CTRL2);
1446
1447 return 0;
1448 }
1449
mxs_lradc_hw_stop(struct mxs_lradc * lradc)1450 static void mxs_lradc_hw_stop(struct mxs_lradc *lradc)
1451 {
1452 int i;
1453
1454 mxs_lradc_reg_clear(lradc, mxs_lradc_irq_en_mask(lradc), LRADC_CTRL1);
1455
1456 for (i = 0; i < LRADC_MAX_DELAY_CHANS; i++)
1457 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(i));
1458 }
1459
1460 static const struct of_device_id mxs_lradc_dt_ids[] = {
1461 { .compatible = "fsl,imx23-lradc", .data = (void *)IMX23_LRADC, },
1462 { .compatible = "fsl,imx28-lradc", .data = (void *)IMX28_LRADC, },
1463 { /* sentinel */ }
1464 };
1465 MODULE_DEVICE_TABLE(of, mxs_lradc_dt_ids);
1466
mxs_lradc_probe_touchscreen(struct mxs_lradc * lradc,struct device_node * lradc_node)1467 static int mxs_lradc_probe_touchscreen(struct mxs_lradc *lradc,
1468 struct device_node *lradc_node)
1469 {
1470 int ret;
1471 u32 ts_wires = 0, adapt;
1472
1473 ret = of_property_read_u32(lradc_node, "fsl,lradc-touchscreen-wires",
1474 &ts_wires);
1475 if (ret)
1476 return -ENODEV; /* touchscreen feature disabled */
1477
1478 switch (ts_wires) {
1479 case 4:
1480 lradc->use_touchscreen = MXS_LRADC_TOUCHSCREEN_4WIRE;
1481 break;
1482 case 5:
1483 if (lradc->soc == IMX28_LRADC) {
1484 lradc->use_touchscreen = MXS_LRADC_TOUCHSCREEN_5WIRE;
1485 break;
1486 }
1487 /* fall through an error message for i.MX23 */
1488 default:
1489 dev_err(lradc->dev,
1490 "Unsupported number of touchscreen wires (%d)\n",
1491 ts_wires);
1492 return -EINVAL;
1493 }
1494
1495 lradc->over_sample_cnt = 4;
1496 ret = of_property_read_u32(lradc_node, "fsl,ave-ctrl", &adapt);
1497 if (ret == 0)
1498 lradc->over_sample_cnt = adapt;
1499
1500 lradc->over_sample_delay = 2;
1501 ret = of_property_read_u32(lradc_node, "fsl,ave-delay", &adapt);
1502 if (ret == 0)
1503 lradc->over_sample_delay = adapt;
1504
1505 lradc->settling_delay = 10;
1506 ret = of_property_read_u32(lradc_node, "fsl,settling", &adapt);
1507 if (ret == 0)
1508 lradc->settling_delay = adapt;
1509
1510 return 0;
1511 }
1512
mxs_lradc_probe(struct platform_device * pdev)1513 static int mxs_lradc_probe(struct platform_device *pdev)
1514 {
1515 const struct of_device_id *of_id =
1516 of_match_device(mxs_lradc_dt_ids, &pdev->dev);
1517 const struct mxs_lradc_of_config *of_cfg =
1518 &mxs_lradc_of_config[(enum mxs_lradc_id)of_id->data];
1519 struct device *dev = &pdev->dev;
1520 struct device_node *node = dev->of_node;
1521 struct mxs_lradc *lradc;
1522 struct iio_dev *iio;
1523 struct resource *iores;
1524 int ret = 0, touch_ret;
1525 int i, s;
1526 uint64_t scale_uv;
1527
1528 /* Allocate the IIO device. */
1529 iio = devm_iio_device_alloc(dev, sizeof(*lradc));
1530 if (!iio) {
1531 dev_err(dev, "Failed to allocate IIO device\n");
1532 return -ENOMEM;
1533 }
1534
1535 lradc = iio_priv(iio);
1536 lradc->soc = (enum mxs_lradc_id)of_id->data;
1537
1538 /* Grab the memory area */
1539 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1540 lradc->dev = &pdev->dev;
1541 lradc->base = devm_ioremap_resource(dev, iores);
1542 if (IS_ERR(lradc->base))
1543 return PTR_ERR(lradc->base);
1544
1545 lradc->clk = devm_clk_get(&pdev->dev, NULL);
1546 if (IS_ERR(lradc->clk)) {
1547 dev_err(dev, "Failed to get the delay unit clock\n");
1548 return PTR_ERR(lradc->clk);
1549 }
1550 ret = clk_prepare_enable(lradc->clk);
1551 if (ret != 0) {
1552 dev_err(dev, "Failed to enable the delay unit clock\n");
1553 return ret;
1554 }
1555
1556 touch_ret = mxs_lradc_probe_touchscreen(lradc, node);
1557
1558 if (touch_ret == 0)
1559 lradc->buffer_vchans = BUFFER_VCHANS_LIMITED;
1560 else
1561 lradc->buffer_vchans = BUFFER_VCHANS_ALL;
1562
1563 /* Grab all IRQ sources */
1564 for (i = 0; i < of_cfg->irq_count; i++) {
1565 lradc->irq[i] = platform_get_irq(pdev, i);
1566 if (lradc->irq[i] < 0) {
1567 ret = lradc->irq[i];
1568 goto err_clk;
1569 }
1570
1571 ret = devm_request_irq(dev, lradc->irq[i],
1572 mxs_lradc_handle_irq, 0,
1573 of_cfg->irq_name[i], iio);
1574 if (ret)
1575 goto err_clk;
1576 }
1577
1578 lradc->vref_mv = of_cfg->vref_mv;
1579
1580 platform_set_drvdata(pdev, iio);
1581
1582 init_completion(&lradc->completion);
1583 mutex_init(&lradc->lock);
1584
1585 iio->name = pdev->name;
1586 iio->dev.parent = &pdev->dev;
1587 iio->info = &mxs_lradc_iio_info;
1588 iio->modes = INDIO_DIRECT_MODE;
1589 iio->channels = mxs_lradc_chan_spec;
1590 iio->num_channels = ARRAY_SIZE(mxs_lradc_chan_spec);
1591 iio->masklength = LRADC_MAX_TOTAL_CHANS;
1592
1593 ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time,
1594 &mxs_lradc_trigger_handler,
1595 &mxs_lradc_buffer_ops);
1596 if (ret)
1597 goto err_clk;
1598
1599 ret = mxs_lradc_trigger_init(iio);
1600 if (ret)
1601 goto err_trig;
1602
1603 /* Populate available ADC input ranges */
1604 for (i = 0; i < LRADC_MAX_TOTAL_CHANS; i++) {
1605 for (s = 0; s < ARRAY_SIZE(lradc->scale_avail[i]); s++) {
1606 /*
1607 * [s=0] = optional divider by two disabled (default)
1608 * [s=1] = optional divider by two enabled
1609 *
1610 * The scale is calculated by doing:
1611 * Vref >> (realbits - s)
1612 * which multiplies by two on the second component
1613 * of the array.
1614 */
1615 scale_uv = ((u64)lradc->vref_mv[i] * 100000000) >>
1616 (LRADC_RESOLUTION - s);
1617 lradc->scale_avail[i][s].nano =
1618 do_div(scale_uv, 100000000) * 10;
1619 lradc->scale_avail[i][s].integer = scale_uv;
1620 }
1621 }
1622
1623 /* Configure the hardware. */
1624 ret = mxs_lradc_hw_init(lradc);
1625 if (ret)
1626 goto err_dev;
1627
1628 /* Register the touchscreen input device. */
1629 if (touch_ret == 0) {
1630 ret = mxs_lradc_ts_register(lradc);
1631 if (ret)
1632 goto err_ts_register;
1633 }
1634
1635 /* Register IIO device. */
1636 ret = iio_device_register(iio);
1637 if (ret) {
1638 dev_err(dev, "Failed to register IIO device\n");
1639 goto err_ts;
1640 }
1641
1642 return 0;
1643
1644 err_ts:
1645 mxs_lradc_ts_unregister(lradc);
1646 err_ts_register:
1647 mxs_lradc_hw_stop(lradc);
1648 err_dev:
1649 mxs_lradc_trigger_remove(iio);
1650 err_trig:
1651 iio_triggered_buffer_cleanup(iio);
1652 err_clk:
1653 clk_disable_unprepare(lradc->clk);
1654 return ret;
1655 }
1656
mxs_lradc_remove(struct platform_device * pdev)1657 static int mxs_lradc_remove(struct platform_device *pdev)
1658 {
1659 struct iio_dev *iio = platform_get_drvdata(pdev);
1660 struct mxs_lradc *lradc = iio_priv(iio);
1661
1662 iio_device_unregister(iio);
1663 mxs_lradc_ts_unregister(lradc);
1664 mxs_lradc_hw_stop(lradc);
1665 mxs_lradc_trigger_remove(iio);
1666 iio_triggered_buffer_cleanup(iio);
1667
1668 clk_disable_unprepare(lradc->clk);
1669 return 0;
1670 }
1671
1672 static struct platform_driver mxs_lradc_driver = {
1673 .driver = {
1674 .name = DRIVER_NAME,
1675 .owner = THIS_MODULE,
1676 .of_match_table = mxs_lradc_dt_ids,
1677 },
1678 .probe = mxs_lradc_probe,
1679 .remove = mxs_lradc_remove,
1680 };
1681
1682 module_platform_driver(mxs_lradc_driver);
1683
1684 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
1685 MODULE_DESCRIPTION("Freescale i.MX28 LRADC driver");
1686 MODULE_LICENSE("GPL v2");
1687 MODULE_ALIAS("platform:" DRIVER_NAME);
1688