1 /*
2 * drivers/media/platform/omap24xxcam.h
3 *
4 * Copyright (C) 2004 MontaVista Software, Inc.
5 * Copyright (C) 2004 Texas Instruments.
6 * Copyright (C) 2007 Nokia Corporation.
7 *
8 * Contact: Sakari Ailus <sakari.ailus@nokia.com>
9 *
10 * Based on code from Andy Lowe <source@mvista.com>.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * version 2 as published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 * 02110-1301 USA
25 */
26
27 #ifndef OMAP24XXCAM_H
28 #define OMAP24XXCAM_H
29
30 #include <media/videobuf-dma-sg.h>
31 #include <media/v4l2-device.h>
32 #include "v4l2-int-device.h"
33
34 /*
35 *
36 * General driver related definitions.
37 *
38 */
39
40 #define CAM_NAME "omap24xxcam"
41
42 #define CAM_MCLK 96000000
43
44 /* number of bytes transferred per DMA request */
45 #define DMA_THRESHOLD 32
46
47 /*
48 * NUM_CAMDMA_CHANNELS is the number of logical channels provided by
49 * the camera DMA controller.
50 */
51 #define NUM_CAMDMA_CHANNELS 4
52
53 /*
54 * NUM_SG_DMA is the number of scatter-gather DMA transfers that can
55 * be queued. (We don't have any overlay sglists now.)
56 */
57 #define NUM_SG_DMA (VIDEO_MAX_FRAME)
58
59 /*
60 *
61 * Register definitions.
62 *
63 */
64
65 /* subsystem register block offsets */
66 #define CC_REG_OFFSET 0x00000400
67 #define CAMDMA_REG_OFFSET 0x00000800
68 #define CAMMMU_REG_OFFSET 0x00000C00
69
70 /* define camera subsystem register offsets */
71 #define CAM_REVISION 0x000
72 #define CAM_SYSCONFIG 0x010
73 #define CAM_SYSSTATUS 0x014
74 #define CAM_IRQSTATUS 0x018
75 #define CAM_GPO 0x040
76 #define CAM_GPI 0x050
77
78 /* define camera core register offsets */
79 #define CC_REVISION 0x000
80 #define CC_SYSCONFIG 0x010
81 #define CC_SYSSTATUS 0x014
82 #define CC_IRQSTATUS 0x018
83 #define CC_IRQENABLE 0x01C
84 #define CC_CTRL 0x040
85 #define CC_CTRL_DMA 0x044
86 #define CC_CTRL_XCLK 0x048
87 #define CC_FIFODATA 0x04C
88 #define CC_TEST 0x050
89 #define CC_GENPAR 0x054
90 #define CC_CCPFSCR 0x058
91 #define CC_CCPFECR 0x05C
92 #define CC_CCPLSCR 0x060
93 #define CC_CCPLECR 0x064
94 #define CC_CCPDFR 0x068
95
96 /* define camera dma register offsets */
97 #define CAMDMA_REVISION 0x000
98 #define CAMDMA_IRQSTATUS_L0 0x008
99 #define CAMDMA_IRQSTATUS_L1 0x00C
100 #define CAMDMA_IRQSTATUS_L2 0x010
101 #define CAMDMA_IRQSTATUS_L3 0x014
102 #define CAMDMA_IRQENABLE_L0 0x018
103 #define CAMDMA_IRQENABLE_L1 0x01C
104 #define CAMDMA_IRQENABLE_L2 0x020
105 #define CAMDMA_IRQENABLE_L3 0x024
106 #define CAMDMA_SYSSTATUS 0x028
107 #define CAMDMA_OCP_SYSCONFIG 0x02C
108 #define CAMDMA_CAPS_0 0x064
109 #define CAMDMA_CAPS_2 0x06C
110 #define CAMDMA_CAPS_3 0x070
111 #define CAMDMA_CAPS_4 0x074
112 #define CAMDMA_GCR 0x078
113 #define CAMDMA_CCR(n) (0x080 + (n)*0x60)
114 #define CAMDMA_CLNK_CTRL(n) (0x084 + (n)*0x60)
115 #define CAMDMA_CICR(n) (0x088 + (n)*0x60)
116 #define CAMDMA_CSR(n) (0x08C + (n)*0x60)
117 #define CAMDMA_CSDP(n) (0x090 + (n)*0x60)
118 #define CAMDMA_CEN(n) (0x094 + (n)*0x60)
119 #define CAMDMA_CFN(n) (0x098 + (n)*0x60)
120 #define CAMDMA_CSSA(n) (0x09C + (n)*0x60)
121 #define CAMDMA_CDSA(n) (0x0A0 + (n)*0x60)
122 #define CAMDMA_CSEI(n) (0x0A4 + (n)*0x60)
123 #define CAMDMA_CSFI(n) (0x0A8 + (n)*0x60)
124 #define CAMDMA_CDEI(n) (0x0AC + (n)*0x60)
125 #define CAMDMA_CDFI(n) (0x0B0 + (n)*0x60)
126 #define CAMDMA_CSAC(n) (0x0B4 + (n)*0x60)
127 #define CAMDMA_CDAC(n) (0x0B8 + (n)*0x60)
128 #define CAMDMA_CCEN(n) (0x0BC + (n)*0x60)
129 #define CAMDMA_CCFN(n) (0x0C0 + (n)*0x60)
130 #define CAMDMA_COLOR(n) (0x0C4 + (n)*0x60)
131
132 /* define camera mmu register offsets */
133 #define CAMMMU_REVISION 0x000
134 #define CAMMMU_SYSCONFIG 0x010
135 #define CAMMMU_SYSSTATUS 0x014
136 #define CAMMMU_IRQSTATUS 0x018
137 #define CAMMMU_IRQENABLE 0x01C
138 #define CAMMMU_WALKING_ST 0x040
139 #define CAMMMU_CNTL 0x044
140 #define CAMMMU_FAULT_AD 0x048
141 #define CAMMMU_TTB 0x04C
142 #define CAMMMU_LOCK 0x050
143 #define CAMMMU_LD_TLB 0x054
144 #define CAMMMU_CAM 0x058
145 #define CAMMMU_RAM 0x05C
146 #define CAMMMU_GFLUSH 0x060
147 #define CAMMMU_FLUSH_ENTRY 0x064
148 #define CAMMMU_READ_CAM 0x068
149 #define CAMMMU_READ_RAM 0x06C
150 #define CAMMMU_EMU_FAULT_AD 0x070
151
152 /* Define bit fields within selected registers */
153 #define CAM_REVISION_MAJOR (15 << 4)
154 #define CAM_REVISION_MAJOR_SHIFT 4
155 #define CAM_REVISION_MINOR (15 << 0)
156 #define CAM_REVISION_MINOR_SHIFT 0
157
158 #define CAM_SYSCONFIG_SOFTRESET (1 << 1)
159 #define CAM_SYSCONFIG_AUTOIDLE (1 << 0)
160
161 #define CAM_SYSSTATUS_RESETDONE (1 << 0)
162
163 #define CAM_IRQSTATUS_CC_IRQ (1 << 4)
164 #define CAM_IRQSTATUS_MMU_IRQ (1 << 3)
165 #define CAM_IRQSTATUS_DMA_IRQ2 (1 << 2)
166 #define CAM_IRQSTATUS_DMA_IRQ1 (1 << 1)
167 #define CAM_IRQSTATUS_DMA_IRQ0 (1 << 0)
168
169 #define CAM_GPO_CAM_S_P_EN (1 << 1)
170 #define CAM_GPO_CAM_CCP_MODE (1 << 0)
171
172 #define CAM_GPI_CC_DMA_REQ1 (1 << 24)
173 #define CAP_GPI_CC_DMA_REQ0 (1 << 23)
174 #define CAP_GPI_CAM_MSTANDBY (1 << 21)
175 #define CAP_GPI_CAM_WAIT (1 << 20)
176 #define CAP_GPI_CAM_S_DATA (1 << 17)
177 #define CAP_GPI_CAM_S_CLK (1 << 16)
178 #define CAP_GPI_CAM_P_DATA (0xFFF << 3)
179 #define CAP_GPI_CAM_P_DATA_SHIFT 3
180 #define CAP_GPI_CAM_P_VS (1 << 2)
181 #define CAP_GPI_CAM_P_HS (1 << 1)
182 #define CAP_GPI_CAM_P_CLK (1 << 0)
183
184 #define CC_REVISION_MAJOR (15 << 4)
185 #define CC_REVISION_MAJOR_SHIFT 4
186 #define CC_REVISION_MINOR (15 << 0)
187 #define CC_REVISION_MINOR_SHIFT 0
188
189 #define CC_SYSCONFIG_SIDLEMODE (3 << 3)
190 #define CC_SYSCONFIG_SIDLEMODE_FIDLE (0 << 3)
191 #define CC_SYSCONFIG_SIDLEMODE_NIDLE (1 << 3)
192 #define CC_SYSCONFIG_SOFTRESET (1 << 1)
193 #define CC_SYSCONFIG_AUTOIDLE (1 << 0)
194
195 #define CC_SYSSTATUS_RESETDONE (1 << 0)
196
197 #define CC_IRQSTATUS_FS_IRQ (1 << 19)
198 #define CC_IRQSTATUS_LE_IRQ (1 << 18)
199 #define CC_IRQSTATUS_LS_IRQ (1 << 17)
200 #define CC_IRQSTATUS_FE_IRQ (1 << 16)
201 #define CC_IRQSTATUS_FW_ERR_IRQ (1 << 10)
202 #define CC_IRQSTATUS_FSC_ERR_IRQ (1 << 9)
203 #define CC_IRQSTATUS_SSC_ERR_IRQ (1 << 8)
204 #define CC_IRQSTATUS_FIFO_NOEMPTY_IRQ (1 << 4)
205 #define CC_IRQSTATUS_FIFO_FULL_IRQ (1 << 3)
206 #define CC_IRQSTATUS_FIFO_THR_IRQ (1 << 2)
207 #define CC_IRQSTATUS_FIFO_OF_IRQ (1 << 1)
208 #define CC_IRQSTATUS_FIFO_UF_IRQ (1 << 0)
209
210 #define CC_IRQENABLE_FS_IRQ (1 << 19)
211 #define CC_IRQENABLE_LE_IRQ (1 << 18)
212 #define CC_IRQENABLE_LS_IRQ (1 << 17)
213 #define CC_IRQENABLE_FE_IRQ (1 << 16)
214 #define CC_IRQENABLE_FW_ERR_IRQ (1 << 10)
215 #define CC_IRQENABLE_FSC_ERR_IRQ (1 << 9)
216 #define CC_IRQENABLE_SSC_ERR_IRQ (1 << 8)
217 #define CC_IRQENABLE_FIFO_NOEMPTY_IRQ (1 << 4)
218 #define CC_IRQENABLE_FIFO_FULL_IRQ (1 << 3)
219 #define CC_IRQENABLE_FIFO_THR_IRQ (1 << 2)
220 #define CC_IRQENABLE_FIFO_OF_IRQ (1 << 1)
221 #define CC_IRQENABLE_FIFO_UF_IRQ (1 << 0)
222
223 #define CC_CTRL_CC_ONE_SHOT (1 << 20)
224 #define CC_CTRL_CC_IF_SYNCHRO (1 << 19)
225 #define CC_CTRL_CC_RST (1 << 18)
226 #define CC_CTRL_CC_FRAME_TRIG (1 << 17)
227 #define CC_CTRL_CC_EN (1 << 16)
228 #define CC_CTRL_NOBT_SYNCHRO (1 << 13)
229 #define CC_CTRL_BT_CORRECT (1 << 12)
230 #define CC_CTRL_PAR_ORDERCAM (1 << 11)
231 #define CC_CTRL_PAR_CLK_POL (1 << 10)
232 #define CC_CTRL_NOBT_HS_POL (1 << 9)
233 #define CC_CTRL_NOBT_VS_POL (1 << 8)
234 #define CC_CTRL_PAR_MODE (7 << 1)
235 #define CC_CTRL_PAR_MODE_SHIFT 1
236 #define CC_CTRL_PAR_MODE_NOBT8 (0 << 1)
237 #define CC_CTRL_PAR_MODE_NOBT10 (1 << 1)
238 #define CC_CTRL_PAR_MODE_NOBT12 (2 << 1)
239 #define CC_CTRL_PAR_MODE_BT8 (4 << 1)
240 #define CC_CTRL_PAR_MODE_BT10 (5 << 1)
241 #define CC_CTRL_PAR_MODE_FIFOTEST (7 << 1)
242 #define CC_CTRL_CCP_MODE (1 << 0)
243
244 #define CC_CTRL_DMA_EN (1 << 8)
245 #define CC_CTRL_DMA_FIFO_THRESHOLD (0x7F << 0)
246 #define CC_CTRL_DMA_FIFO_THRESHOLD_SHIFT 0
247
248 #define CC_CTRL_XCLK_DIV (0x1F << 0)
249 #define CC_CTRL_XCLK_DIV_SHIFT 0
250 #define CC_CTRL_XCLK_DIV_STABLE_LOW (0 << 0)
251 #define CC_CTRL_XCLK_DIV_STABLE_HIGH (1 << 0)
252 #define CC_CTRL_XCLK_DIV_BYPASS (31 << 0)
253
254 #define CC_TEST_FIFO_RD_POINTER (0xFF << 24)
255 #define CC_TEST_FIFO_RD_POINTER_SHIFT 24
256 #define CC_TEST_FIFO_WR_POINTER (0xFF << 16)
257 #define CC_TEST_FIFO_WR_POINTER_SHIFT 16
258 #define CC_TEST_FIFO_LEVEL (0xFF << 8)
259 #define CC_TEST_FIFO_LEVEL_SHIFT 8
260 #define CC_TEST_FIFO_LEVEL_PEAK (0xFF << 0)
261 #define CC_TEST_FIFO_LEVEL_PEAK_SHIFT 0
262
263 #define CC_GENPAR_FIFO_DEPTH (7 << 0)
264 #define CC_GENPAR_FIFO_DEPTH_SHIFT 0
265
266 #define CC_CCPDFR_ALPHA (0xFF << 8)
267 #define CC_CCPDFR_ALPHA_SHIFT 8
268 #define CC_CCPDFR_DATAFORMAT (15 << 0)
269 #define CC_CCPDFR_DATAFORMAT_SHIFT 0
270 #define CC_CCPDFR_DATAFORMAT_YUV422BE (0 << 0)
271 #define CC_CCPDFR_DATAFORMAT_YUV422 (1 << 0)
272 #define CC_CCPDFR_DATAFORMAT_YUV420 (2 << 0)
273 #define CC_CCPDFR_DATAFORMAT_RGB444 (4 << 0)
274 #define CC_CCPDFR_DATAFORMAT_RGB565 (5 << 0)
275 #define CC_CCPDFR_DATAFORMAT_RGB888NDE (6 << 0)
276 #define CC_CCPDFR_DATAFORMAT_RGB888 (7 << 0)
277 #define CC_CCPDFR_DATAFORMAT_RAW8NDE (8 << 0)
278 #define CC_CCPDFR_DATAFORMAT_RAW8 (9 << 0)
279 #define CC_CCPDFR_DATAFORMAT_RAW10NDE (10 << 0)
280 #define CC_CCPDFR_DATAFORMAT_RAW10 (11 << 0)
281 #define CC_CCPDFR_DATAFORMAT_RAW12NDE (12 << 0)
282 #define CC_CCPDFR_DATAFORMAT_RAW12 (13 << 0)
283 #define CC_CCPDFR_DATAFORMAT_JPEG8 (15 << 0)
284
285 #define CAMDMA_REVISION_MAJOR (15 << 4)
286 #define CAMDMA_REVISION_MAJOR_SHIFT 4
287 #define CAMDMA_REVISION_MINOR (15 << 0)
288 #define CAMDMA_REVISION_MINOR_SHIFT 0
289
290 #define CAMDMA_OCP_SYSCONFIG_MIDLEMODE (3 << 12)
291 #define CAMDMA_OCP_SYSCONFIG_MIDLEMODE_FSTANDBY (0 << 12)
292 #define CAMDMA_OCP_SYSCONFIG_MIDLEMODE_NSTANDBY (1 << 12)
293 #define CAMDMA_OCP_SYSCONFIG_MIDLEMODE_SSTANDBY (2 << 12)
294 #define CAMDMA_OCP_SYSCONFIG_FUNC_CLOCK (1 << 9)
295 #define CAMDMA_OCP_SYSCONFIG_OCP_CLOCK (1 << 8)
296 #define CAMDMA_OCP_SYSCONFIG_EMUFREE (1 << 5)
297 #define CAMDMA_OCP_SYSCONFIG_SIDLEMODE (3 << 3)
298 #define CAMDMA_OCP_SYSCONFIG_SIDLEMODE_FIDLE (0 << 3)
299 #define CAMDMA_OCP_SYSCONFIG_SIDLEMODE_NIDLE (1 << 3)
300 #define CAMDMA_OCP_SYSCONFIG_SIDLEMODE_SIDLE (2 << 3)
301 #define CAMDMA_OCP_SYSCONFIG_SOFTRESET (1 << 1)
302 #define CAMDMA_OCP_SYSCONFIG_AUTOIDLE (1 << 0)
303
304 #define CAMDMA_SYSSTATUS_RESETDONE (1 << 0)
305
306 #define CAMDMA_GCR_ARBITRATION_RATE (0xFF << 16)
307 #define CAMDMA_GCR_ARBITRATION_RATE_SHIFT 16
308 #define CAMDMA_GCR_MAX_CHANNEL_FIFO_DEPTH (0xFF << 0)
309 #define CAMDMA_GCR_MAX_CHANNEL_FIFO_DEPTH_SHIFT 0
310
311 #define CAMDMA_CCR_SEL_SRC_DST_SYNC (1 << 24)
312 #define CAMDMA_CCR_PREFETCH (1 << 23)
313 #define CAMDMA_CCR_SUPERVISOR (1 << 22)
314 #define CAMDMA_CCR_SECURE (1 << 21)
315 #define CAMDMA_CCR_BS (1 << 18)
316 #define CAMDMA_CCR_TRANSPARENT_COPY_ENABLE (1 << 17)
317 #define CAMDMA_CCR_CONSTANT_FILL_ENABLE (1 << 16)
318 #define CAMDMA_CCR_DST_AMODE (3 << 14)
319 #define CAMDMA_CCR_DST_AMODE_CONST_ADDR (0 << 14)
320 #define CAMDMA_CCR_DST_AMODE_POST_INC (1 << 14)
321 #define CAMDMA_CCR_DST_AMODE_SGL_IDX (2 << 14)
322 #define CAMDMA_CCR_DST_AMODE_DBL_IDX (3 << 14)
323 #define CAMDMA_CCR_SRC_AMODE (3 << 12)
324 #define CAMDMA_CCR_SRC_AMODE_CONST_ADDR (0 << 12)
325 #define CAMDMA_CCR_SRC_AMODE_POST_INC (1 << 12)
326 #define CAMDMA_CCR_SRC_AMODE_SGL_IDX (2 << 12)
327 #define CAMDMA_CCR_SRC_AMODE_DBL_IDX (3 << 12)
328 #define CAMDMA_CCR_WR_ACTIVE (1 << 10)
329 #define CAMDMA_CCR_RD_ACTIVE (1 << 9)
330 #define CAMDMA_CCR_SUSPEND_SENSITIVE (1 << 8)
331 #define CAMDMA_CCR_ENABLE (1 << 7)
332 #define CAMDMA_CCR_PRIO (1 << 6)
333 #define CAMDMA_CCR_FS (1 << 5)
334 #define CAMDMA_CCR_SYNCHRO ((3 << 19) | (31 << 0))
335 #define CAMDMA_CCR_SYNCHRO_CAMERA 0x01
336
337 #define CAMDMA_CLNK_CTRL_ENABLE_LNK (1 << 15)
338 #define CAMDMA_CLNK_CTRL_NEXTLCH_ID (0x1F << 0)
339 #define CAMDMA_CLNK_CTRL_NEXTLCH_ID_SHIFT 0
340
341 #define CAMDMA_CICR_MISALIGNED_ERR_IE (1 << 11)
342 #define CAMDMA_CICR_SUPERVISOR_ERR_IE (1 << 10)
343 #define CAMDMA_CICR_SECURE_ERR_IE (1 << 9)
344 #define CAMDMA_CICR_TRANS_ERR_IE (1 << 8)
345 #define CAMDMA_CICR_PACKET_IE (1 << 7)
346 #define CAMDMA_CICR_BLOCK_IE (1 << 5)
347 #define CAMDMA_CICR_LAST_IE (1 << 4)
348 #define CAMDMA_CICR_FRAME_IE (1 << 3)
349 #define CAMDMA_CICR_HALF_IE (1 << 2)
350 #define CAMDMA_CICR_DROP_IE (1 << 1)
351
352 #define CAMDMA_CSR_MISALIGNED_ERR (1 << 11)
353 #define CAMDMA_CSR_SUPERVISOR_ERR (1 << 10)
354 #define CAMDMA_CSR_SECURE_ERR (1 << 9)
355 #define CAMDMA_CSR_TRANS_ERR (1 << 8)
356 #define CAMDMA_CSR_PACKET (1 << 7)
357 #define CAMDMA_CSR_SYNC (1 << 6)
358 #define CAMDMA_CSR_BLOCK (1 << 5)
359 #define CAMDMA_CSR_LAST (1 << 4)
360 #define CAMDMA_CSR_FRAME (1 << 3)
361 #define CAMDMA_CSR_HALF (1 << 2)
362 #define CAMDMA_CSR_DROP (1 << 1)
363
364 #define CAMDMA_CSDP_SRC_ENDIANNESS (1 << 21)
365 #define CAMDMA_CSDP_SRC_ENDIANNESS_LOCK (1 << 20)
366 #define CAMDMA_CSDP_DST_ENDIANNESS (1 << 19)
367 #define CAMDMA_CSDP_DST_ENDIANNESS_LOCK (1 << 18)
368 #define CAMDMA_CSDP_WRITE_MODE (3 << 16)
369 #define CAMDMA_CSDP_WRITE_MODE_WRNP (0 << 16)
370 #define CAMDMA_CSDP_WRITE_MODE_POSTED (1 << 16)
371 #define CAMDMA_CSDP_WRITE_MODE_POSTED_LAST_WRNP (2 << 16)
372 #define CAMDMA_CSDP_DST_BURST_EN (3 << 14)
373 #define CAMDMA_CSDP_DST_BURST_EN_1 (0 << 14)
374 #define CAMDMA_CSDP_DST_BURST_EN_16 (1 << 14)
375 #define CAMDMA_CSDP_DST_BURST_EN_32 (2 << 14)
376 #define CAMDMA_CSDP_DST_BURST_EN_64 (3 << 14)
377 #define CAMDMA_CSDP_DST_PACKED (1 << 13)
378 #define CAMDMA_CSDP_WR_ADD_TRSLT (15 << 9)
379 #define CAMDMA_CSDP_WR_ADD_TRSLT_ENABLE_MREQADD (3 << 9)
380 #define CAMDMA_CSDP_SRC_BURST_EN (3 << 7)
381 #define CAMDMA_CSDP_SRC_BURST_EN_1 (0 << 7)
382 #define CAMDMA_CSDP_SRC_BURST_EN_16 (1 << 7)
383 #define CAMDMA_CSDP_SRC_BURST_EN_32 (2 << 7)
384 #define CAMDMA_CSDP_SRC_BURST_EN_64 (3 << 7)
385 #define CAMDMA_CSDP_SRC_PACKED (1 << 6)
386 #define CAMDMA_CSDP_RD_ADD_TRSLT (15 << 2)
387 #define CAMDMA_CSDP_RD_ADD_TRSLT_ENABLE_MREQADD (3 << 2)
388 #define CAMDMA_CSDP_DATA_TYPE (3 << 0)
389 #define CAMDMA_CSDP_DATA_TYPE_8BITS (0 << 0)
390 #define CAMDMA_CSDP_DATA_TYPE_16BITS (1 << 0)
391 #define CAMDMA_CSDP_DATA_TYPE_32BITS (2 << 0)
392
393 #define CAMMMU_SYSCONFIG_AUTOIDLE (1 << 0)
394
395 /*
396 *
397 * Declarations.
398 *
399 */
400
401 /* forward declarations */
402 struct omap24xxcam_sgdma;
403 struct omap24xxcam_dma;
404
405 typedef void (*sgdma_callback_t)(struct omap24xxcam_sgdma *cam,
406 u32 status, void *arg);
407 typedef void (*dma_callback_t)(struct omap24xxcam_dma *cam,
408 u32 status, void *arg);
409
410 struct channel_state {
411 dma_callback_t callback;
412 void *arg;
413 };
414
415 /* sgdma state for each of the possible videobuf_buffers + 2 overlays */
416 struct sgdma_state {
417 const struct scatterlist *sglist;
418 int sglen; /* number of sglist entries */
419 int next_sglist; /* index of next sglist entry to process */
420 unsigned int bytes_read; /* number of bytes read */
421 unsigned int len; /* total length of sglist (excluding
422 * bytes due to page alignment) */
423 int queued_sglist; /* number of sglist entries queued for DMA */
424 u32 csr; /* DMA return code */
425 sgdma_callback_t callback;
426 void *arg;
427 };
428
429 /* physical DMA channel management */
430 struct omap24xxcam_dma {
431 spinlock_t lock; /* Lock for the whole structure. */
432
433 void __iomem *base; /* base address for dma controller */
434
435 /* While dma_stop!=0, an attempt to start a new DMA transfer will
436 * fail.
437 */
438 atomic_t dma_stop;
439 int free_dmach; /* number of dma channels free */
440 int next_dmach; /* index of next dma channel to use */
441 struct channel_state ch_state[NUM_CAMDMA_CHANNELS];
442 };
443
444 /* scatter-gather DMA (scatterlist stuff) management */
445 struct omap24xxcam_sgdma {
446 struct omap24xxcam_dma dma;
447
448 spinlock_t lock; /* Lock for the fields below. */
449 int free_sgdma; /* number of free sg dma slots */
450 int next_sgdma; /* index of next sg dma slot to use */
451 struct sgdma_state sg_state[NUM_SG_DMA];
452
453 /* Reset timer data */
454 struct timer_list reset_timer;
455 };
456
457 /* per-device data structure */
458 struct omap24xxcam_device {
459 /*** mutex ***/
460 /*
461 * mutex serialises access to this structure. Also camera
462 * opening and releasing is synchronised by this.
463 */
464 struct mutex mutex;
465
466 struct v4l2_device v4l2_dev;
467
468 /*** general driver state information ***/
469 atomic_t users;
470 /*
471 * Lock to serialise core enabling and disabling and access to
472 * sgdma_in_queue.
473 */
474 spinlock_t core_enable_disable_lock;
475 /*
476 * Number or sgdma requests in scatter-gather queue, protected
477 * by the lock above.
478 */
479 int sgdma_in_queue;
480 /*
481 * Sensor interface parameters: interface type, CC_CTRL
482 * register value and interface specific data.
483 */
484 int if_type;
485 union {
486 struct parallel {
487 u32 xclk;
488 } bt656;
489 } if_u;
490 u32 cc_ctrl;
491
492 /*** subsystem structures ***/
493 struct omap24xxcam_sgdma sgdma;
494
495 /*** hardware resources ***/
496 unsigned int irq;
497 void __iomem *mmio_base;
498 unsigned long mmio_base_phys;
499 unsigned long mmio_size;
500
501 /*** interfaces and device ***/
502 struct v4l2_int_device *sdev;
503 struct device *dev;
504 struct video_device *vfd;
505
506 /*** camera and sensor reset related stuff ***/
507 struct work_struct sensor_reset_work;
508 /*
509 * We're in the middle of a reset. Don't enable core if this
510 * is non-zero! This exists to help decisionmaking in a case
511 * where videobuf_qbuf is called while we are in the middle of
512 * a reset.
513 */
514 atomic_t in_reset;
515 /*
516 * Non-zero if we don't want any resets for now. Used to
517 * prevent reset work to run when we're about to stop
518 * streaming.
519 */
520 atomic_t reset_disable;
521
522 /*** video device parameters ***/
523 int capture_mem;
524
525 /*** camera module clocks ***/
526 struct clk *fck;
527 struct clk *ick;
528
529 /*** capture data ***/
530 /* file handle, if streaming is on */
531 struct file *streaming;
532 };
533
534 /* Per-file handle data. */
535 struct omap24xxcam_fh {
536 spinlock_t vbq_lock; /* spinlock for the videobuf queue */
537 struct videobuf_queue vbq;
538 struct v4l2_pix_format pix; /* serialise pix by vbq->lock */
539 atomic_t field_count; /* field counter for videobuf_buffer */
540 /* accessing cam here doesn't need serialisation: it's constant */
541 struct omap24xxcam_device *cam;
542 };
543
544 /*
545 *
546 * Register I/O functions.
547 *
548 */
549
omap24xxcam_reg_in(u32 __iomem * base,u32 offset)550 static inline u32 omap24xxcam_reg_in(u32 __iomem *base, u32 offset)
551 {
552 return readl(base + offset);
553 }
554
omap24xxcam_reg_out(u32 __iomem * base,u32 offset,u32 val)555 static inline u32 omap24xxcam_reg_out(u32 __iomem *base, u32 offset,
556 u32 val)
557 {
558 writel(val, base + offset);
559 return val;
560 }
561
omap24xxcam_reg_merge(u32 __iomem * base,u32 offset,u32 val,u32 mask)562 static inline u32 omap24xxcam_reg_merge(u32 __iomem *base, u32 offset,
563 u32 val, u32 mask)
564 {
565 u32 __iomem *addr = base + offset;
566 u32 new_val = (readl(addr) & ~mask) | (val & mask);
567
568 writel(new_val, addr);
569 return new_val;
570 }
571
572 /*
573 *
574 * Function prototypes.
575 *
576 */
577
578 /* dma prototypes */
579
580 void omap24xxcam_dma_hwinit(struct omap24xxcam_dma *dma);
581 void omap24xxcam_dma_isr(struct omap24xxcam_dma *dma);
582
583 /* sgdma prototypes */
584
585 void omap24xxcam_sgdma_process(struct omap24xxcam_sgdma *sgdma);
586 int omap24xxcam_sgdma_queue(struct omap24xxcam_sgdma *sgdma,
587 const struct scatterlist *sglist, int sglen,
588 int len, sgdma_callback_t callback, void *arg);
589 void omap24xxcam_sgdma_sync(struct omap24xxcam_sgdma *sgdma);
590 void omap24xxcam_sgdma_init(struct omap24xxcam_sgdma *sgdma,
591 void __iomem *base,
592 void (*reset_callback)(unsigned long data),
593 unsigned long reset_callback_data);
594 void omap24xxcam_sgdma_exit(struct omap24xxcam_sgdma *sgdma);
595
596 #endif
597