1 /*
2 * Synopsys DesignWare 8250 driver.
3 *
4 * Copyright 2011 Picochip, Jamie Iles.
5 * Copyright 2013 Intel Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
13 * LCR is written whilst busy. If it is, then a busy detect interrupt is
14 * raised, the LCR needs to be rewritten and the uart status register read.
15 */
16 #include <linux/device.h>
17 #include <linux/io.h>
18 #include <linux/module.h>
19 #include <linux/serial_8250.h>
20 #include <linux/serial_core.h>
21 #include <linux/serial_reg.h>
22 #include <linux/of.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_platform.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include <linux/acpi.h>
28 #include <linux/clk.h>
29 #include <linux/reset.h>
30 #include <linux/pm_runtime.h>
31
32 #include <asm/byteorder.h>
33
34 #include "8250.h"
35
36 /* Offsets for the DesignWare specific registers */
37 #define DW_UART_USR 0x1f /* UART Status Register */
38 #define DW_UART_CPR 0xf4 /* Component Parameter Register */
39 #define DW_UART_UCV 0xf8 /* UART Component Version */
40
41 /* Component Parameter Register bits */
42 #define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0)
43 #define DW_UART_CPR_AFCE_MODE (1 << 4)
44 #define DW_UART_CPR_THRE_MODE (1 << 5)
45 #define DW_UART_CPR_SIR_MODE (1 << 6)
46 #define DW_UART_CPR_SIR_LP_MODE (1 << 7)
47 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
48 #define DW_UART_CPR_FIFO_ACCESS (1 << 9)
49 #define DW_UART_CPR_FIFO_STAT (1 << 10)
50 #define DW_UART_CPR_SHADOW (1 << 11)
51 #define DW_UART_CPR_ENCODED_PARMS (1 << 12)
52 #define DW_UART_CPR_DMA_EXTRA (1 << 13)
53 #define DW_UART_CPR_FIFO_MODE (0xff << 16)
54 /* Helper for fifo size calculation */
55 #define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16)
56
57
58 struct dw8250_data {
59 u8 usr_reg;
60 int last_mcr;
61 int line;
62 struct clk *clk;
63 struct clk *pclk;
64 struct reset_control *rst;
65 struct uart_8250_dma dma;
66 };
67
68 #define BYT_PRV_CLK 0x800
69 #define BYT_PRV_CLK_EN (1 << 0)
70 #define BYT_PRV_CLK_M_VAL_SHIFT 1
71 #define BYT_PRV_CLK_N_VAL_SHIFT 16
72 #define BYT_PRV_CLK_UPDATE (1 << 31)
73
dw8250_modify_msr(struct uart_port * p,int offset,int value)74 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
75 {
76 struct dw8250_data *d = p->private_data;
77
78 /* If reading MSR, report CTS asserted when auto-CTS/RTS enabled */
79 if (offset == UART_MSR && d->last_mcr & UART_MCR_AFE) {
80 value |= UART_MSR_CTS;
81 value &= ~UART_MSR_DCTS;
82 }
83
84 return value;
85 }
86
dw8250_force_idle(struct uart_port * p)87 static void dw8250_force_idle(struct uart_port *p)
88 {
89 struct uart_8250_port *up = up_to_u8250p(p);
90
91 serial8250_clear_and_reinit_fifos(up);
92 (void)p->serial_in(p, UART_RX);
93 }
94
dw8250_serial_out(struct uart_port * p,int offset,int value)95 static void dw8250_serial_out(struct uart_port *p, int offset, int value)
96 {
97 struct dw8250_data *d = p->private_data;
98
99 if (offset == UART_MCR)
100 d->last_mcr = value;
101
102 writeb(value, p->membase + (offset << p->regshift));
103
104 /* Make sure LCR write wasn't ignored */
105 if (offset == UART_LCR) {
106 int tries = 1000;
107 while (tries--) {
108 unsigned int lcr = p->serial_in(p, UART_LCR);
109 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
110 return;
111 dw8250_force_idle(p);
112 writeb(value, p->membase + (UART_LCR << p->regshift));
113 }
114 /*
115 * FIXME: this deadlocks if port->lock is already held
116 * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
117 */
118 }
119 }
120
dw8250_serial_in(struct uart_port * p,int offset)121 static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
122 {
123 unsigned int value = readb(p->membase + (offset << p->regshift));
124
125 return dw8250_modify_msr(p, offset, value);
126 }
127
128 /* Read Back (rb) version to ensure register access ording. */
dw8250_serial_out_rb(struct uart_port * p,int offset,int value)129 static void dw8250_serial_out_rb(struct uart_port *p, int offset, int value)
130 {
131 dw8250_serial_out(p, offset, value);
132 dw8250_serial_in(p, UART_LCR);
133 }
134
dw8250_serial_out32(struct uart_port * p,int offset,int value)135 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
136 {
137 struct dw8250_data *d = p->private_data;
138
139 if (offset == UART_MCR)
140 d->last_mcr = value;
141
142 writel(value, p->membase + (offset << p->regshift));
143
144 /* Make sure LCR write wasn't ignored */
145 if (offset == UART_LCR) {
146 int tries = 1000;
147 while (tries--) {
148 unsigned int lcr = p->serial_in(p, UART_LCR);
149 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
150 return;
151 dw8250_force_idle(p);
152 writel(value, p->membase + (UART_LCR << p->regshift));
153 }
154 /*
155 * FIXME: this deadlocks if port->lock is already held
156 * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
157 */
158 }
159 }
160
dw8250_serial_in32(struct uart_port * p,int offset)161 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
162 {
163 unsigned int value = readl(p->membase + (offset << p->regshift));
164
165 return dw8250_modify_msr(p, offset, value);
166 }
167
dw8250_handle_irq(struct uart_port * p)168 static int dw8250_handle_irq(struct uart_port *p)
169 {
170 struct dw8250_data *d = p->private_data;
171 unsigned int iir = p->serial_in(p, UART_IIR);
172
173 if (serial8250_handle_irq(p, iir)) {
174 return 1;
175 } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
176 /* Clear the USR */
177 (void)p->serial_in(p, d->usr_reg);
178
179 return 1;
180 }
181
182 return 0;
183 }
184
185 static void
dw8250_do_pm(struct uart_port * port,unsigned int state,unsigned int old)186 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
187 {
188 if (!state)
189 pm_runtime_get_sync(port->dev);
190
191 serial8250_do_pm(port, state, old);
192
193 if (state)
194 pm_runtime_put_sync_suspend(port->dev);
195 }
196
dw8250_set_termios(struct uart_port * p,struct ktermios * termios,struct ktermios * old)197 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
198 struct ktermios *old)
199 {
200 unsigned int baud = tty_termios_baud_rate(termios);
201 struct dw8250_data *d = p->private_data;
202 unsigned int rate;
203 int ret;
204
205 if (IS_ERR(d->clk) || !old)
206 goto out;
207
208 /* Not requesting clock rates below 1.8432Mhz */
209 if (baud < 115200)
210 baud = 115200;
211
212 clk_disable_unprepare(d->clk);
213 rate = clk_round_rate(d->clk, baud * 16);
214 ret = clk_set_rate(d->clk, rate);
215 clk_prepare_enable(d->clk);
216
217 if (!ret)
218 p->uartclk = rate;
219 out:
220 serial8250_do_set_termios(p, termios, old);
221 }
222
dw8250_dma_filter(struct dma_chan * chan,void * param)223 static bool dw8250_dma_filter(struct dma_chan *chan, void *param)
224 {
225 return false;
226 }
227
dw8250_setup_port(struct uart_8250_port * up)228 static void dw8250_setup_port(struct uart_8250_port *up)
229 {
230 struct uart_port *p = &up->port;
231 u32 reg = readl(p->membase + DW_UART_UCV);
232
233 /*
234 * If the Component Version Register returns zero, we know that
235 * ADDITIONAL_FEATURES are not enabled. No need to go any further.
236 */
237 if (!reg)
238 return;
239
240 dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
241 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
242
243 reg = readl(p->membase + DW_UART_CPR);
244 if (!reg)
245 return;
246
247 /* Select the type based on fifo */
248 if (reg & DW_UART_CPR_FIFO_MODE) {
249 p->type = PORT_16550A;
250 p->flags |= UPF_FIXED_TYPE;
251 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
252 up->tx_loadsz = p->fifosize;
253 up->capabilities = UART_CAP_FIFO;
254 }
255
256 if (reg & DW_UART_CPR_AFCE_MODE)
257 up->capabilities |= UART_CAP_AFE;
258 }
259
dw8250_probe_of(struct uart_port * p,struct dw8250_data * data)260 static int dw8250_probe_of(struct uart_port *p,
261 struct dw8250_data *data)
262 {
263 struct device_node *np = p->dev->of_node;
264 struct uart_8250_port *up = up_to_u8250p(p);
265 u32 val;
266 bool has_ucv = true;
267
268 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
269 #ifdef __BIG_ENDIAN
270 /*
271 * Low order bits of these 64-bit registers, when
272 * accessed as a byte, are 7 bytes further down in the
273 * address space in big endian mode.
274 */
275 p->membase += 7;
276 #endif
277 p->serial_out = dw8250_serial_out_rb;
278 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
279 p->type = PORT_OCTEON;
280 data->usr_reg = 0x27;
281 has_ucv = false;
282 } else if (!of_property_read_u32(np, "reg-io-width", &val)) {
283 switch (val) {
284 case 1:
285 break;
286 case 4:
287 p->iotype = UPIO_MEM32;
288 p->serial_in = dw8250_serial_in32;
289 p->serial_out = dw8250_serial_out32;
290 break;
291 default:
292 dev_err(p->dev, "unsupported reg-io-width (%u)\n", val);
293 return -EINVAL;
294 }
295 }
296 if (has_ucv)
297 dw8250_setup_port(up);
298
299 if (!of_property_read_u32(np, "reg-shift", &val))
300 p->regshift = val;
301
302 /* clock got configured through clk api, all done */
303 if (p->uartclk)
304 return 0;
305
306 /* try to find out clock frequency from DT as fallback */
307 if (of_property_read_u32(np, "clock-frequency", &val)) {
308 dev_err(p->dev, "clk or clock-frequency not defined\n");
309 return -EINVAL;
310 }
311 p->uartclk = val;
312
313 return 0;
314 }
315
dw8250_probe_acpi(struct uart_8250_port * up,struct dw8250_data * data)316 static int dw8250_probe_acpi(struct uart_8250_port *up,
317 struct dw8250_data *data)
318 {
319 const struct acpi_device_id *id;
320 struct uart_port *p = &up->port;
321
322 dw8250_setup_port(up);
323
324 id = acpi_match_device(p->dev->driver->acpi_match_table, p->dev);
325 if (!id)
326 return -ENODEV;
327
328 if (!p->uartclk)
329 if (device_property_read_u32(p->dev, "clock-frequency",
330 &p->uartclk))
331 return -EINVAL;
332
333 p->iotype = UPIO_MEM32;
334 p->serial_in = dw8250_serial_in32;
335 p->serial_out = dw8250_serial_out32;
336 p->regshift = 2;
337
338 up->dma = &data->dma;
339
340 up->dma->rxconf.src_maxburst = p->fifosize / 4;
341 up->dma->txconf.dst_maxburst = p->fifosize / 4;
342
343 up->port.set_termios = dw8250_set_termios;
344
345 return 0;
346 }
347
dw8250_probe(struct platform_device * pdev)348 static int dw8250_probe(struct platform_device *pdev)
349 {
350 struct uart_8250_port uart = {};
351 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
352 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
353 struct dw8250_data *data;
354 int err;
355
356 if (!regs || !irq) {
357 dev_err(&pdev->dev, "no registers/irq defined\n");
358 return -EINVAL;
359 }
360
361 spin_lock_init(&uart.port.lock);
362 uart.port.mapbase = regs->start;
363 uart.port.irq = irq->start;
364 uart.port.handle_irq = dw8250_handle_irq;
365 uart.port.pm = dw8250_do_pm;
366 uart.port.type = PORT_8250;
367 uart.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
368 uart.port.dev = &pdev->dev;
369
370 uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
371 resource_size(regs));
372 if (!uart.port.membase)
373 return -ENOMEM;
374
375 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
376 if (!data)
377 return -ENOMEM;
378
379 data->usr_reg = DW_UART_USR;
380 data->clk = devm_clk_get(&pdev->dev, "baudclk");
381 if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER)
382 data->clk = devm_clk_get(&pdev->dev, NULL);
383 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER)
384 return -EPROBE_DEFER;
385 if (!IS_ERR(data->clk)) {
386 err = clk_prepare_enable(data->clk);
387 if (err)
388 dev_warn(&pdev->dev, "could not enable optional baudclk: %d\n",
389 err);
390 else
391 uart.port.uartclk = clk_get_rate(data->clk);
392 }
393
394 data->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
395 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) {
396 err = -EPROBE_DEFER;
397 goto err_clk;
398 }
399 if (!IS_ERR(data->pclk)) {
400 err = clk_prepare_enable(data->pclk);
401 if (err) {
402 dev_err(&pdev->dev, "could not enable apb_pclk\n");
403 goto err_clk;
404 }
405 }
406
407 data->rst = devm_reset_control_get_optional(&pdev->dev, NULL);
408 if (IS_ERR(data->rst) && PTR_ERR(data->rst) == -EPROBE_DEFER) {
409 err = -EPROBE_DEFER;
410 goto err_pclk;
411 }
412 if (!IS_ERR(data->rst))
413 reset_control_deassert(data->rst);
414
415 data->dma.rx_param = data;
416 data->dma.tx_param = data;
417 data->dma.fn = dw8250_dma_filter;
418
419 uart.port.iotype = UPIO_MEM;
420 uart.port.serial_in = dw8250_serial_in;
421 uart.port.serial_out = dw8250_serial_out;
422 uart.port.private_data = data;
423
424 if (pdev->dev.of_node) {
425 err = dw8250_probe_of(&uart.port, data);
426 if (err)
427 goto err_reset;
428 } else if (ACPI_HANDLE(&pdev->dev)) {
429 err = dw8250_probe_acpi(&uart, data);
430 if (err)
431 goto err_reset;
432 } else {
433 err = -ENODEV;
434 goto err_reset;
435 }
436
437 data->line = serial8250_register_8250_port(&uart);
438 if (data->line < 0) {
439 err = data->line;
440 goto err_reset;
441 }
442
443 platform_set_drvdata(pdev, data);
444
445 pm_runtime_set_active(&pdev->dev);
446 pm_runtime_enable(&pdev->dev);
447
448 return 0;
449
450 err_reset:
451 if (!IS_ERR(data->rst))
452 reset_control_assert(data->rst);
453
454 err_pclk:
455 if (!IS_ERR(data->pclk))
456 clk_disable_unprepare(data->pclk);
457
458 err_clk:
459 if (!IS_ERR(data->clk))
460 clk_disable_unprepare(data->clk);
461
462 return err;
463 }
464
dw8250_remove(struct platform_device * pdev)465 static int dw8250_remove(struct platform_device *pdev)
466 {
467 struct dw8250_data *data = platform_get_drvdata(pdev);
468
469 pm_runtime_get_sync(&pdev->dev);
470
471 serial8250_unregister_port(data->line);
472
473 if (!IS_ERR(data->rst))
474 reset_control_assert(data->rst);
475
476 if (!IS_ERR(data->pclk))
477 clk_disable_unprepare(data->pclk);
478
479 if (!IS_ERR(data->clk))
480 clk_disable_unprepare(data->clk);
481
482 pm_runtime_disable(&pdev->dev);
483 pm_runtime_put_noidle(&pdev->dev);
484
485 return 0;
486 }
487
488 #ifdef CONFIG_PM_SLEEP
dw8250_suspend(struct device * dev)489 static int dw8250_suspend(struct device *dev)
490 {
491 struct dw8250_data *data = dev_get_drvdata(dev);
492
493 serial8250_suspend_port(data->line);
494
495 return 0;
496 }
497
dw8250_resume(struct device * dev)498 static int dw8250_resume(struct device *dev)
499 {
500 struct dw8250_data *data = dev_get_drvdata(dev);
501
502 serial8250_resume_port(data->line);
503
504 return 0;
505 }
506 #endif /* CONFIG_PM_SLEEP */
507
508 #ifdef CONFIG_PM_RUNTIME
dw8250_runtime_suspend(struct device * dev)509 static int dw8250_runtime_suspend(struct device *dev)
510 {
511 struct dw8250_data *data = dev_get_drvdata(dev);
512
513 if (!IS_ERR(data->clk))
514 clk_disable_unprepare(data->clk);
515
516 if (!IS_ERR(data->pclk))
517 clk_disable_unprepare(data->pclk);
518
519 return 0;
520 }
521
dw8250_runtime_resume(struct device * dev)522 static int dw8250_runtime_resume(struct device *dev)
523 {
524 struct dw8250_data *data = dev_get_drvdata(dev);
525
526 if (!IS_ERR(data->pclk))
527 clk_prepare_enable(data->pclk);
528
529 if (!IS_ERR(data->clk))
530 clk_prepare_enable(data->clk);
531
532 return 0;
533 }
534 #endif
535
536 static const struct dev_pm_ops dw8250_pm_ops = {
537 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
538 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
539 };
540
541 static const struct of_device_id dw8250_of_match[] = {
542 { .compatible = "snps,dw-apb-uart" },
543 { .compatible = "cavium,octeon-3860-uart" },
544 { /* Sentinel */ }
545 };
546 MODULE_DEVICE_TABLE(of, dw8250_of_match);
547
548 static const struct acpi_device_id dw8250_acpi_match[] = {
549 { "INT33C4", 0 },
550 { "INT33C5", 0 },
551 { "INT3434", 0 },
552 { "INT3435", 0 },
553 { "80860F0A", 0 },
554 { "8086228A", 0 },
555 { "APMC0D08", 0},
556 { "AMD0020", 0 },
557 { },
558 };
559 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
560
561 static struct platform_driver dw8250_platform_driver = {
562 .driver = {
563 .name = "dw-apb-uart",
564 .owner = THIS_MODULE,
565 .pm = &dw8250_pm_ops,
566 .of_match_table = dw8250_of_match,
567 .acpi_match_table = ACPI_PTR(dw8250_acpi_match),
568 },
569 .probe = dw8250_probe,
570 .remove = dw8250_remove,
571 };
572
573 module_platform_driver(dw8250_platform_driver);
574
575 MODULE_AUTHOR("Jamie Iles");
576 MODULE_LICENSE("GPL");
577 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
578