1 #if defined(CONFIG_SERIAL_EFM32_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
2 #define SUPPORT_SYSRQ
3 #endif
4
5 #include <linux/kernel.h>
6 #include <linux/module.h>
7 #include <linux/io.h>
8 #include <linux/platform_device.h>
9 #include <linux/console.h>
10 #include <linux/sysrq.h>
11 #include <linux/serial_core.h>
12 #include <linux/tty_flip.h>
13 #include <linux/slab.h>
14 #include <linux/clk.h>
15 #include <linux/of.h>
16 #include <linux/of_device.h>
17
18 #include <linux/platform_data/efm32-uart.h>
19
20 #define DRIVER_NAME "efm32-uart"
21 #define DEV_NAME "ttyefm"
22
23 #define UARTn_CTRL 0x00
24 #define UARTn_CTRL_SYNC 0x0001
25 #define UARTn_CTRL_TXBIL 0x1000
26
27 #define UARTn_FRAME 0x04
28 #define UARTn_FRAME_DATABITS__MASK 0x000f
29 #define UARTn_FRAME_DATABITS(n) ((n) - 3)
30 #define UARTn_FRAME_PARITY__MASK 0x0300
31 #define UARTn_FRAME_PARITY_NONE 0x0000
32 #define UARTn_FRAME_PARITY_EVEN 0x0200
33 #define UARTn_FRAME_PARITY_ODD 0x0300
34 #define UARTn_FRAME_STOPBITS_HALF 0x0000
35 #define UARTn_FRAME_STOPBITS_ONE 0x1000
36 #define UARTn_FRAME_STOPBITS_TWO 0x3000
37
38 #define UARTn_CMD 0x0c
39 #define UARTn_CMD_RXEN 0x0001
40 #define UARTn_CMD_RXDIS 0x0002
41 #define UARTn_CMD_TXEN 0x0004
42 #define UARTn_CMD_TXDIS 0x0008
43
44 #define UARTn_STATUS 0x10
45 #define UARTn_STATUS_TXENS 0x0002
46 #define UARTn_STATUS_TXC 0x0020
47 #define UARTn_STATUS_TXBL 0x0040
48 #define UARTn_STATUS_RXDATAV 0x0080
49
50 #define UARTn_CLKDIV 0x14
51
52 #define UARTn_RXDATAX 0x18
53 #define UARTn_RXDATAX_RXDATA__MASK 0x01ff
54 #define UARTn_RXDATAX_PERR 0x4000
55 #define UARTn_RXDATAX_FERR 0x8000
56 /*
57 * This is a software only flag used for ignore_status_mask and
58 * read_status_mask! It's used for breaks that the hardware doesn't report
59 * explicitly.
60 */
61 #define SW_UARTn_RXDATAX_BERR 0x2000
62
63 #define UARTn_TXDATA 0x34
64
65 #define UARTn_IF 0x40
66 #define UARTn_IF_TXC 0x0001
67 #define UARTn_IF_TXBL 0x0002
68 #define UARTn_IF_RXDATAV 0x0004
69 #define UARTn_IF_RXOF 0x0010
70
71 #define UARTn_IFS 0x44
72 #define UARTn_IFC 0x48
73 #define UARTn_IEN 0x4c
74
75 #define UARTn_ROUTE 0x54
76 #define UARTn_ROUTE_LOCATION__MASK 0x0700
77 #define UARTn_ROUTE_LOCATION(n) (((n) << 8) & UARTn_ROUTE_LOCATION__MASK)
78 #define UARTn_ROUTE_RXPEN 0x0001
79 #define UARTn_ROUTE_TXPEN 0x0002
80
81 struct efm32_uart_port {
82 struct uart_port port;
83 unsigned int txirq;
84 struct clk *clk;
85 struct efm32_uart_pdata pdata;
86 };
87 #define to_efm_port(_port) container_of(_port, struct efm32_uart_port, port)
88 #define efm_debug(efm_port, format, arg...) \
89 dev_dbg(efm_port->port.dev, format, ##arg)
90
efm32_uart_write32(struct efm32_uart_port * efm_port,u32 value,unsigned offset)91 static void efm32_uart_write32(struct efm32_uart_port *efm_port,
92 u32 value, unsigned offset)
93 {
94 writel_relaxed(value, efm_port->port.membase + offset);
95 }
96
efm32_uart_read32(struct efm32_uart_port * efm_port,unsigned offset)97 static u32 efm32_uart_read32(struct efm32_uart_port *efm_port,
98 unsigned offset)
99 {
100 return readl_relaxed(efm_port->port.membase + offset);
101 }
102
efm32_uart_tx_empty(struct uart_port * port)103 static unsigned int efm32_uart_tx_empty(struct uart_port *port)
104 {
105 struct efm32_uart_port *efm_port = to_efm_port(port);
106 u32 status = efm32_uart_read32(efm_port, UARTn_STATUS);
107
108 if (status & UARTn_STATUS_TXC)
109 return TIOCSER_TEMT;
110 else
111 return 0;
112 }
113
efm32_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)114 static void efm32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
115 {
116 /* sorry, neither handshaking lines nor loop functionallity */
117 }
118
efm32_uart_get_mctrl(struct uart_port * port)119 static unsigned int efm32_uart_get_mctrl(struct uart_port *port)
120 {
121 /* sorry, no handshaking lines available */
122 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR;
123 }
124
efm32_uart_stop_tx(struct uart_port * port)125 static void efm32_uart_stop_tx(struct uart_port *port)
126 {
127 struct efm32_uart_port *efm_port = to_efm_port(port);
128 u32 ien = efm32_uart_read32(efm_port, UARTn_IEN);
129
130 efm32_uart_write32(efm_port, UARTn_CMD_TXDIS, UARTn_CMD);
131 ien &= ~(UARTn_IF_TXC | UARTn_IF_TXBL);
132 efm32_uart_write32(efm_port, ien, UARTn_IEN);
133 }
134
efm32_uart_tx_chars(struct efm32_uart_port * efm_port)135 static void efm32_uart_tx_chars(struct efm32_uart_port *efm_port)
136 {
137 struct uart_port *port = &efm_port->port;
138 struct circ_buf *xmit = &port->state->xmit;
139
140 while (efm32_uart_read32(efm_port, UARTn_STATUS) &
141 UARTn_STATUS_TXBL) {
142 if (port->x_char) {
143 port->icount.tx++;
144 efm32_uart_write32(efm_port, port->x_char,
145 UARTn_TXDATA);
146 port->x_char = 0;
147 continue;
148 }
149 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
150 port->icount.tx++;
151 efm32_uart_write32(efm_port, xmit->buf[xmit->tail],
152 UARTn_TXDATA);
153 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
154 } else
155 break;
156 }
157
158 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
159 uart_write_wakeup(port);
160
161 if (!port->x_char && uart_circ_empty(xmit) &&
162 efm32_uart_read32(efm_port, UARTn_STATUS) &
163 UARTn_STATUS_TXC)
164 efm32_uart_stop_tx(port);
165 }
166
efm32_uart_start_tx(struct uart_port * port)167 static void efm32_uart_start_tx(struct uart_port *port)
168 {
169 struct efm32_uart_port *efm_port = to_efm_port(port);
170 u32 ien;
171
172 efm32_uart_write32(efm_port,
173 UARTn_IF_TXBL | UARTn_IF_TXC, UARTn_IFC);
174 ien = efm32_uart_read32(efm_port, UARTn_IEN);
175 efm32_uart_write32(efm_port,
176 ien | UARTn_IF_TXBL | UARTn_IF_TXC, UARTn_IEN);
177 efm32_uart_write32(efm_port, UARTn_CMD_TXEN, UARTn_CMD);
178
179 efm32_uart_tx_chars(efm_port);
180 }
181
efm32_uart_stop_rx(struct uart_port * port)182 static void efm32_uart_stop_rx(struct uart_port *port)
183 {
184 struct efm32_uart_port *efm_port = to_efm_port(port);
185
186 efm32_uart_write32(efm_port, UARTn_CMD_RXDIS, UARTn_CMD);
187 }
188
efm32_uart_break_ctl(struct uart_port * port,int ctl)189 static void efm32_uart_break_ctl(struct uart_port *port, int ctl)
190 {
191 /* not possible without fiddling with gpios */
192 }
193
efm32_uart_rx_chars(struct efm32_uart_port * efm_port)194 static void efm32_uart_rx_chars(struct efm32_uart_port *efm_port)
195 {
196 struct uart_port *port = &efm_port->port;
197
198 while (efm32_uart_read32(efm_port, UARTn_STATUS) &
199 UARTn_STATUS_RXDATAV) {
200 u32 rxdata = efm32_uart_read32(efm_port, UARTn_RXDATAX);
201 int flag = 0;
202
203 /*
204 * This is a reserved bit and I only saw it read as 0. But to be
205 * sure not to be confused too much by new devices adhere to the
206 * warning in the reference manual that reserverd bits might
207 * read as 1 in the future.
208 */
209 rxdata &= ~SW_UARTn_RXDATAX_BERR;
210
211 port->icount.rx++;
212
213 if ((rxdata & UARTn_RXDATAX_FERR) &&
214 !(rxdata & UARTn_RXDATAX_RXDATA__MASK)) {
215 rxdata |= SW_UARTn_RXDATAX_BERR;
216 port->icount.brk++;
217 if (uart_handle_break(port))
218 continue;
219 } else if (rxdata & UARTn_RXDATAX_PERR)
220 port->icount.parity++;
221 else if (rxdata & UARTn_RXDATAX_FERR)
222 port->icount.frame++;
223
224 rxdata &= port->read_status_mask;
225
226 if (rxdata & SW_UARTn_RXDATAX_BERR)
227 flag = TTY_BREAK;
228 else if (rxdata & UARTn_RXDATAX_PERR)
229 flag = TTY_PARITY;
230 else if (rxdata & UARTn_RXDATAX_FERR)
231 flag = TTY_FRAME;
232 else if (uart_handle_sysrq_char(port,
233 rxdata & UARTn_RXDATAX_RXDATA__MASK))
234 continue;
235
236 if ((rxdata & port->ignore_status_mask) == 0)
237 tty_insert_flip_char(&port->state->port,
238 rxdata & UARTn_RXDATAX_RXDATA__MASK, flag);
239 }
240 }
241
efm32_uart_rxirq(int irq,void * data)242 static irqreturn_t efm32_uart_rxirq(int irq, void *data)
243 {
244 struct efm32_uart_port *efm_port = data;
245 u32 irqflag = efm32_uart_read32(efm_port, UARTn_IF);
246 int handled = IRQ_NONE;
247 struct uart_port *port = &efm_port->port;
248 struct tty_port *tport = &port->state->port;
249
250 spin_lock(&port->lock);
251
252 if (irqflag & UARTn_IF_RXDATAV) {
253 efm32_uart_write32(efm_port, UARTn_IF_RXDATAV, UARTn_IFC);
254 efm32_uart_rx_chars(efm_port);
255
256 handled = IRQ_HANDLED;
257 }
258
259 if (irqflag & UARTn_IF_RXOF) {
260 efm32_uart_write32(efm_port, UARTn_IF_RXOF, UARTn_IFC);
261 port->icount.overrun++;
262 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
263
264 handled = IRQ_HANDLED;
265 }
266
267 spin_unlock(&port->lock);
268
269 tty_flip_buffer_push(tport);
270
271 return handled;
272 }
273
efm32_uart_txirq(int irq,void * data)274 static irqreturn_t efm32_uart_txirq(int irq, void *data)
275 {
276 struct efm32_uart_port *efm_port = data;
277 u32 irqflag = efm32_uart_read32(efm_port, UARTn_IF);
278
279 /* TXBL doesn't need to be cleared */
280 if (irqflag & UARTn_IF_TXC)
281 efm32_uart_write32(efm_port, UARTn_IF_TXC, UARTn_IFC);
282
283 if (irqflag & (UARTn_IF_TXC | UARTn_IF_TXBL)) {
284 efm32_uart_tx_chars(efm_port);
285 return IRQ_HANDLED;
286 } else
287 return IRQ_NONE;
288 }
289
efm32_uart_startup(struct uart_port * port)290 static int efm32_uart_startup(struct uart_port *port)
291 {
292 struct efm32_uart_port *efm_port = to_efm_port(port);
293 int ret;
294
295 ret = clk_enable(efm_port->clk);
296 if (ret) {
297 efm_debug(efm_port, "failed to enable clk\n");
298 goto err_clk_enable;
299 }
300 port->uartclk = clk_get_rate(efm_port->clk);
301
302 /* Enable pins at configured location */
303 efm32_uart_write32(efm_port,
304 UARTn_ROUTE_LOCATION(efm_port->pdata.location) |
305 UARTn_ROUTE_RXPEN | UARTn_ROUTE_TXPEN,
306 UARTn_ROUTE);
307
308 ret = request_irq(port->irq, efm32_uart_rxirq, 0,
309 DRIVER_NAME, efm_port);
310 if (ret) {
311 efm_debug(efm_port, "failed to register rxirq\n");
312 goto err_request_irq_rx;
313 }
314
315 /* disable all irqs */
316 efm32_uart_write32(efm_port, 0, UARTn_IEN);
317
318 ret = request_irq(efm_port->txirq, efm32_uart_txirq, 0,
319 DRIVER_NAME, efm_port);
320 if (ret) {
321 efm_debug(efm_port, "failed to register txirq\n");
322 free_irq(port->irq, efm_port);
323 err_request_irq_rx:
324
325 clk_disable(efm_port->clk);
326 } else {
327 efm32_uart_write32(efm_port,
328 UARTn_IF_RXDATAV | UARTn_IF_RXOF, UARTn_IEN);
329 efm32_uart_write32(efm_port, UARTn_CMD_RXEN, UARTn_CMD);
330 }
331
332 err_clk_enable:
333 return ret;
334 }
335
efm32_uart_shutdown(struct uart_port * port)336 static void efm32_uart_shutdown(struct uart_port *port)
337 {
338 struct efm32_uart_port *efm_port = to_efm_port(port);
339
340 efm32_uart_write32(efm_port, 0, UARTn_IEN);
341 free_irq(port->irq, efm_port);
342
343 clk_disable(efm_port->clk);
344 }
345
efm32_uart_set_termios(struct uart_port * port,struct ktermios * new,struct ktermios * old)346 static void efm32_uart_set_termios(struct uart_port *port,
347 struct ktermios *new, struct ktermios *old)
348 {
349 struct efm32_uart_port *efm_port = to_efm_port(port);
350 unsigned long flags;
351 unsigned baud;
352 u32 clkdiv;
353 u32 frame = 0;
354
355 /* no modem control lines */
356 new->c_cflag &= ~(CRTSCTS | CMSPAR);
357
358 baud = uart_get_baud_rate(port, new, old,
359 DIV_ROUND_CLOSEST(port->uartclk, 16 * 8192),
360 DIV_ROUND_CLOSEST(port->uartclk, 16));
361
362 switch (new->c_cflag & CSIZE) {
363 case CS5:
364 frame |= UARTn_FRAME_DATABITS(5);
365 break;
366 case CS6:
367 frame |= UARTn_FRAME_DATABITS(6);
368 break;
369 case CS7:
370 frame |= UARTn_FRAME_DATABITS(7);
371 break;
372 case CS8:
373 frame |= UARTn_FRAME_DATABITS(8);
374 break;
375 }
376
377 if (new->c_cflag & CSTOPB)
378 /* the receiver only verifies the first stop bit */
379 frame |= UARTn_FRAME_STOPBITS_TWO;
380 else
381 frame |= UARTn_FRAME_STOPBITS_ONE;
382
383 if (new->c_cflag & PARENB) {
384 if (new->c_cflag & PARODD)
385 frame |= UARTn_FRAME_PARITY_ODD;
386 else
387 frame |= UARTn_FRAME_PARITY_EVEN;
388 } else
389 frame |= UARTn_FRAME_PARITY_NONE;
390
391 /*
392 * the 6 lowest bits of CLKDIV are dc, bit 6 has value 0.25.
393 * port->uartclk <= 14e6, so 4 * port->uartclk doesn't overflow.
394 */
395 clkdiv = (DIV_ROUND_CLOSEST(4 * port->uartclk, 16 * baud) - 4) << 6;
396
397 spin_lock_irqsave(&port->lock, flags);
398
399 efm32_uart_write32(efm_port,
400 UARTn_CMD_TXDIS | UARTn_CMD_RXDIS, UARTn_CMD);
401
402 port->read_status_mask = UARTn_RXDATAX_RXDATA__MASK;
403 if (new->c_iflag & INPCK)
404 port->read_status_mask |=
405 UARTn_RXDATAX_FERR | UARTn_RXDATAX_PERR;
406 if (new->c_iflag & (IGNBRK | BRKINT | PARMRK))
407 port->read_status_mask |= SW_UARTn_RXDATAX_BERR;
408
409 port->ignore_status_mask = 0;
410 if (new->c_iflag & IGNPAR)
411 port->ignore_status_mask |=
412 UARTn_RXDATAX_FERR | UARTn_RXDATAX_PERR;
413 if (new->c_iflag & IGNBRK)
414 port->ignore_status_mask |= SW_UARTn_RXDATAX_BERR;
415
416 uart_update_timeout(port, new->c_cflag, baud);
417
418 efm32_uart_write32(efm_port, UARTn_CTRL_TXBIL, UARTn_CTRL);
419 efm32_uart_write32(efm_port, frame, UARTn_FRAME);
420 efm32_uart_write32(efm_port, clkdiv, UARTn_CLKDIV);
421
422 efm32_uart_write32(efm_port, UARTn_CMD_TXEN | UARTn_CMD_RXEN,
423 UARTn_CMD);
424
425 spin_unlock_irqrestore(&port->lock, flags);
426 }
427
efm32_uart_type(struct uart_port * port)428 static const char *efm32_uart_type(struct uart_port *port)
429 {
430 return port->type == PORT_EFMUART ? "efm32-uart" : NULL;
431 }
432
efm32_uart_release_port(struct uart_port * port)433 static void efm32_uart_release_port(struct uart_port *port)
434 {
435 struct efm32_uart_port *efm_port = to_efm_port(port);
436
437 clk_unprepare(efm_port->clk);
438 clk_put(efm_port->clk);
439 iounmap(port->membase);
440 }
441
efm32_uart_request_port(struct uart_port * port)442 static int efm32_uart_request_port(struct uart_port *port)
443 {
444 struct efm32_uart_port *efm_port = to_efm_port(port);
445 int ret;
446
447 port->membase = ioremap(port->mapbase, 60);
448 if (!efm_port->port.membase) {
449 ret = -ENOMEM;
450 efm_debug(efm_port, "failed to remap\n");
451 goto err_ioremap;
452 }
453
454 efm_port->clk = clk_get(port->dev, NULL);
455 if (IS_ERR(efm_port->clk)) {
456 ret = PTR_ERR(efm_port->clk);
457 efm_debug(efm_port, "failed to get clock\n");
458 goto err_clk_get;
459 }
460
461 ret = clk_prepare(efm_port->clk);
462 if (ret) {
463 clk_put(efm_port->clk);
464 err_clk_get:
465
466 iounmap(port->membase);
467 err_ioremap:
468 return ret;
469 }
470 return 0;
471 }
472
efm32_uart_config_port(struct uart_port * port,int type)473 static void efm32_uart_config_port(struct uart_port *port, int type)
474 {
475 if (type & UART_CONFIG_TYPE &&
476 !efm32_uart_request_port(port))
477 port->type = PORT_EFMUART;
478 }
479
efm32_uart_verify_port(struct uart_port * port,struct serial_struct * serinfo)480 static int efm32_uart_verify_port(struct uart_port *port,
481 struct serial_struct *serinfo)
482 {
483 int ret = 0;
484
485 if (serinfo->type != PORT_UNKNOWN && serinfo->type != PORT_EFMUART)
486 ret = -EINVAL;
487
488 return ret;
489 }
490
491 static struct uart_ops efm32_uart_pops = {
492 .tx_empty = efm32_uart_tx_empty,
493 .set_mctrl = efm32_uart_set_mctrl,
494 .get_mctrl = efm32_uart_get_mctrl,
495 .stop_tx = efm32_uart_stop_tx,
496 .start_tx = efm32_uart_start_tx,
497 .stop_rx = efm32_uart_stop_rx,
498 .break_ctl = efm32_uart_break_ctl,
499 .startup = efm32_uart_startup,
500 .shutdown = efm32_uart_shutdown,
501 .set_termios = efm32_uart_set_termios,
502 .type = efm32_uart_type,
503 .release_port = efm32_uart_release_port,
504 .request_port = efm32_uart_request_port,
505 .config_port = efm32_uart_config_port,
506 .verify_port = efm32_uart_verify_port,
507 };
508
509 static struct efm32_uart_port *efm32_uart_ports[5];
510
511 #ifdef CONFIG_SERIAL_EFM32_UART_CONSOLE
efm32_uart_console_putchar(struct uart_port * port,int ch)512 static void efm32_uart_console_putchar(struct uart_port *port, int ch)
513 {
514 struct efm32_uart_port *efm_port = to_efm_port(port);
515 unsigned int timeout = 0x400;
516 u32 status;
517
518 while (1) {
519 status = efm32_uart_read32(efm_port, UARTn_STATUS);
520
521 if (status & UARTn_STATUS_TXBL)
522 break;
523 if (!timeout--)
524 return;
525 }
526 efm32_uart_write32(efm_port, ch, UARTn_TXDATA);
527 }
528
efm32_uart_console_write(struct console * co,const char * s,unsigned int count)529 static void efm32_uart_console_write(struct console *co, const char *s,
530 unsigned int count)
531 {
532 struct efm32_uart_port *efm_port = efm32_uart_ports[co->index];
533 u32 status = efm32_uart_read32(efm_port, UARTn_STATUS);
534 unsigned int timeout = 0x400;
535
536 if (!(status & UARTn_STATUS_TXENS))
537 efm32_uart_write32(efm_port, UARTn_CMD_TXEN, UARTn_CMD);
538
539 uart_console_write(&efm_port->port, s, count,
540 efm32_uart_console_putchar);
541
542 /* Wait for the transmitter to become empty */
543 while (1) {
544 u32 status = efm32_uart_read32(efm_port, UARTn_STATUS);
545 if (status & UARTn_STATUS_TXC)
546 break;
547 if (!timeout--)
548 break;
549 }
550
551 if (!(status & UARTn_STATUS_TXENS))
552 efm32_uart_write32(efm_port, UARTn_CMD_TXDIS, UARTn_CMD);
553 }
554
efm32_uart_console_get_options(struct efm32_uart_port * efm_port,int * baud,int * parity,int * bits)555 static void efm32_uart_console_get_options(struct efm32_uart_port *efm_port,
556 int *baud, int *parity, int *bits)
557 {
558 u32 ctrl = efm32_uart_read32(efm_port, UARTn_CTRL);
559 u32 route, clkdiv, frame;
560
561 if (ctrl & UARTn_CTRL_SYNC)
562 /* not operating in async mode */
563 return;
564
565 route = efm32_uart_read32(efm_port, UARTn_ROUTE);
566 if (!(route & UARTn_ROUTE_TXPEN))
567 /* tx pin not routed */
568 return;
569
570 clkdiv = efm32_uart_read32(efm_port, UARTn_CLKDIV);
571
572 *baud = DIV_ROUND_CLOSEST(4 * efm_port->port.uartclk,
573 16 * (4 + (clkdiv >> 6)));
574
575 frame = efm32_uart_read32(efm_port, UARTn_FRAME);
576 switch (frame & UARTn_FRAME_PARITY__MASK) {
577 case UARTn_FRAME_PARITY_ODD:
578 *parity = 'o';
579 break;
580 case UARTn_FRAME_PARITY_EVEN:
581 *parity = 'e';
582 break;
583 default:
584 *parity = 'n';
585 }
586
587 *bits = (frame & UARTn_FRAME_DATABITS__MASK) -
588 UARTn_FRAME_DATABITS(4) + 4;
589
590 efm_debug(efm_port, "get_opts: options=%d%c%d\n",
591 *baud, *parity, *bits);
592 }
593
efm32_uart_console_setup(struct console * co,char * options)594 static int efm32_uart_console_setup(struct console *co, char *options)
595 {
596 struct efm32_uart_port *efm_port;
597 int baud = 115200;
598 int bits = 8;
599 int parity = 'n';
600 int flow = 'n';
601 int ret;
602
603 if (co->index < 0 || co->index >= ARRAY_SIZE(efm32_uart_ports)) {
604 unsigned i;
605 for (i = 0; i < ARRAY_SIZE(efm32_uart_ports); ++i) {
606 if (efm32_uart_ports[i]) {
607 pr_warn("efm32-console: fall back to console index %u (from %hhi)\n",
608 i, co->index);
609 co->index = i;
610 break;
611 }
612 }
613 }
614
615 efm_port = efm32_uart_ports[co->index];
616 if (!efm_port) {
617 pr_warn("efm32-console: No port at %d\n", co->index);
618 return -ENODEV;
619 }
620
621 ret = clk_prepare(efm_port->clk);
622 if (ret) {
623 dev_warn(efm_port->port.dev,
624 "console: clk_prepare failed: %d\n", ret);
625 return ret;
626 }
627
628 efm_port->port.uartclk = clk_get_rate(efm_port->clk);
629
630 if (options)
631 uart_parse_options(options, &baud, &parity, &bits, &flow);
632 else
633 efm32_uart_console_get_options(efm_port,
634 &baud, &parity, &bits);
635
636 return uart_set_options(&efm_port->port, co, baud, parity, bits, flow);
637 }
638
639 static struct uart_driver efm32_uart_reg;
640
641 static struct console efm32_uart_console = {
642 .name = DEV_NAME,
643 .write = efm32_uart_console_write,
644 .device = uart_console_device,
645 .setup = efm32_uart_console_setup,
646 .flags = CON_PRINTBUFFER,
647 .index = -1,
648 .data = &efm32_uart_reg,
649 };
650
651 #else
652 #define efm32_uart_console (*(struct console *)NULL)
653 #endif /* ifdef CONFIG_SERIAL_EFM32_UART_CONSOLE / else */
654
655 static struct uart_driver efm32_uart_reg = {
656 .owner = THIS_MODULE,
657 .driver_name = DRIVER_NAME,
658 .dev_name = DEV_NAME,
659 .nr = ARRAY_SIZE(efm32_uart_ports),
660 .cons = &efm32_uart_console,
661 };
662
efm32_uart_probe_dt(struct platform_device * pdev,struct efm32_uart_port * efm_port)663 static int efm32_uart_probe_dt(struct platform_device *pdev,
664 struct efm32_uart_port *efm_port)
665 {
666 struct device_node *np = pdev->dev.of_node;
667 u32 location;
668 int ret;
669
670 if (!np)
671 return 1;
672
673 ret = of_property_read_u32(np, "energymicro,location", &location);
674
675 if (ret)
676 /* fall back to wrongly namespaced property */
677 ret = of_property_read_u32(np, "efm32,location", &location);
678
679 if (ret)
680 /* fall back to old and (wrongly) generic property "location" */
681 ret = of_property_read_u32(np, "location", &location);
682
683 if (!ret) {
684 if (location > 5) {
685 dev_err(&pdev->dev, "invalid location\n");
686 return -EINVAL;
687 }
688 efm_debug(efm_port, "using location %u\n", location);
689 efm_port->pdata.location = location;
690 } else {
691 efm_debug(efm_port, "fall back to location 0\n");
692 }
693
694 ret = of_alias_get_id(np, "serial");
695 if (ret < 0) {
696 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);
697 return ret;
698 } else {
699 efm_port->port.line = ret;
700 return 0;
701 }
702
703 }
704
efm32_uart_probe(struct platform_device * pdev)705 static int efm32_uart_probe(struct platform_device *pdev)
706 {
707 struct efm32_uart_port *efm_port;
708 struct resource *res;
709 unsigned int line;
710 int ret;
711
712 efm_port = kzalloc(sizeof(*efm_port), GFP_KERNEL);
713 if (!efm_port) {
714 dev_dbg(&pdev->dev, "failed to allocate private data\n");
715 return -ENOMEM;
716 }
717
718 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
719 if (!res) {
720 ret = -ENODEV;
721 dev_dbg(&pdev->dev, "failed to determine base address\n");
722 goto err_get_base;
723 }
724
725 if (resource_size(res) < 60) {
726 ret = -EINVAL;
727 dev_dbg(&pdev->dev, "memory resource too small\n");
728 goto err_too_small;
729 }
730
731 ret = platform_get_irq(pdev, 0);
732 if (ret <= 0) {
733 dev_dbg(&pdev->dev, "failed to get rx irq\n");
734 goto err_get_rxirq;
735 }
736
737 efm_port->port.irq = ret;
738
739 ret = platform_get_irq(pdev, 1);
740 if (ret <= 0)
741 ret = efm_port->port.irq + 1;
742
743 efm_port->txirq = ret;
744
745 efm_port->port.dev = &pdev->dev;
746 efm_port->port.mapbase = res->start;
747 efm_port->port.type = PORT_EFMUART;
748 efm_port->port.iotype = UPIO_MEM32;
749 efm_port->port.fifosize = 2;
750 efm_port->port.ops = &efm32_uart_pops;
751 efm_port->port.flags = UPF_BOOT_AUTOCONF;
752
753 ret = efm32_uart_probe_dt(pdev, efm_port);
754 if (ret > 0) {
755 /* not created by device tree */
756 const struct efm32_uart_pdata *pdata = dev_get_platdata(&pdev->dev);
757
758 efm_port->port.line = pdev->id;
759
760 if (pdata)
761 efm_port->pdata = *pdata;
762 } else if (ret < 0)
763 goto err_probe_dt;
764
765 line = efm_port->port.line;
766
767 if (line >= 0 && line < ARRAY_SIZE(efm32_uart_ports))
768 efm32_uart_ports[line] = efm_port;
769
770 ret = uart_add_one_port(&efm32_uart_reg, &efm_port->port);
771 if (ret) {
772 dev_dbg(&pdev->dev, "failed to add port: %d\n", ret);
773
774 if (line >= 0 && line < ARRAY_SIZE(efm32_uart_ports))
775 efm32_uart_ports[line] = NULL;
776 err_probe_dt:
777 err_get_rxirq:
778 err_too_small:
779 err_get_base:
780 kfree(efm_port);
781 } else {
782 platform_set_drvdata(pdev, efm_port);
783 dev_dbg(&pdev->dev, "\\o/\n");
784 }
785
786 return ret;
787 }
788
efm32_uart_remove(struct platform_device * pdev)789 static int efm32_uart_remove(struct platform_device *pdev)
790 {
791 struct efm32_uart_port *efm_port = platform_get_drvdata(pdev);
792 unsigned int line = efm_port->port.line;
793
794 uart_remove_one_port(&efm32_uart_reg, &efm_port->port);
795
796 if (line >= 0 && line < ARRAY_SIZE(efm32_uart_ports))
797 efm32_uart_ports[line] = NULL;
798
799 kfree(efm_port);
800
801 return 0;
802 }
803
804 static const struct of_device_id efm32_uart_dt_ids[] = {
805 {
806 .compatible = "energymicro,efm32-uart",
807 }, {
808 /* doesn't follow the "vendor,device" scheme, don't use */
809 .compatible = "efm32,uart",
810 }, {
811 /* sentinel */
812 }
813 };
814 MODULE_DEVICE_TABLE(of, efm32_uart_dt_ids);
815
816 static struct platform_driver efm32_uart_driver = {
817 .probe = efm32_uart_probe,
818 .remove = efm32_uart_remove,
819
820 .driver = {
821 .name = DRIVER_NAME,
822 .owner = THIS_MODULE,
823 .of_match_table = efm32_uart_dt_ids,
824 },
825 };
826
efm32_uart_init(void)827 static int __init efm32_uart_init(void)
828 {
829 int ret;
830
831 ret = uart_register_driver(&efm32_uart_reg);
832 if (ret)
833 return ret;
834
835 ret = platform_driver_register(&efm32_uart_driver);
836 if (ret)
837 uart_unregister_driver(&efm32_uart_reg);
838
839 pr_info("EFM32 UART/USART driver\n");
840
841 return ret;
842 }
843 module_init(efm32_uart_init);
844
efm32_uart_exit(void)845 static void __exit efm32_uart_exit(void)
846 {
847 platform_driver_unregister(&efm32_uart_driver);
848 uart_unregister_driver(&efm32_uart_reg);
849 }
850 module_exit(efm32_uart_exit);
851
852 MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
853 MODULE_DESCRIPTION("EFM32 UART/USART driver");
854 MODULE_LICENSE("GPL v2");
855 MODULE_ALIAS("platform:" DRIVER_NAME);
856