1 /*
2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #define SUPPORT_SYSRQ
22 #endif
23
24 #undef DEBUG
25
26 #include <linux/clk.h>
27 #include <linux/console.h>
28 #include <linux/ctype.h>
29 #include <linux/cpufreq.h>
30 #include <linux/delay.h>
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/err.h>
34 #include <linux/errno.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
37 #include <linux/ioport.h>
38 #include <linux/major.h>
39 #include <linux/module.h>
40 #include <linux/mm.h>
41 #include <linux/notifier.h>
42 #include <linux/of.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/scatterlist.h>
46 #include <linux/serial.h>
47 #include <linux/serial_sci.h>
48 #include <linux/sh_dma.h>
49 #include <linux/slab.h>
50 #include <linux/string.h>
51 #include <linux/sysrq.h>
52 #include <linux/timer.h>
53 #include <linux/tty.h>
54 #include <linux/tty_flip.h>
55
56 #ifdef CONFIG_SUPERH
57 #include <asm/sh_bios.h>
58 #endif
59
60 #include "sh-sci.h"
61
62 /* Offsets into the sci_port->irqs array */
63 enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71 };
72
73 #define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
79 struct sci_port {
80 struct uart_port port;
81
82 /* Platform configuration */
83 struct plat_sci_port *cfg;
84 int overrun_bit;
85 unsigned int error_mask;
86 unsigned int sampling_rate;
87
88
89 /* Break timer */
90 struct timer_list break_timer;
91 int break_flag;
92
93 /* Interface clock */
94 struct clk *iclk;
95 /* Function clock */
96 struct clk *fclk;
97
98 int irqs[SCIx_NR_IRQS];
99 char *irqstr[SCIx_NR_IRQS];
100
101 struct dma_chan *chan_tx;
102 struct dma_chan *chan_rx;
103
104 #ifdef CONFIG_SERIAL_SH_SCI_DMA
105 struct dma_async_tx_descriptor *desc_tx;
106 struct dma_async_tx_descriptor *desc_rx[2];
107 dma_cookie_t cookie_tx;
108 dma_cookie_t cookie_rx[2];
109 dma_cookie_t active_rx;
110 struct scatterlist sg_tx;
111 unsigned int sg_len_tx;
112 struct scatterlist sg_rx[2];
113 size_t buf_len_rx;
114 struct sh_dmae_slave param_tx;
115 struct sh_dmae_slave param_rx;
116 struct work_struct work_tx;
117 struct work_struct work_rx;
118 struct timer_list rx_timer;
119 unsigned int rx_timeout;
120 #endif
121
122 struct notifier_block freq_transition;
123 };
124
125 /* Function prototypes */
126 static void sci_start_tx(struct uart_port *port);
127 static void sci_stop_tx(struct uart_port *port);
128 static void sci_start_rx(struct uart_port *port);
129
130 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
131
132 static struct sci_port sci_ports[SCI_NPORTS];
133 static struct uart_driver sci_uart_driver;
134
135 static inline struct sci_port *
to_sci_port(struct uart_port * uart)136 to_sci_port(struct uart_port *uart)
137 {
138 return container_of(uart, struct sci_port, port);
139 }
140
141 struct plat_sci_reg {
142 u8 offset, size;
143 };
144
145 /* Helper for invalidating specific entries of an inherited map. */
146 #define sci_reg_invalid { .offset = 0, .size = 0 }
147
148 static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
149 [SCIx_PROBE_REGTYPE] = {
150 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
151 },
152
153 /*
154 * Common SCI definitions, dependent on the port's regshift
155 * value.
156 */
157 [SCIx_SCI_REGTYPE] = {
158 [SCSMR] = { 0x00, 8 },
159 [SCBRR] = { 0x01, 8 },
160 [SCSCR] = { 0x02, 8 },
161 [SCxTDR] = { 0x03, 8 },
162 [SCxSR] = { 0x04, 8 },
163 [SCxRDR] = { 0x05, 8 },
164 [SCFCR] = sci_reg_invalid,
165 [SCFDR] = sci_reg_invalid,
166 [SCTFDR] = sci_reg_invalid,
167 [SCRFDR] = sci_reg_invalid,
168 [SCSPTR] = sci_reg_invalid,
169 [SCLSR] = sci_reg_invalid,
170 [HSSRR] = sci_reg_invalid,
171 },
172
173 /*
174 * Common definitions for legacy IrDA ports.
175 */
176 [SCIx_IRDA_REGTYPE] = {
177 [SCSMR] = { 0x00, 8 },
178 [SCBRR] = { 0x02, 8 },
179 [SCSCR] = { 0x04, 8 },
180 [SCxTDR] = { 0x06, 8 },
181 [SCxSR] = { 0x08, 16 },
182 [SCxRDR] = { 0x0a, 8 },
183 [SCFCR] = { 0x0c, 8 },
184 [SCFDR] = { 0x0e, 16 },
185 [SCTFDR] = sci_reg_invalid,
186 [SCRFDR] = sci_reg_invalid,
187 [SCSPTR] = sci_reg_invalid,
188 [SCLSR] = sci_reg_invalid,
189 [HSSRR] = sci_reg_invalid,
190 },
191
192 /*
193 * Common SCIFA definitions.
194 */
195 [SCIx_SCIFA_REGTYPE] = {
196 [SCSMR] = { 0x00, 16 },
197 [SCBRR] = { 0x04, 8 },
198 [SCSCR] = { 0x08, 16 },
199 [SCxTDR] = { 0x20, 8 },
200 [SCxSR] = { 0x14, 16 },
201 [SCxRDR] = { 0x24, 8 },
202 [SCFCR] = { 0x18, 16 },
203 [SCFDR] = { 0x1c, 16 },
204 [SCTFDR] = sci_reg_invalid,
205 [SCRFDR] = sci_reg_invalid,
206 [SCSPTR] = sci_reg_invalid,
207 [SCLSR] = sci_reg_invalid,
208 [HSSRR] = sci_reg_invalid,
209 },
210
211 /*
212 * Common SCIFB definitions.
213 */
214 [SCIx_SCIFB_REGTYPE] = {
215 [SCSMR] = { 0x00, 16 },
216 [SCBRR] = { 0x04, 8 },
217 [SCSCR] = { 0x08, 16 },
218 [SCxTDR] = { 0x40, 8 },
219 [SCxSR] = { 0x14, 16 },
220 [SCxRDR] = { 0x60, 8 },
221 [SCFCR] = { 0x18, 16 },
222 [SCFDR] = sci_reg_invalid,
223 [SCTFDR] = { 0x38, 16 },
224 [SCRFDR] = { 0x3c, 16 },
225 [SCSPTR] = sci_reg_invalid,
226 [SCLSR] = sci_reg_invalid,
227 [HSSRR] = sci_reg_invalid,
228 },
229
230 /*
231 * Common SH-2(A) SCIF definitions for ports with FIFO data
232 * count registers.
233 */
234 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
235 [SCSMR] = { 0x00, 16 },
236 [SCBRR] = { 0x04, 8 },
237 [SCSCR] = { 0x08, 16 },
238 [SCxTDR] = { 0x0c, 8 },
239 [SCxSR] = { 0x10, 16 },
240 [SCxRDR] = { 0x14, 8 },
241 [SCFCR] = { 0x18, 16 },
242 [SCFDR] = { 0x1c, 16 },
243 [SCTFDR] = sci_reg_invalid,
244 [SCRFDR] = sci_reg_invalid,
245 [SCSPTR] = { 0x20, 16 },
246 [SCLSR] = { 0x24, 16 },
247 [HSSRR] = sci_reg_invalid,
248 },
249
250 /*
251 * Common SH-3 SCIF definitions.
252 */
253 [SCIx_SH3_SCIF_REGTYPE] = {
254 [SCSMR] = { 0x00, 8 },
255 [SCBRR] = { 0x02, 8 },
256 [SCSCR] = { 0x04, 8 },
257 [SCxTDR] = { 0x06, 8 },
258 [SCxSR] = { 0x08, 16 },
259 [SCxRDR] = { 0x0a, 8 },
260 [SCFCR] = { 0x0c, 8 },
261 [SCFDR] = { 0x0e, 16 },
262 [SCTFDR] = sci_reg_invalid,
263 [SCRFDR] = sci_reg_invalid,
264 [SCSPTR] = sci_reg_invalid,
265 [SCLSR] = sci_reg_invalid,
266 [HSSRR] = sci_reg_invalid,
267 },
268
269 /*
270 * Common SH-4(A) SCIF(B) definitions.
271 */
272 [SCIx_SH4_SCIF_REGTYPE] = {
273 [SCSMR] = { 0x00, 16 },
274 [SCBRR] = { 0x04, 8 },
275 [SCSCR] = { 0x08, 16 },
276 [SCxTDR] = { 0x0c, 8 },
277 [SCxSR] = { 0x10, 16 },
278 [SCxRDR] = { 0x14, 8 },
279 [SCFCR] = { 0x18, 16 },
280 [SCFDR] = { 0x1c, 16 },
281 [SCTFDR] = sci_reg_invalid,
282 [SCRFDR] = sci_reg_invalid,
283 [SCSPTR] = { 0x20, 16 },
284 [SCLSR] = { 0x24, 16 },
285 [HSSRR] = sci_reg_invalid,
286 },
287
288 /*
289 * Common HSCIF definitions.
290 */
291 [SCIx_HSCIF_REGTYPE] = {
292 [SCSMR] = { 0x00, 16 },
293 [SCBRR] = { 0x04, 8 },
294 [SCSCR] = { 0x08, 16 },
295 [SCxTDR] = { 0x0c, 8 },
296 [SCxSR] = { 0x10, 16 },
297 [SCxRDR] = { 0x14, 8 },
298 [SCFCR] = { 0x18, 16 },
299 [SCFDR] = { 0x1c, 16 },
300 [SCTFDR] = sci_reg_invalid,
301 [SCRFDR] = sci_reg_invalid,
302 [SCSPTR] = { 0x20, 16 },
303 [SCLSR] = { 0x24, 16 },
304 [HSSRR] = { 0x40, 16 },
305 },
306
307 /*
308 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
309 * register.
310 */
311 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
312 [SCSMR] = { 0x00, 16 },
313 [SCBRR] = { 0x04, 8 },
314 [SCSCR] = { 0x08, 16 },
315 [SCxTDR] = { 0x0c, 8 },
316 [SCxSR] = { 0x10, 16 },
317 [SCxRDR] = { 0x14, 8 },
318 [SCFCR] = { 0x18, 16 },
319 [SCFDR] = { 0x1c, 16 },
320 [SCTFDR] = sci_reg_invalid,
321 [SCRFDR] = sci_reg_invalid,
322 [SCSPTR] = sci_reg_invalid,
323 [SCLSR] = { 0x24, 16 },
324 [HSSRR] = sci_reg_invalid,
325 },
326
327 /*
328 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
329 * count registers.
330 */
331 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
332 [SCSMR] = { 0x00, 16 },
333 [SCBRR] = { 0x04, 8 },
334 [SCSCR] = { 0x08, 16 },
335 [SCxTDR] = { 0x0c, 8 },
336 [SCxSR] = { 0x10, 16 },
337 [SCxRDR] = { 0x14, 8 },
338 [SCFCR] = { 0x18, 16 },
339 [SCFDR] = { 0x1c, 16 },
340 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
341 [SCRFDR] = { 0x20, 16 },
342 [SCSPTR] = { 0x24, 16 },
343 [SCLSR] = { 0x28, 16 },
344 [HSSRR] = sci_reg_invalid,
345 },
346
347 /*
348 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
349 * registers.
350 */
351 [SCIx_SH7705_SCIF_REGTYPE] = {
352 [SCSMR] = { 0x00, 16 },
353 [SCBRR] = { 0x04, 8 },
354 [SCSCR] = { 0x08, 16 },
355 [SCxTDR] = { 0x20, 8 },
356 [SCxSR] = { 0x14, 16 },
357 [SCxRDR] = { 0x24, 8 },
358 [SCFCR] = { 0x18, 16 },
359 [SCFDR] = { 0x1c, 16 },
360 [SCTFDR] = sci_reg_invalid,
361 [SCRFDR] = sci_reg_invalid,
362 [SCSPTR] = sci_reg_invalid,
363 [SCLSR] = sci_reg_invalid,
364 [HSSRR] = sci_reg_invalid,
365 },
366 };
367
368 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
369
370 /*
371 * The "offset" here is rather misleading, in that it refers to an enum
372 * value relative to the port mapping rather than the fixed offset
373 * itself, which needs to be manually retrieved from the platform's
374 * register map for the given port.
375 */
sci_serial_in(struct uart_port * p,int offset)376 static unsigned int sci_serial_in(struct uart_port *p, int offset)
377 {
378 struct plat_sci_reg *reg = sci_getreg(p, offset);
379
380 if (reg->size == 8)
381 return ioread8(p->membase + (reg->offset << p->regshift));
382 else if (reg->size == 16)
383 return ioread16(p->membase + (reg->offset << p->regshift));
384 else
385 WARN(1, "Invalid register access\n");
386
387 return 0;
388 }
389
sci_serial_out(struct uart_port * p,int offset,int value)390 static void sci_serial_out(struct uart_port *p, int offset, int value)
391 {
392 struct plat_sci_reg *reg = sci_getreg(p, offset);
393
394 if (reg->size == 8)
395 iowrite8(value, p->membase + (reg->offset << p->regshift));
396 else if (reg->size == 16)
397 iowrite16(value, p->membase + (reg->offset << p->regshift));
398 else
399 WARN(1, "Invalid register access\n");
400 }
401
sci_probe_regmap(struct plat_sci_port * cfg)402 static int sci_probe_regmap(struct plat_sci_port *cfg)
403 {
404 switch (cfg->type) {
405 case PORT_SCI:
406 cfg->regtype = SCIx_SCI_REGTYPE;
407 break;
408 case PORT_IRDA:
409 cfg->regtype = SCIx_IRDA_REGTYPE;
410 break;
411 case PORT_SCIFA:
412 cfg->regtype = SCIx_SCIFA_REGTYPE;
413 break;
414 case PORT_SCIFB:
415 cfg->regtype = SCIx_SCIFB_REGTYPE;
416 break;
417 case PORT_SCIF:
418 /*
419 * The SH-4 is a bit of a misnomer here, although that's
420 * where this particular port layout originated. This
421 * configuration (or some slight variation thereof)
422 * remains the dominant model for all SCIFs.
423 */
424 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
425 break;
426 case PORT_HSCIF:
427 cfg->regtype = SCIx_HSCIF_REGTYPE;
428 break;
429 default:
430 pr_err("Can't probe register map for given port\n");
431 return -EINVAL;
432 }
433
434 return 0;
435 }
436
sci_port_enable(struct sci_port * sci_port)437 static void sci_port_enable(struct sci_port *sci_port)
438 {
439 if (!sci_port->port.dev)
440 return;
441
442 pm_runtime_get_sync(sci_port->port.dev);
443
444 clk_prepare_enable(sci_port->iclk);
445 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
446 clk_prepare_enable(sci_port->fclk);
447 }
448
sci_port_disable(struct sci_port * sci_port)449 static void sci_port_disable(struct sci_port *sci_port)
450 {
451 if (!sci_port->port.dev)
452 return;
453
454 /* Cancel the break timer to ensure that the timer handler will not try
455 * to access the hardware with clocks and power disabled. Reset the
456 * break flag to make the break debouncing state machine ready for the
457 * next break.
458 */
459 del_timer_sync(&sci_port->break_timer);
460 sci_port->break_flag = 0;
461
462 clk_disable_unprepare(sci_port->fclk);
463 clk_disable_unprepare(sci_port->iclk);
464
465 pm_runtime_put_sync(sci_port->port.dev);
466 }
467
468 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
469
470 #ifdef CONFIG_CONSOLE_POLL
sci_poll_get_char(struct uart_port * port)471 static int sci_poll_get_char(struct uart_port *port)
472 {
473 unsigned short status;
474 int c;
475
476 do {
477 status = serial_port_in(port, SCxSR);
478 if (status & SCxSR_ERRORS(port)) {
479 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
480 continue;
481 }
482 break;
483 } while (1);
484
485 if (!(status & SCxSR_RDxF(port)))
486 return NO_POLL_CHAR;
487
488 c = serial_port_in(port, SCxRDR);
489
490 /* Dummy read */
491 serial_port_in(port, SCxSR);
492 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
493
494 return c;
495 }
496 #endif
497
sci_poll_put_char(struct uart_port * port,unsigned char c)498 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
499 {
500 unsigned short status;
501
502 do {
503 status = serial_port_in(port, SCxSR);
504 } while (!(status & SCxSR_TDxE(port)));
505
506 serial_port_out(port, SCxTDR, c);
507 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
508 }
509 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
510
sci_init_pins(struct uart_port * port,unsigned int cflag)511 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
512 {
513 struct sci_port *s = to_sci_port(port);
514 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
515
516 /*
517 * Use port-specific handler if provided.
518 */
519 if (s->cfg->ops && s->cfg->ops->init_pins) {
520 s->cfg->ops->init_pins(port, cflag);
521 return;
522 }
523
524 /*
525 * For the generic path SCSPTR is necessary. Bail out if that's
526 * unavailable, too.
527 */
528 if (!reg->size)
529 return;
530
531 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
532 ((!(cflag & CRTSCTS)))) {
533 unsigned short status;
534
535 status = serial_port_in(port, SCSPTR);
536 status &= ~SCSPTR_CTSIO;
537 status |= SCSPTR_RTSIO;
538 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
539 }
540 }
541
sci_txfill(struct uart_port * port)542 static int sci_txfill(struct uart_port *port)
543 {
544 struct plat_sci_reg *reg;
545
546 reg = sci_getreg(port, SCTFDR);
547 if (reg->size)
548 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
549
550 reg = sci_getreg(port, SCFDR);
551 if (reg->size)
552 return serial_port_in(port, SCFDR) >> 8;
553
554 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
555 }
556
sci_txroom(struct uart_port * port)557 static int sci_txroom(struct uart_port *port)
558 {
559 return port->fifosize - sci_txfill(port);
560 }
561
sci_rxfill(struct uart_port * port)562 static int sci_rxfill(struct uart_port *port)
563 {
564 struct plat_sci_reg *reg;
565
566 reg = sci_getreg(port, SCRFDR);
567 if (reg->size)
568 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
569
570 reg = sci_getreg(port, SCFDR);
571 if (reg->size)
572 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
573
574 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
575 }
576
577 /*
578 * SCI helper for checking the state of the muxed port/RXD pins.
579 */
sci_rxd_in(struct uart_port * port)580 static inline int sci_rxd_in(struct uart_port *port)
581 {
582 struct sci_port *s = to_sci_port(port);
583
584 if (s->cfg->port_reg <= 0)
585 return 1;
586
587 /* Cast for ARM damage */
588 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
589 }
590
591 /* ********************************************************************** *
592 * the interrupt related routines *
593 * ********************************************************************** */
594
sci_transmit_chars(struct uart_port * port)595 static void sci_transmit_chars(struct uart_port *port)
596 {
597 struct circ_buf *xmit = &port->state->xmit;
598 unsigned int stopped = uart_tx_stopped(port);
599 unsigned short status;
600 unsigned short ctrl;
601 int count;
602
603 status = serial_port_in(port, SCxSR);
604 if (!(status & SCxSR_TDxE(port))) {
605 ctrl = serial_port_in(port, SCSCR);
606 if (uart_circ_empty(xmit))
607 ctrl &= ~SCSCR_TIE;
608 else
609 ctrl |= SCSCR_TIE;
610 serial_port_out(port, SCSCR, ctrl);
611 return;
612 }
613
614 count = sci_txroom(port);
615
616 do {
617 unsigned char c;
618
619 if (port->x_char) {
620 c = port->x_char;
621 port->x_char = 0;
622 } else if (!uart_circ_empty(xmit) && !stopped) {
623 c = xmit->buf[xmit->tail];
624 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
625 } else {
626 break;
627 }
628
629 serial_port_out(port, SCxTDR, c);
630
631 port->icount.tx++;
632 } while (--count > 0);
633
634 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
635
636 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
637 uart_write_wakeup(port);
638 if (uart_circ_empty(xmit)) {
639 sci_stop_tx(port);
640 } else {
641 ctrl = serial_port_in(port, SCSCR);
642
643 if (port->type != PORT_SCI) {
644 serial_port_in(port, SCxSR); /* Dummy read */
645 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
646 }
647
648 ctrl |= SCSCR_TIE;
649 serial_port_out(port, SCSCR, ctrl);
650 }
651 }
652
653 /* On SH3, SCIF may read end-of-break as a space->mark char */
654 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
655
sci_receive_chars(struct uart_port * port)656 static void sci_receive_chars(struct uart_port *port)
657 {
658 struct sci_port *sci_port = to_sci_port(port);
659 struct tty_port *tport = &port->state->port;
660 int i, count, copied = 0;
661 unsigned short status;
662 unsigned char flag;
663
664 status = serial_port_in(port, SCxSR);
665 if (!(status & SCxSR_RDxF(port)))
666 return;
667
668 while (1) {
669 /* Don't copy more bytes than there is room for in the buffer */
670 count = tty_buffer_request_room(tport, sci_rxfill(port));
671
672 /* If for any reason we can't copy more data, we're done! */
673 if (count == 0)
674 break;
675
676 if (port->type == PORT_SCI) {
677 char c = serial_port_in(port, SCxRDR);
678 if (uart_handle_sysrq_char(port, c) ||
679 sci_port->break_flag)
680 count = 0;
681 else
682 tty_insert_flip_char(tport, c, TTY_NORMAL);
683 } else {
684 for (i = 0; i < count; i++) {
685 char c = serial_port_in(port, SCxRDR);
686
687 status = serial_port_in(port, SCxSR);
688 #if defined(CONFIG_CPU_SH3)
689 /* Skip "chars" during break */
690 if (sci_port->break_flag) {
691 if ((c == 0) &&
692 (status & SCxSR_FER(port))) {
693 count--; i--;
694 continue;
695 }
696
697 /* Nonzero => end-of-break */
698 dev_dbg(port->dev, "debounce<%02x>\n", c);
699 sci_port->break_flag = 0;
700
701 if (STEPFN(c)) {
702 count--; i--;
703 continue;
704 }
705 }
706 #endif /* CONFIG_CPU_SH3 */
707 if (uart_handle_sysrq_char(port, c)) {
708 count--; i--;
709 continue;
710 }
711
712 /* Store data and status */
713 if (status & SCxSR_FER(port)) {
714 flag = TTY_FRAME;
715 port->icount.frame++;
716 dev_notice(port->dev, "frame error\n");
717 } else if (status & SCxSR_PER(port)) {
718 flag = TTY_PARITY;
719 port->icount.parity++;
720 dev_notice(port->dev, "parity error\n");
721 } else
722 flag = TTY_NORMAL;
723
724 tty_insert_flip_char(tport, c, flag);
725 }
726 }
727
728 serial_port_in(port, SCxSR); /* dummy read */
729 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
730
731 copied += count;
732 port->icount.rx += count;
733 }
734
735 if (copied) {
736 /* Tell the rest of the system the news. New characters! */
737 tty_flip_buffer_push(tport);
738 } else {
739 serial_port_in(port, SCxSR); /* dummy read */
740 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
741 }
742 }
743
744 #define SCI_BREAK_JIFFIES (HZ/20)
745
746 /*
747 * The sci generates interrupts during the break,
748 * 1 per millisecond or so during the break period, for 9600 baud.
749 * So dont bother disabling interrupts.
750 * But dont want more than 1 break event.
751 * Use a kernel timer to periodically poll the rx line until
752 * the break is finished.
753 */
sci_schedule_break_timer(struct sci_port * port)754 static inline void sci_schedule_break_timer(struct sci_port *port)
755 {
756 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
757 }
758
759 /* Ensure that two consecutive samples find the break over. */
sci_break_timer(unsigned long data)760 static void sci_break_timer(unsigned long data)
761 {
762 struct sci_port *port = (struct sci_port *)data;
763
764 if (sci_rxd_in(&port->port) == 0) {
765 port->break_flag = 1;
766 sci_schedule_break_timer(port);
767 } else if (port->break_flag == 1) {
768 /* break is over. */
769 port->break_flag = 2;
770 sci_schedule_break_timer(port);
771 } else
772 port->break_flag = 0;
773 }
774
sci_handle_errors(struct uart_port * port)775 static int sci_handle_errors(struct uart_port *port)
776 {
777 int copied = 0;
778 unsigned short status = serial_port_in(port, SCxSR);
779 struct tty_port *tport = &port->state->port;
780 struct sci_port *s = to_sci_port(port);
781
782 /* Handle overruns */
783 if (status & (1 << s->overrun_bit)) {
784 port->icount.overrun++;
785
786 /* overrun error */
787 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
788 copied++;
789
790 dev_notice(port->dev, "overrun error\n");
791 }
792
793 if (status & SCxSR_FER(port)) {
794 if (sci_rxd_in(port) == 0) {
795 /* Notify of BREAK */
796 struct sci_port *sci_port = to_sci_port(port);
797
798 if (!sci_port->break_flag) {
799 port->icount.brk++;
800
801 sci_port->break_flag = 1;
802 sci_schedule_break_timer(sci_port);
803
804 /* Do sysrq handling. */
805 if (uart_handle_break(port))
806 return 0;
807
808 dev_dbg(port->dev, "BREAK detected\n");
809
810 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
811 copied++;
812 }
813
814 } else {
815 /* frame error */
816 port->icount.frame++;
817
818 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
819 copied++;
820
821 dev_notice(port->dev, "frame error\n");
822 }
823 }
824
825 if (status & SCxSR_PER(port)) {
826 /* parity error */
827 port->icount.parity++;
828
829 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
830 copied++;
831
832 dev_notice(port->dev, "parity error\n");
833 }
834
835 if (copied)
836 tty_flip_buffer_push(tport);
837
838 return copied;
839 }
840
sci_handle_fifo_overrun(struct uart_port * port)841 static int sci_handle_fifo_overrun(struct uart_port *port)
842 {
843 struct tty_port *tport = &port->state->port;
844 struct sci_port *s = to_sci_port(port);
845 struct plat_sci_reg *reg;
846 int copied = 0;
847
848 reg = sci_getreg(port, SCLSR);
849 if (!reg->size)
850 return 0;
851
852 if ((serial_port_in(port, SCLSR) & (1 << s->overrun_bit))) {
853 serial_port_out(port, SCLSR, 0);
854
855 port->icount.overrun++;
856
857 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
858 tty_flip_buffer_push(tport);
859
860 dev_notice(port->dev, "overrun error\n");
861 copied++;
862 }
863
864 return copied;
865 }
866
sci_handle_breaks(struct uart_port * port)867 static int sci_handle_breaks(struct uart_port *port)
868 {
869 int copied = 0;
870 unsigned short status = serial_port_in(port, SCxSR);
871 struct tty_port *tport = &port->state->port;
872 struct sci_port *s = to_sci_port(port);
873
874 if (uart_handle_break(port))
875 return 0;
876
877 if (!s->break_flag && status & SCxSR_BRK(port)) {
878 #if defined(CONFIG_CPU_SH3)
879 /* Debounce break */
880 s->break_flag = 1;
881 #endif
882
883 port->icount.brk++;
884
885 /* Notify of BREAK */
886 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
887 copied++;
888
889 dev_dbg(port->dev, "BREAK detected\n");
890 }
891
892 if (copied)
893 tty_flip_buffer_push(tport);
894
895 copied += sci_handle_fifo_overrun(port);
896
897 return copied;
898 }
899
sci_rx_interrupt(int irq,void * ptr)900 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
901 {
902 #ifdef CONFIG_SERIAL_SH_SCI_DMA
903 struct uart_port *port = ptr;
904 struct sci_port *s = to_sci_port(port);
905
906 if (s->chan_rx) {
907 u16 scr = serial_port_in(port, SCSCR);
908 u16 ssr = serial_port_in(port, SCxSR);
909
910 /* Disable future Rx interrupts */
911 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
912 disable_irq_nosync(irq);
913 scr |= SCSCR_RDRQE;
914 } else {
915 scr &= ~SCSCR_RIE;
916 }
917 serial_port_out(port, SCSCR, scr);
918 /* Clear current interrupt */
919 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
920 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
921 jiffies, s->rx_timeout);
922 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
923
924 return IRQ_HANDLED;
925 }
926 #endif
927
928 /* I think sci_receive_chars has to be called irrespective
929 * of whether the I_IXOFF is set, otherwise, how is the interrupt
930 * to be disabled?
931 */
932 sci_receive_chars(ptr);
933
934 return IRQ_HANDLED;
935 }
936
sci_tx_interrupt(int irq,void * ptr)937 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
938 {
939 struct uart_port *port = ptr;
940 unsigned long flags;
941
942 spin_lock_irqsave(&port->lock, flags);
943 sci_transmit_chars(port);
944 spin_unlock_irqrestore(&port->lock, flags);
945
946 return IRQ_HANDLED;
947 }
948
sci_er_interrupt(int irq,void * ptr)949 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
950 {
951 struct uart_port *port = ptr;
952
953 /* Handle errors */
954 if (port->type == PORT_SCI) {
955 if (sci_handle_errors(port)) {
956 /* discard character in rx buffer */
957 serial_port_in(port, SCxSR);
958 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
959 }
960 } else {
961 sci_handle_fifo_overrun(port);
962 sci_rx_interrupt(irq, ptr);
963 }
964
965 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
966
967 /* Kick the transmission */
968 sci_tx_interrupt(irq, ptr);
969
970 return IRQ_HANDLED;
971 }
972
sci_br_interrupt(int irq,void * ptr)973 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
974 {
975 struct uart_port *port = ptr;
976
977 /* Handle BREAKs */
978 sci_handle_breaks(port);
979 serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
980
981 return IRQ_HANDLED;
982 }
983
port_rx_irq_mask(struct uart_port * port)984 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
985 {
986 /*
987 * Not all ports (such as SCIFA) will support REIE. Rather than
988 * special-casing the port type, we check the port initialization
989 * IRQ enable mask to see whether the IRQ is desired at all. If
990 * it's unset, it's logically inferred that there's no point in
991 * testing for it.
992 */
993 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
994 }
995
sci_mpxed_interrupt(int irq,void * ptr)996 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
997 {
998 unsigned short ssr_status, scr_status, err_enabled;
999 struct uart_port *port = ptr;
1000 struct sci_port *s = to_sci_port(port);
1001 irqreturn_t ret = IRQ_NONE;
1002
1003 ssr_status = serial_port_in(port, SCxSR);
1004 scr_status = serial_port_in(port, SCSCR);
1005 err_enabled = scr_status & port_rx_irq_mask(port);
1006
1007 /* Tx Interrupt */
1008 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1009 !s->chan_tx)
1010 ret = sci_tx_interrupt(irq, ptr);
1011
1012 /*
1013 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1014 * DR flags
1015 */
1016 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1017 (scr_status & SCSCR_RIE))
1018 ret = sci_rx_interrupt(irq, ptr);
1019
1020 /* Error Interrupt */
1021 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1022 ret = sci_er_interrupt(irq, ptr);
1023
1024 /* Break Interrupt */
1025 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1026 ret = sci_br_interrupt(irq, ptr);
1027
1028 return ret;
1029 }
1030
1031 /*
1032 * Here we define a transition notifier so that we can update all of our
1033 * ports' baud rate when the peripheral clock changes.
1034 */
sci_notifier(struct notifier_block * self,unsigned long phase,void * p)1035 static int sci_notifier(struct notifier_block *self,
1036 unsigned long phase, void *p)
1037 {
1038 struct sci_port *sci_port;
1039 unsigned long flags;
1040
1041 sci_port = container_of(self, struct sci_port, freq_transition);
1042
1043 if (phase == CPUFREQ_POSTCHANGE) {
1044 struct uart_port *port = &sci_port->port;
1045
1046 spin_lock_irqsave(&port->lock, flags);
1047 port->uartclk = clk_get_rate(sci_port->iclk);
1048 spin_unlock_irqrestore(&port->lock, flags);
1049 }
1050
1051 return NOTIFY_OK;
1052 }
1053
1054 static struct sci_irq_desc {
1055 const char *desc;
1056 irq_handler_t handler;
1057 } sci_irq_desc[] = {
1058 /*
1059 * Split out handlers, the default case.
1060 */
1061 [SCIx_ERI_IRQ] = {
1062 .desc = "rx err",
1063 .handler = sci_er_interrupt,
1064 },
1065
1066 [SCIx_RXI_IRQ] = {
1067 .desc = "rx full",
1068 .handler = sci_rx_interrupt,
1069 },
1070
1071 [SCIx_TXI_IRQ] = {
1072 .desc = "tx empty",
1073 .handler = sci_tx_interrupt,
1074 },
1075
1076 [SCIx_BRI_IRQ] = {
1077 .desc = "break",
1078 .handler = sci_br_interrupt,
1079 },
1080
1081 /*
1082 * Special muxed handler.
1083 */
1084 [SCIx_MUX_IRQ] = {
1085 .desc = "mux",
1086 .handler = sci_mpxed_interrupt,
1087 },
1088 };
1089
sci_request_irq(struct sci_port * port)1090 static int sci_request_irq(struct sci_port *port)
1091 {
1092 struct uart_port *up = &port->port;
1093 int i, j, ret = 0;
1094
1095 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1096 struct sci_irq_desc *desc;
1097 int irq;
1098
1099 if (SCIx_IRQ_IS_MUXED(port)) {
1100 i = SCIx_MUX_IRQ;
1101 irq = up->irq;
1102 } else {
1103 irq = port->irqs[i];
1104
1105 /*
1106 * Certain port types won't support all of the
1107 * available interrupt sources.
1108 */
1109 if (unlikely(irq < 0))
1110 continue;
1111 }
1112
1113 desc = sci_irq_desc + i;
1114 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1115 dev_name(up->dev), desc->desc);
1116 if (!port->irqstr[j]) {
1117 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1118 desc->desc);
1119 goto out_nomem;
1120 }
1121
1122 ret = request_irq(irq, desc->handler, up->irqflags,
1123 port->irqstr[j], port);
1124 if (unlikely(ret)) {
1125 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1126 goto out_noirq;
1127 }
1128 }
1129
1130 return 0;
1131
1132 out_noirq:
1133 while (--i >= 0)
1134 free_irq(port->irqs[i], port);
1135
1136 out_nomem:
1137 while (--j >= 0)
1138 kfree(port->irqstr[j]);
1139
1140 return ret;
1141 }
1142
sci_free_irq(struct sci_port * port)1143 static void sci_free_irq(struct sci_port *port)
1144 {
1145 int i;
1146
1147 /*
1148 * Intentionally in reverse order so we iterate over the muxed
1149 * IRQ first.
1150 */
1151 for (i = 0; i < SCIx_NR_IRQS; i++) {
1152 int irq = port->irqs[i];
1153
1154 /*
1155 * Certain port types won't support all of the available
1156 * interrupt sources.
1157 */
1158 if (unlikely(irq < 0))
1159 continue;
1160
1161 free_irq(port->irqs[i], port);
1162 kfree(port->irqstr[i]);
1163
1164 if (SCIx_IRQ_IS_MUXED(port)) {
1165 /* If there's only one IRQ, we're done. */
1166 return;
1167 }
1168 }
1169 }
1170
sci_tx_empty(struct uart_port * port)1171 static unsigned int sci_tx_empty(struct uart_port *port)
1172 {
1173 unsigned short status = serial_port_in(port, SCxSR);
1174 unsigned short in_tx_fifo = sci_txfill(port);
1175
1176 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1177 }
1178
1179 /*
1180 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1181 * CTS/RTS is supported in hardware by at least one port and controlled
1182 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1183 * handled via the ->init_pins() op, which is a bit of a one-way street,
1184 * lacking any ability to defer pin control -- this will later be
1185 * converted over to the GPIO framework).
1186 *
1187 * Other modes (such as loopback) are supported generically on certain
1188 * port types, but not others. For these it's sufficient to test for the
1189 * existence of the support register and simply ignore the port type.
1190 */
sci_set_mctrl(struct uart_port * port,unsigned int mctrl)1191 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1192 {
1193 if (mctrl & TIOCM_LOOP) {
1194 struct plat_sci_reg *reg;
1195
1196 /*
1197 * Standard loopback mode for SCFCR ports.
1198 */
1199 reg = sci_getreg(port, SCFCR);
1200 if (reg->size)
1201 serial_port_out(port, SCFCR,
1202 serial_port_in(port, SCFCR) |
1203 SCFCR_LOOP);
1204 }
1205 }
1206
sci_get_mctrl(struct uart_port * port)1207 static unsigned int sci_get_mctrl(struct uart_port *port)
1208 {
1209 /*
1210 * CTS/RTS is handled in hardware when supported, while nothing
1211 * else is wired up. Keep it simple and simply assert DSR/CAR.
1212 */
1213 return TIOCM_DSR | TIOCM_CAR;
1214 }
1215
1216 #ifdef CONFIG_SERIAL_SH_SCI_DMA
sci_dma_tx_complete(void * arg)1217 static void sci_dma_tx_complete(void *arg)
1218 {
1219 struct sci_port *s = arg;
1220 struct uart_port *port = &s->port;
1221 struct circ_buf *xmit = &port->state->xmit;
1222 unsigned long flags;
1223
1224 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1225
1226 spin_lock_irqsave(&port->lock, flags);
1227
1228 xmit->tail += sg_dma_len(&s->sg_tx);
1229 xmit->tail &= UART_XMIT_SIZE - 1;
1230
1231 port->icount.tx += sg_dma_len(&s->sg_tx);
1232
1233 async_tx_ack(s->desc_tx);
1234 s->desc_tx = NULL;
1235
1236 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1237 uart_write_wakeup(port);
1238
1239 if (!uart_circ_empty(xmit)) {
1240 s->cookie_tx = 0;
1241 schedule_work(&s->work_tx);
1242 } else {
1243 s->cookie_tx = -EINVAL;
1244 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1245 u16 ctrl = serial_port_in(port, SCSCR);
1246 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1247 }
1248 }
1249
1250 spin_unlock_irqrestore(&port->lock, flags);
1251 }
1252
1253 /* Locking: called with port lock held */
sci_dma_rx_push(struct sci_port * s,size_t count)1254 static int sci_dma_rx_push(struct sci_port *s, size_t count)
1255 {
1256 struct uart_port *port = &s->port;
1257 struct tty_port *tport = &port->state->port;
1258 int i, active, room;
1259
1260 room = tty_buffer_request_room(tport, count);
1261
1262 if (s->active_rx == s->cookie_rx[0]) {
1263 active = 0;
1264 } else if (s->active_rx == s->cookie_rx[1]) {
1265 active = 1;
1266 } else {
1267 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1268 return 0;
1269 }
1270
1271 if (room < count)
1272 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1273 count - room);
1274 if (!room)
1275 return room;
1276
1277 for (i = 0; i < room; i++)
1278 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1279 TTY_NORMAL);
1280
1281 port->icount.rx += room;
1282
1283 return room;
1284 }
1285
sci_dma_rx_complete(void * arg)1286 static void sci_dma_rx_complete(void *arg)
1287 {
1288 struct sci_port *s = arg;
1289 struct uart_port *port = &s->port;
1290 unsigned long flags;
1291 int count;
1292
1293 dev_dbg(port->dev, "%s(%d) active #%d\n",
1294 __func__, port->line, s->active_rx);
1295
1296 spin_lock_irqsave(&port->lock, flags);
1297
1298 count = sci_dma_rx_push(s, s->buf_len_rx);
1299
1300 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1301
1302 spin_unlock_irqrestore(&port->lock, flags);
1303
1304 if (count)
1305 tty_flip_buffer_push(&port->state->port);
1306
1307 schedule_work(&s->work_rx);
1308 }
1309
sci_rx_dma_release(struct sci_port * s,bool enable_pio)1310 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1311 {
1312 struct dma_chan *chan = s->chan_rx;
1313 struct uart_port *port = &s->port;
1314
1315 s->chan_rx = NULL;
1316 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1317 dma_release_channel(chan);
1318 if (sg_dma_address(&s->sg_rx[0]))
1319 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1320 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1321 if (enable_pio)
1322 sci_start_rx(port);
1323 }
1324
sci_tx_dma_release(struct sci_port * s,bool enable_pio)1325 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1326 {
1327 struct dma_chan *chan = s->chan_tx;
1328 struct uart_port *port = &s->port;
1329
1330 s->chan_tx = NULL;
1331 s->cookie_tx = -EINVAL;
1332 dma_release_channel(chan);
1333 if (enable_pio)
1334 sci_start_tx(port);
1335 }
1336
sci_submit_rx(struct sci_port * s)1337 static void sci_submit_rx(struct sci_port *s)
1338 {
1339 struct dma_chan *chan = s->chan_rx;
1340 int i;
1341
1342 for (i = 0; i < 2; i++) {
1343 struct scatterlist *sg = &s->sg_rx[i];
1344 struct dma_async_tx_descriptor *desc;
1345
1346 desc = dmaengine_prep_slave_sg(chan,
1347 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1348
1349 if (desc) {
1350 s->desc_rx[i] = desc;
1351 desc->callback = sci_dma_rx_complete;
1352 desc->callback_param = s;
1353 s->cookie_rx[i] = desc->tx_submit(desc);
1354 }
1355
1356 if (!desc || s->cookie_rx[i] < 0) {
1357 if (i) {
1358 async_tx_ack(s->desc_rx[0]);
1359 s->cookie_rx[0] = -EINVAL;
1360 }
1361 if (desc) {
1362 async_tx_ack(desc);
1363 s->cookie_rx[i] = -EINVAL;
1364 }
1365 dev_warn(s->port.dev,
1366 "failed to re-start DMA, using PIO\n");
1367 sci_rx_dma_release(s, true);
1368 return;
1369 }
1370 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n",
1371 __func__, s->cookie_rx[i], i);
1372 }
1373
1374 s->active_rx = s->cookie_rx[0];
1375
1376 dma_async_issue_pending(chan);
1377 }
1378
work_fn_rx(struct work_struct * work)1379 static void work_fn_rx(struct work_struct *work)
1380 {
1381 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1382 struct uart_port *port = &s->port;
1383 struct dma_async_tx_descriptor *desc;
1384 int new;
1385
1386 if (s->active_rx == s->cookie_rx[0]) {
1387 new = 0;
1388 } else if (s->active_rx == s->cookie_rx[1]) {
1389 new = 1;
1390 } else {
1391 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1392 return;
1393 }
1394 desc = s->desc_rx[new];
1395
1396 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1397 DMA_COMPLETE) {
1398 /* Handle incomplete DMA receive */
1399 struct dma_chan *chan = s->chan_rx;
1400 struct shdma_desc *sh_desc = container_of(desc,
1401 struct shdma_desc, async_tx);
1402 unsigned long flags;
1403 int count;
1404
1405 dmaengine_terminate_all(chan);
1406 dev_dbg(port->dev, "Read %zu bytes with cookie %d\n",
1407 sh_desc->partial, sh_desc->cookie);
1408
1409 spin_lock_irqsave(&port->lock, flags);
1410 count = sci_dma_rx_push(s, sh_desc->partial);
1411 spin_unlock_irqrestore(&port->lock, flags);
1412
1413 if (count)
1414 tty_flip_buffer_push(&port->state->port);
1415
1416 sci_submit_rx(s);
1417
1418 return;
1419 }
1420
1421 s->cookie_rx[new] = desc->tx_submit(desc);
1422 if (s->cookie_rx[new] < 0) {
1423 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1424 sci_rx_dma_release(s, true);
1425 return;
1426 }
1427
1428 s->active_rx = s->cookie_rx[!new];
1429
1430 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n",
1431 __func__, s->cookie_rx[new], new, s->active_rx);
1432 }
1433
work_fn_tx(struct work_struct * work)1434 static void work_fn_tx(struct work_struct *work)
1435 {
1436 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1437 struct dma_async_tx_descriptor *desc;
1438 struct dma_chan *chan = s->chan_tx;
1439 struct uart_port *port = &s->port;
1440 struct circ_buf *xmit = &port->state->xmit;
1441 struct scatterlist *sg = &s->sg_tx;
1442
1443 /*
1444 * DMA is idle now.
1445 * Port xmit buffer is already mapped, and it is one page... Just adjust
1446 * offsets and lengths. Since it is a circular buffer, we have to
1447 * transmit till the end, and then the rest. Take the port lock to get a
1448 * consistent xmit buffer state.
1449 */
1450 spin_lock_irq(&port->lock);
1451 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
1452 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
1453 sg->offset;
1454 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1455 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1456 spin_unlock_irq(&port->lock);
1457
1458 BUG_ON(!sg_dma_len(sg));
1459
1460 desc = dmaengine_prep_slave_sg(chan,
1461 sg, s->sg_len_tx, DMA_MEM_TO_DEV,
1462 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1463 if (!desc) {
1464 /* switch to PIO */
1465 sci_tx_dma_release(s, true);
1466 return;
1467 }
1468
1469 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1470
1471 spin_lock_irq(&port->lock);
1472 s->desc_tx = desc;
1473 desc->callback = sci_dma_tx_complete;
1474 desc->callback_param = s;
1475 spin_unlock_irq(&port->lock);
1476 s->cookie_tx = desc->tx_submit(desc);
1477 if (s->cookie_tx < 0) {
1478 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1479 /* switch to PIO */
1480 sci_tx_dma_release(s, true);
1481 return;
1482 }
1483
1484 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1485 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1486
1487 dma_async_issue_pending(chan);
1488 }
1489 #endif
1490
sci_start_tx(struct uart_port * port)1491 static void sci_start_tx(struct uart_port *port)
1492 {
1493 struct sci_port *s = to_sci_port(port);
1494 unsigned short ctrl;
1495
1496 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1497 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1498 u16 new, scr = serial_port_in(port, SCSCR);
1499 if (s->chan_tx)
1500 new = scr | SCSCR_TDRQE;
1501 else
1502 new = scr & ~SCSCR_TDRQE;
1503 if (new != scr)
1504 serial_port_out(port, SCSCR, new);
1505 }
1506
1507 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1508 s->cookie_tx < 0) {
1509 s->cookie_tx = 0;
1510 schedule_work(&s->work_tx);
1511 }
1512 #endif
1513
1514 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1515 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1516 ctrl = serial_port_in(port, SCSCR);
1517 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
1518 }
1519 }
1520
sci_stop_tx(struct uart_port * port)1521 static void sci_stop_tx(struct uart_port *port)
1522 {
1523 unsigned short ctrl;
1524
1525 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1526 ctrl = serial_port_in(port, SCSCR);
1527
1528 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1529 ctrl &= ~SCSCR_TDRQE;
1530
1531 ctrl &= ~SCSCR_TIE;
1532
1533 serial_port_out(port, SCSCR, ctrl);
1534 }
1535
sci_start_rx(struct uart_port * port)1536 static void sci_start_rx(struct uart_port *port)
1537 {
1538 unsigned short ctrl;
1539
1540 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1541
1542 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1543 ctrl &= ~SCSCR_RDRQE;
1544
1545 serial_port_out(port, SCSCR, ctrl);
1546 }
1547
sci_stop_rx(struct uart_port * port)1548 static void sci_stop_rx(struct uart_port *port)
1549 {
1550 unsigned short ctrl;
1551
1552 ctrl = serial_port_in(port, SCSCR);
1553
1554 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1555 ctrl &= ~SCSCR_RDRQE;
1556
1557 ctrl &= ~port_rx_irq_mask(port);
1558
1559 serial_port_out(port, SCSCR, ctrl);
1560 }
1561
sci_break_ctl(struct uart_port * port,int break_state)1562 static void sci_break_ctl(struct uart_port *port, int break_state)
1563 {
1564 struct sci_port *s = to_sci_port(port);
1565 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1566 unsigned short scscr, scsptr;
1567
1568 /* check wheter the port has SCSPTR */
1569 if (!reg->size) {
1570 /*
1571 * Not supported by hardware. Most parts couple break and rx
1572 * interrupts together, with break detection always enabled.
1573 */
1574 return;
1575 }
1576
1577 scsptr = serial_port_in(port, SCSPTR);
1578 scscr = serial_port_in(port, SCSCR);
1579
1580 if (break_state == -1) {
1581 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1582 scscr &= ~SCSCR_TE;
1583 } else {
1584 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1585 scscr |= SCSCR_TE;
1586 }
1587
1588 serial_port_out(port, SCSPTR, scsptr);
1589 serial_port_out(port, SCSCR, scscr);
1590 }
1591
1592 #ifdef CONFIG_SERIAL_SH_SCI_DMA
filter(struct dma_chan * chan,void * slave)1593 static bool filter(struct dma_chan *chan, void *slave)
1594 {
1595 struct sh_dmae_slave *param = slave;
1596
1597 dev_dbg(chan->device->dev, "%s: slave ID %d\n",
1598 __func__, param->shdma_slave.slave_id);
1599
1600 chan->private = ¶m->shdma_slave;
1601 return true;
1602 }
1603
rx_timer_fn(unsigned long arg)1604 static void rx_timer_fn(unsigned long arg)
1605 {
1606 struct sci_port *s = (struct sci_port *)arg;
1607 struct uart_port *port = &s->port;
1608 u16 scr = serial_port_in(port, SCSCR);
1609
1610 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1611 scr &= ~SCSCR_RDRQE;
1612 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1613 }
1614 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1615 dev_dbg(port->dev, "DMA Rx timed out\n");
1616 schedule_work(&s->work_rx);
1617 }
1618
sci_request_dma(struct uart_port * port)1619 static void sci_request_dma(struct uart_port *port)
1620 {
1621 struct sci_port *s = to_sci_port(port);
1622 struct sh_dmae_slave *param;
1623 struct dma_chan *chan;
1624 dma_cap_mask_t mask;
1625 int nent;
1626
1627 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1628
1629 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
1630 return;
1631
1632 dma_cap_zero(mask);
1633 dma_cap_set(DMA_SLAVE, mask);
1634
1635 param = &s->param_tx;
1636
1637 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1638 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
1639
1640 s->cookie_tx = -EINVAL;
1641 chan = dma_request_channel(mask, filter, param);
1642 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1643 if (chan) {
1644 s->chan_tx = chan;
1645 sg_init_table(&s->sg_tx, 1);
1646 /* UART circular tx buffer is an aligned page. */
1647 BUG_ON((uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
1648 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1649 UART_XMIT_SIZE,
1650 (uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
1651 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1652 if (!nent)
1653 sci_tx_dma_release(s, false);
1654 else
1655 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n",
1656 __func__,
1657 sg_dma_len(&s->sg_tx), port->state->xmit.buf,
1658 &sg_dma_address(&s->sg_tx));
1659
1660 s->sg_len_tx = nent;
1661
1662 INIT_WORK(&s->work_tx, work_fn_tx);
1663 }
1664
1665 param = &s->param_rx;
1666
1667 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1668 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
1669
1670 chan = dma_request_channel(mask, filter, param);
1671 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1672 if (chan) {
1673 dma_addr_t dma[2];
1674 void *buf[2];
1675 int i;
1676
1677 s->chan_rx = chan;
1678
1679 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1680 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1681 &dma[0], GFP_KERNEL);
1682
1683 if (!buf[0]) {
1684 dev_warn(port->dev,
1685 "failed to allocate dma buffer, using PIO\n");
1686 sci_rx_dma_release(s, true);
1687 return;
1688 }
1689
1690 buf[1] = buf[0] + s->buf_len_rx;
1691 dma[1] = dma[0] + s->buf_len_rx;
1692
1693 for (i = 0; i < 2; i++) {
1694 struct scatterlist *sg = &s->sg_rx[i];
1695
1696 sg_init_table(sg, 1);
1697 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1698 (uintptr_t)buf[i] & ~PAGE_MASK);
1699 sg_dma_address(sg) = dma[i];
1700 }
1701
1702 INIT_WORK(&s->work_rx, work_fn_rx);
1703 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1704
1705 sci_submit_rx(s);
1706 }
1707 }
1708
sci_free_dma(struct uart_port * port)1709 static void sci_free_dma(struct uart_port *port)
1710 {
1711 struct sci_port *s = to_sci_port(port);
1712
1713 if (s->chan_tx)
1714 sci_tx_dma_release(s, false);
1715 if (s->chan_rx)
1716 sci_rx_dma_release(s, false);
1717 }
1718 #else
sci_request_dma(struct uart_port * port)1719 static inline void sci_request_dma(struct uart_port *port)
1720 {
1721 }
1722
sci_free_dma(struct uart_port * port)1723 static inline void sci_free_dma(struct uart_port *port)
1724 {
1725 }
1726 #endif
1727
sci_startup(struct uart_port * port)1728 static int sci_startup(struct uart_port *port)
1729 {
1730 struct sci_port *s = to_sci_port(port);
1731 unsigned long flags;
1732 int ret;
1733
1734 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1735
1736 sci_request_dma(port);
1737
1738 ret = sci_request_irq(s);
1739 if (unlikely(ret < 0)) {
1740 sci_free_dma(port);
1741 return ret;
1742 }
1743
1744 spin_lock_irqsave(&port->lock, flags);
1745 sci_start_tx(port);
1746 sci_start_rx(port);
1747 spin_unlock_irqrestore(&port->lock, flags);
1748
1749 return 0;
1750 }
1751
sci_shutdown(struct uart_port * port)1752 static void sci_shutdown(struct uart_port *port)
1753 {
1754 struct sci_port *s = to_sci_port(port);
1755 unsigned long flags;
1756
1757 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1758
1759 spin_lock_irqsave(&port->lock, flags);
1760 sci_stop_rx(port);
1761 sci_stop_tx(port);
1762 spin_unlock_irqrestore(&port->lock, flags);
1763
1764 sci_free_irq(s);
1765 sci_free_dma(port);
1766 }
1767
sci_scbrr_calc(struct sci_port * s,unsigned int bps,unsigned long freq)1768 static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1769 unsigned long freq)
1770 {
1771 if (s->sampling_rate)
1772 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1773
1774 /* Warn, but use a safe default */
1775 WARN_ON(1);
1776
1777 return ((freq + 16 * bps) / (32 * bps) - 1);
1778 }
1779
1780 /* calculate frame length from SMR */
sci_baud_calc_frame_len(unsigned int smr_val)1781 static int sci_baud_calc_frame_len(unsigned int smr_val)
1782 {
1783 int len = 10;
1784
1785 if (smr_val & SCSMR_CHR)
1786 len--;
1787 if (smr_val & SCSMR_PE)
1788 len++;
1789 if (smr_val & SCSMR_STOP)
1790 len++;
1791
1792 return len;
1793 }
1794
1795
1796 /* calculate sample rate, BRR, and clock select for HSCIF */
sci_baud_calc_hscif(unsigned int bps,unsigned long freq,int * brr,unsigned int * srr,unsigned int * cks,int frame_len)1797 static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1798 int *brr, unsigned int *srr,
1799 unsigned int *cks, int frame_len)
1800 {
1801 int sr, c, br, err, recv_margin;
1802 int min_err = 1000; /* 100% */
1803 int recv_max_margin = 0;
1804
1805 /* Find the combination of sample rate and clock select with the
1806 smallest deviation from the desired baud rate. */
1807 for (sr = 8; sr <= 32; sr++) {
1808 for (c = 0; c <= 3; c++) {
1809 /* integerized formulas from HSCIF documentation */
1810 br = DIV_ROUND_CLOSEST(freq, (sr *
1811 (1 << (2 * c + 1)) * bps)) - 1;
1812 br = clamp(br, 0, 255);
1813 err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr *
1814 (1 << (2 * c + 1)) / 1000)) -
1815 1000;
1816 if (err < 0)
1817 continue;
1818
1819 /* Calc recv margin
1820 * M: Receive margin (%)
1821 * N: Ratio of bit rate to clock (N = sampling rate)
1822 * D: Clock duty (D = 0 to 1.0)
1823 * L: Frame length (L = 9 to 12)
1824 * F: Absolute value of clock frequency deviation
1825 *
1826 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1827 * (|D - 0.5| / N * (1 + F))|
1828 * NOTE: Usually, treat D for 0.5, F is 0 by this
1829 * calculation.
1830 */
1831 recv_margin = abs((500 -
1832 DIV_ROUND_CLOSEST(1000, sr << 1)) / 10);
1833 if (min_err > err) {
1834 min_err = err;
1835 recv_max_margin = recv_margin;
1836 } else if ((min_err == err) &&
1837 (recv_margin > recv_max_margin))
1838 recv_max_margin = recv_margin;
1839 else
1840 continue;
1841
1842 *brr = br;
1843 *srr = sr - 1;
1844 *cks = c;
1845 }
1846 }
1847
1848 if (min_err == 1000) {
1849 WARN_ON(1);
1850 /* use defaults */
1851 *brr = 255;
1852 *srr = 15;
1853 *cks = 0;
1854 }
1855 }
1856
sci_reset(struct uart_port * port)1857 static void sci_reset(struct uart_port *port)
1858 {
1859 struct plat_sci_reg *reg;
1860 unsigned int status;
1861
1862 do {
1863 status = serial_port_in(port, SCxSR);
1864 } while (!(status & SCxSR_TEND(port)));
1865
1866 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1867
1868 reg = sci_getreg(port, SCFCR);
1869 if (reg->size)
1870 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1871 }
1872
sci_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)1873 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1874 struct ktermios *old)
1875 {
1876 struct sci_port *s = to_sci_port(port);
1877 struct plat_sci_reg *reg;
1878 unsigned int baud, smr_val = 0, max_baud, cks = 0;
1879 int t = -1;
1880 unsigned int srr = 15;
1881
1882 if ((termios->c_cflag & CSIZE) == CS7)
1883 smr_val |= SCSMR_CHR;
1884 if (termios->c_cflag & PARENB)
1885 smr_val |= SCSMR_PE;
1886 if (termios->c_cflag & PARODD)
1887 smr_val |= SCSMR_PE | SCSMR_ODD;
1888 if (termios->c_cflag & CSTOPB)
1889 smr_val |= SCSMR_STOP;
1890
1891 /*
1892 * earlyprintk comes here early on with port->uartclk set to zero.
1893 * the clock framework is not up and running at this point so here
1894 * we assume that 115200 is the maximum baud rate. please note that
1895 * the baud rate is not programmed during earlyprintk - it is assumed
1896 * that the previous boot loader has enabled required clocks and
1897 * setup the baud rate generator hardware for us already.
1898 */
1899 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1900
1901 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1902 if (likely(baud && port->uartclk)) {
1903 if (s->cfg->type == PORT_HSCIF) {
1904 int frame_len = sci_baud_calc_frame_len(smr_val);
1905 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
1906 &cks, frame_len);
1907 } else {
1908 t = sci_scbrr_calc(s, baud, port->uartclk);
1909 for (cks = 0; t >= 256 && cks <= 3; cks++)
1910 t >>= 2;
1911 }
1912 }
1913
1914 sci_port_enable(s);
1915
1916 sci_reset(port);
1917
1918 smr_val |= serial_port_in(port, SCSMR) & 3;
1919
1920 uart_update_timeout(port, termios->c_cflag, baud);
1921
1922 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1923 __func__, smr_val, cks, t, s->cfg->scscr);
1924
1925 if (t >= 0) {
1926 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
1927 serial_port_out(port, SCBRR, t);
1928 reg = sci_getreg(port, HSSRR);
1929 if (reg->size)
1930 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1931 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1932 } else
1933 serial_port_out(port, SCSMR, smr_val);
1934
1935 sci_init_pins(port, termios->c_cflag);
1936
1937 reg = sci_getreg(port, SCFCR);
1938 if (reg->size) {
1939 unsigned short ctrl = serial_port_in(port, SCFCR);
1940
1941 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
1942 if (termios->c_cflag & CRTSCTS)
1943 ctrl |= SCFCR_MCE;
1944 else
1945 ctrl &= ~SCFCR_MCE;
1946 }
1947
1948 /*
1949 * As we've done a sci_reset() above, ensure we don't
1950 * interfere with the FIFOs while toggling MCE. As the
1951 * reset values could still be set, simply mask them out.
1952 */
1953 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
1954
1955 serial_port_out(port, SCFCR, ctrl);
1956 }
1957
1958 serial_port_out(port, SCSCR, s->cfg->scscr);
1959
1960 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1961 /*
1962 * Calculate delay for 1.5 DMA buffers: see
1963 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1964 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1965 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1966 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1967 * sizes), but it has been found out experimentally, that this is not
1968 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1969 * as a minimum seem to work perfectly.
1970 */
1971 if (s->chan_rx) {
1972 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1973 port->fifosize / 2;
1974 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1975 s->rx_timeout * 1000 / HZ, port->timeout);
1976 if (s->rx_timeout < msecs_to_jiffies(20))
1977 s->rx_timeout = msecs_to_jiffies(20);
1978 }
1979 #endif
1980
1981 if ((termios->c_cflag & CREAD) != 0)
1982 sci_start_rx(port);
1983
1984 sci_port_disable(s);
1985 }
1986
sci_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)1987 static void sci_pm(struct uart_port *port, unsigned int state,
1988 unsigned int oldstate)
1989 {
1990 struct sci_port *sci_port = to_sci_port(port);
1991
1992 switch (state) {
1993 case UART_PM_STATE_OFF:
1994 sci_port_disable(sci_port);
1995 break;
1996 default:
1997 sci_port_enable(sci_port);
1998 break;
1999 }
2000 }
2001
sci_type(struct uart_port * port)2002 static const char *sci_type(struct uart_port *port)
2003 {
2004 switch (port->type) {
2005 case PORT_IRDA:
2006 return "irda";
2007 case PORT_SCI:
2008 return "sci";
2009 case PORT_SCIF:
2010 return "scif";
2011 case PORT_SCIFA:
2012 return "scifa";
2013 case PORT_SCIFB:
2014 return "scifb";
2015 case PORT_HSCIF:
2016 return "hscif";
2017 }
2018
2019 return NULL;
2020 }
2021
sci_port_size(struct uart_port * port)2022 static inline unsigned long sci_port_size(struct uart_port *port)
2023 {
2024 /*
2025 * Pick an arbitrary size that encapsulates all of the base
2026 * registers by default. This can be optimized later, or derived
2027 * from platform resource data at such a time that ports begin to
2028 * behave more erratically.
2029 */
2030 if (port->type == PORT_HSCIF)
2031 return 96;
2032 else
2033 return 64;
2034 }
2035
sci_remap_port(struct uart_port * port)2036 static int sci_remap_port(struct uart_port *port)
2037 {
2038 unsigned long size = sci_port_size(port);
2039
2040 /*
2041 * Nothing to do if there's already an established membase.
2042 */
2043 if (port->membase)
2044 return 0;
2045
2046 if (port->flags & UPF_IOREMAP) {
2047 port->membase = ioremap_nocache(port->mapbase, size);
2048 if (unlikely(!port->membase)) {
2049 dev_err(port->dev, "can't remap port#%d\n", port->line);
2050 return -ENXIO;
2051 }
2052 } else {
2053 /*
2054 * For the simple (and majority of) cases where we don't
2055 * need to do any remapping, just cast the cookie
2056 * directly.
2057 */
2058 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2059 }
2060
2061 return 0;
2062 }
2063
sci_release_port(struct uart_port * port)2064 static void sci_release_port(struct uart_port *port)
2065 {
2066 if (port->flags & UPF_IOREMAP) {
2067 iounmap(port->membase);
2068 port->membase = NULL;
2069 }
2070
2071 release_mem_region(port->mapbase, sci_port_size(port));
2072 }
2073
sci_request_port(struct uart_port * port)2074 static int sci_request_port(struct uart_port *port)
2075 {
2076 unsigned long size = sci_port_size(port);
2077 struct resource *res;
2078 int ret;
2079
2080 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
2081 if (unlikely(res == NULL))
2082 return -EBUSY;
2083
2084 ret = sci_remap_port(port);
2085 if (unlikely(ret != 0)) {
2086 release_resource(res);
2087 return ret;
2088 }
2089
2090 return 0;
2091 }
2092
sci_config_port(struct uart_port * port,int flags)2093 static void sci_config_port(struct uart_port *port, int flags)
2094 {
2095 if (flags & UART_CONFIG_TYPE) {
2096 struct sci_port *sport = to_sci_port(port);
2097
2098 port->type = sport->cfg->type;
2099 sci_request_port(port);
2100 }
2101 }
2102
sci_verify_port(struct uart_port * port,struct serial_struct * ser)2103 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2104 {
2105 if (ser->baud_base < 2400)
2106 /* No paper tape reader for Mitch.. */
2107 return -EINVAL;
2108
2109 return 0;
2110 }
2111
2112 static struct uart_ops sci_uart_ops = {
2113 .tx_empty = sci_tx_empty,
2114 .set_mctrl = sci_set_mctrl,
2115 .get_mctrl = sci_get_mctrl,
2116 .start_tx = sci_start_tx,
2117 .stop_tx = sci_stop_tx,
2118 .stop_rx = sci_stop_rx,
2119 .break_ctl = sci_break_ctl,
2120 .startup = sci_startup,
2121 .shutdown = sci_shutdown,
2122 .set_termios = sci_set_termios,
2123 .pm = sci_pm,
2124 .type = sci_type,
2125 .release_port = sci_release_port,
2126 .request_port = sci_request_port,
2127 .config_port = sci_config_port,
2128 .verify_port = sci_verify_port,
2129 #ifdef CONFIG_CONSOLE_POLL
2130 .poll_get_char = sci_poll_get_char,
2131 .poll_put_char = sci_poll_put_char,
2132 #endif
2133 };
2134
sci_init_single(struct platform_device * dev,struct sci_port * sci_port,unsigned int index,struct plat_sci_port * p,bool early)2135 static int sci_init_single(struct platform_device *dev,
2136 struct sci_port *sci_port, unsigned int index,
2137 struct plat_sci_port *p, bool early)
2138 {
2139 struct uart_port *port = &sci_port->port;
2140 const struct resource *res;
2141 unsigned int sampling_rate;
2142 unsigned int i;
2143 int ret;
2144
2145 sci_port->cfg = p;
2146
2147 port->ops = &sci_uart_ops;
2148 port->iotype = UPIO_MEM;
2149 port->line = index;
2150
2151 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2152 if (res == NULL)
2153 return -ENOMEM;
2154
2155 port->mapbase = res->start;
2156
2157 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2158 sci_port->irqs[i] = platform_get_irq(dev, i);
2159
2160 /* The SCI generates several interrupts. They can be muxed together or
2161 * connected to different interrupt lines. In the muxed case only one
2162 * interrupt resource is specified. In the non-muxed case three or four
2163 * interrupt resources are specified, as the BRI interrupt is optional.
2164 */
2165 if (sci_port->irqs[0] < 0)
2166 return -ENXIO;
2167
2168 if (sci_port->irqs[1] < 0) {
2169 sci_port->irqs[1] = sci_port->irqs[0];
2170 sci_port->irqs[2] = sci_port->irqs[0];
2171 sci_port->irqs[3] = sci_port->irqs[0];
2172 }
2173
2174 if (p->regtype == SCIx_PROBE_REGTYPE) {
2175 ret = sci_probe_regmap(p);
2176 if (unlikely(ret))
2177 return ret;
2178 }
2179
2180 switch (p->type) {
2181 case PORT_SCIFB:
2182 port->fifosize = 256;
2183 sci_port->overrun_bit = 9;
2184 sampling_rate = 16;
2185 break;
2186 case PORT_HSCIF:
2187 port->fifosize = 128;
2188 sampling_rate = 0;
2189 sci_port->overrun_bit = 0;
2190 break;
2191 case PORT_SCIFA:
2192 port->fifosize = 64;
2193 sci_port->overrun_bit = 9;
2194 sampling_rate = 16;
2195 break;
2196 case PORT_SCIF:
2197 port->fifosize = 16;
2198 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2199 sci_port->overrun_bit = 9;
2200 sampling_rate = 16;
2201 } else {
2202 sci_port->overrun_bit = 0;
2203 sampling_rate = 32;
2204 }
2205 break;
2206 default:
2207 port->fifosize = 1;
2208 sci_port->overrun_bit = 5;
2209 sampling_rate = 32;
2210 break;
2211 }
2212
2213 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2214 * match the SoC datasheet, this should be investigated. Let platform
2215 * data override the sampling rate for now.
2216 */
2217 sci_port->sampling_rate = p->sampling_rate ? p->sampling_rate
2218 : sampling_rate;
2219
2220 if (!early) {
2221 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2222 if (IS_ERR(sci_port->iclk)) {
2223 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2224 if (IS_ERR(sci_port->iclk)) {
2225 dev_err(&dev->dev, "can't get iclk\n");
2226 return PTR_ERR(sci_port->iclk);
2227 }
2228 }
2229
2230 /*
2231 * The function clock is optional, ignore it if we can't
2232 * find it.
2233 */
2234 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2235 if (IS_ERR(sci_port->fclk))
2236 sci_port->fclk = NULL;
2237
2238 port->dev = &dev->dev;
2239
2240 pm_runtime_enable(&dev->dev);
2241 }
2242
2243 sci_port->break_timer.data = (unsigned long)sci_port;
2244 sci_port->break_timer.function = sci_break_timer;
2245 init_timer(&sci_port->break_timer);
2246
2247 /*
2248 * Establish some sensible defaults for the error detection.
2249 */
2250 sci_port->error_mask = (p->type == PORT_SCI) ?
2251 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
2252
2253 /*
2254 * Establish sensible defaults for the overrun detection, unless
2255 * the part has explicitly disabled support for it.
2256 */
2257
2258 /*
2259 * Make the error mask inclusive of overrun detection, if
2260 * supported.
2261 */
2262 sci_port->error_mask |= 1 << sci_port->overrun_bit;
2263
2264 port->type = p->type;
2265 port->flags = UPF_FIXED_PORT | p->flags;
2266 port->regshift = p->regshift;
2267
2268 /*
2269 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2270 * for the multi-IRQ ports, which is where we are primarily
2271 * concerned with the shutdown path synchronization.
2272 *
2273 * For the muxed case there's nothing more to do.
2274 */
2275 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2276 port->irqflags = 0;
2277
2278 port->serial_in = sci_serial_in;
2279 port->serial_out = sci_serial_out;
2280
2281 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2282 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2283 p->dma_slave_tx, p->dma_slave_rx);
2284
2285 return 0;
2286 }
2287
sci_cleanup_single(struct sci_port * port)2288 static void sci_cleanup_single(struct sci_port *port)
2289 {
2290 clk_put(port->iclk);
2291 clk_put(port->fclk);
2292
2293 pm_runtime_disable(port->port.dev);
2294 }
2295
2296 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
serial_console_putchar(struct uart_port * port,int ch)2297 static void serial_console_putchar(struct uart_port *port, int ch)
2298 {
2299 sci_poll_put_char(port, ch);
2300 }
2301
2302 /*
2303 * Print a string to the serial port trying not to disturb
2304 * any possible real use of the port...
2305 */
serial_console_write(struct console * co,const char * s,unsigned count)2306 static void serial_console_write(struct console *co, const char *s,
2307 unsigned count)
2308 {
2309 struct sci_port *sci_port = &sci_ports[co->index];
2310 struct uart_port *port = &sci_port->port;
2311 unsigned short bits, ctrl;
2312 unsigned long flags;
2313 int locked = 1;
2314
2315 local_irq_save(flags);
2316 if (port->sysrq)
2317 locked = 0;
2318 else if (oops_in_progress)
2319 locked = spin_trylock(&port->lock);
2320 else
2321 spin_lock(&port->lock);
2322
2323 /* first save the SCSCR then disable the interrupts */
2324 ctrl = serial_port_in(port, SCSCR);
2325 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
2326
2327 uart_console_write(port, s, count, serial_console_putchar);
2328
2329 /* wait until fifo is empty and last bit has been transmitted */
2330 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2331 while ((serial_port_in(port, SCxSR) & bits) != bits)
2332 cpu_relax();
2333
2334 /* restore the SCSCR */
2335 serial_port_out(port, SCSCR, ctrl);
2336
2337 if (locked)
2338 spin_unlock(&port->lock);
2339 local_irq_restore(flags);
2340 }
2341
serial_console_setup(struct console * co,char * options)2342 static int serial_console_setup(struct console *co, char *options)
2343 {
2344 struct sci_port *sci_port;
2345 struct uart_port *port;
2346 int baud = 115200;
2347 int bits = 8;
2348 int parity = 'n';
2349 int flow = 'n';
2350 int ret;
2351
2352 /*
2353 * Refuse to handle any bogus ports.
2354 */
2355 if (co->index < 0 || co->index >= SCI_NPORTS)
2356 return -ENODEV;
2357
2358 sci_port = &sci_ports[co->index];
2359 port = &sci_port->port;
2360
2361 /*
2362 * Refuse to handle uninitialized ports.
2363 */
2364 if (!port->ops)
2365 return -ENODEV;
2366
2367 ret = sci_remap_port(port);
2368 if (unlikely(ret != 0))
2369 return ret;
2370
2371 if (options)
2372 uart_parse_options(options, &baud, &parity, &bits, &flow);
2373
2374 return uart_set_options(port, co, baud, parity, bits, flow);
2375 }
2376
2377 static struct console serial_console = {
2378 .name = "ttySC",
2379 .device = uart_console_device,
2380 .write = serial_console_write,
2381 .setup = serial_console_setup,
2382 .flags = CON_PRINTBUFFER,
2383 .index = -1,
2384 .data = &sci_uart_driver,
2385 };
2386
2387 static struct console early_serial_console = {
2388 .name = "early_ttySC",
2389 .write = serial_console_write,
2390 .flags = CON_PRINTBUFFER,
2391 .index = -1,
2392 };
2393
2394 static char early_serial_buf[32];
2395
sci_probe_earlyprintk(struct platform_device * pdev)2396 static int sci_probe_earlyprintk(struct platform_device *pdev)
2397 {
2398 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2399
2400 if (early_serial_console.data)
2401 return -EEXIST;
2402
2403 early_serial_console.index = pdev->id;
2404
2405 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2406
2407 serial_console_setup(&early_serial_console, early_serial_buf);
2408
2409 if (!strstr(early_serial_buf, "keep"))
2410 early_serial_console.flags |= CON_BOOT;
2411
2412 register_console(&early_serial_console);
2413 return 0;
2414 }
2415
2416 #define SCI_CONSOLE (&serial_console)
2417
2418 #else
sci_probe_earlyprintk(struct platform_device * pdev)2419 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2420 {
2421 return -EINVAL;
2422 }
2423
2424 #define SCI_CONSOLE NULL
2425
2426 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2427
2428 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2429
2430 static struct uart_driver sci_uart_driver = {
2431 .owner = THIS_MODULE,
2432 .driver_name = "sci",
2433 .dev_name = "ttySC",
2434 .major = SCI_MAJOR,
2435 .minor = SCI_MINOR_START,
2436 .nr = SCI_NPORTS,
2437 .cons = SCI_CONSOLE,
2438 };
2439
sci_remove(struct platform_device * dev)2440 static int sci_remove(struct platform_device *dev)
2441 {
2442 struct sci_port *port = platform_get_drvdata(dev);
2443
2444 cpufreq_unregister_notifier(&port->freq_transition,
2445 CPUFREQ_TRANSITION_NOTIFIER);
2446
2447 uart_remove_one_port(&sci_uart_driver, &port->port);
2448
2449 sci_cleanup_single(port);
2450
2451 return 0;
2452 }
2453
2454 struct sci_port_info {
2455 unsigned int type;
2456 unsigned int regtype;
2457 };
2458
2459 static const struct of_device_id of_sci_match[] = {
2460 {
2461 .compatible = "renesas,scif",
2462 .data = &(const struct sci_port_info) {
2463 .type = PORT_SCIF,
2464 .regtype = SCIx_SH4_SCIF_REGTYPE,
2465 },
2466 }, {
2467 .compatible = "renesas,scifa",
2468 .data = &(const struct sci_port_info) {
2469 .type = PORT_SCIFA,
2470 .regtype = SCIx_SCIFA_REGTYPE,
2471 },
2472 }, {
2473 .compatible = "renesas,scifb",
2474 .data = &(const struct sci_port_info) {
2475 .type = PORT_SCIFB,
2476 .regtype = SCIx_SCIFB_REGTYPE,
2477 },
2478 }, {
2479 .compatible = "renesas,hscif",
2480 .data = &(const struct sci_port_info) {
2481 .type = PORT_HSCIF,
2482 .regtype = SCIx_HSCIF_REGTYPE,
2483 },
2484 }, {
2485 /* Terminator */
2486 },
2487 };
2488 MODULE_DEVICE_TABLE(of, of_sci_match);
2489
2490 static struct plat_sci_port *
sci_parse_dt(struct platform_device * pdev,unsigned int * dev_id)2491 sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2492 {
2493 struct device_node *np = pdev->dev.of_node;
2494 const struct of_device_id *match;
2495 const struct sci_port_info *info;
2496 struct plat_sci_port *p;
2497 int id;
2498
2499 if (!IS_ENABLED(CONFIG_OF) || !np)
2500 return NULL;
2501
2502 match = of_match_node(of_sci_match, pdev->dev.of_node);
2503 if (!match)
2504 return NULL;
2505
2506 info = match->data;
2507
2508 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2509 if (!p) {
2510 dev_err(&pdev->dev, "failed to allocate DT config data\n");
2511 return NULL;
2512 }
2513
2514 /* Get the line number for the aliases node. */
2515 id = of_alias_get_id(np, "serial");
2516 if (id < 0) {
2517 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2518 return NULL;
2519 }
2520
2521 *dev_id = id;
2522
2523 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2524 p->type = info->type;
2525 p->regtype = info->regtype;
2526 p->scscr = SCSCR_RE | SCSCR_TE;
2527
2528 return p;
2529 }
2530
sci_probe_single(struct platform_device * dev,unsigned int index,struct plat_sci_port * p,struct sci_port * sciport)2531 static int sci_probe_single(struct platform_device *dev,
2532 unsigned int index,
2533 struct plat_sci_port *p,
2534 struct sci_port *sciport)
2535 {
2536 int ret;
2537
2538 /* Sanity check */
2539 if (unlikely(index >= SCI_NPORTS)) {
2540 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
2541 index+1, SCI_NPORTS);
2542 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2543 return -EINVAL;
2544 }
2545
2546 ret = sci_init_single(dev, sciport, index, p, false);
2547 if (ret)
2548 return ret;
2549
2550 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2551 if (ret) {
2552 sci_cleanup_single(sciport);
2553 return ret;
2554 }
2555
2556 return 0;
2557 }
2558
sci_probe(struct platform_device * dev)2559 static int sci_probe(struct platform_device *dev)
2560 {
2561 struct plat_sci_port *p;
2562 struct sci_port *sp;
2563 unsigned int dev_id;
2564 int ret;
2565
2566 /*
2567 * If we've come here via earlyprintk initialization, head off to
2568 * the special early probe. We don't have sufficient device state
2569 * to make it beyond this yet.
2570 */
2571 if (is_early_platform_device(dev))
2572 return sci_probe_earlyprintk(dev);
2573
2574 if (dev->dev.of_node) {
2575 p = sci_parse_dt(dev, &dev_id);
2576 if (p == NULL)
2577 return -EINVAL;
2578 } else {
2579 p = dev->dev.platform_data;
2580 if (p == NULL) {
2581 dev_err(&dev->dev, "no platform data supplied\n");
2582 return -EINVAL;
2583 }
2584
2585 dev_id = dev->id;
2586 }
2587
2588 sp = &sci_ports[dev_id];
2589 platform_set_drvdata(dev, sp);
2590
2591 ret = sci_probe_single(dev, dev_id, p, sp);
2592 if (ret)
2593 return ret;
2594
2595 sp->freq_transition.notifier_call = sci_notifier;
2596
2597 ret = cpufreq_register_notifier(&sp->freq_transition,
2598 CPUFREQ_TRANSITION_NOTIFIER);
2599 if (unlikely(ret < 0)) {
2600 uart_remove_one_port(&sci_uart_driver, &sp->port);
2601 sci_cleanup_single(sp);
2602 return ret;
2603 }
2604
2605 #ifdef CONFIG_SH_STANDARD_BIOS
2606 sh_bios_gdb_detach();
2607 #endif
2608
2609 return 0;
2610 }
2611
sci_suspend(struct device * dev)2612 static int sci_suspend(struct device *dev)
2613 {
2614 struct sci_port *sport = dev_get_drvdata(dev);
2615
2616 if (sport)
2617 uart_suspend_port(&sci_uart_driver, &sport->port);
2618
2619 return 0;
2620 }
2621
sci_resume(struct device * dev)2622 static int sci_resume(struct device *dev)
2623 {
2624 struct sci_port *sport = dev_get_drvdata(dev);
2625
2626 if (sport)
2627 uart_resume_port(&sci_uart_driver, &sport->port);
2628
2629 return 0;
2630 }
2631
2632 static const struct dev_pm_ops sci_dev_pm_ops = {
2633 .suspend = sci_suspend,
2634 .resume = sci_resume,
2635 };
2636
2637 static struct platform_driver sci_driver = {
2638 .probe = sci_probe,
2639 .remove = sci_remove,
2640 .driver = {
2641 .name = "sh-sci",
2642 .owner = THIS_MODULE,
2643 .pm = &sci_dev_pm_ops,
2644 .of_match_table = of_match_ptr(of_sci_match),
2645 },
2646 };
2647
sci_init(void)2648 static int __init sci_init(void)
2649 {
2650 int ret;
2651
2652 pr_info("%s\n", banner);
2653
2654 ret = uart_register_driver(&sci_uart_driver);
2655 if (likely(ret == 0)) {
2656 ret = platform_driver_register(&sci_driver);
2657 if (unlikely(ret))
2658 uart_unregister_driver(&sci_uart_driver);
2659 }
2660
2661 return ret;
2662 }
2663
sci_exit(void)2664 static void __exit sci_exit(void)
2665 {
2666 platform_driver_unregister(&sci_driver);
2667 uart_unregister_driver(&sci_uart_driver);
2668 }
2669
2670 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2671 early_platform_init_buffer("earlyprintk", &sci_driver,
2672 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2673 #endif
2674 module_init(sci_init);
2675 module_exit(sci_exit);
2676
2677 MODULE_LICENSE("GPL");
2678 MODULE_ALIAS("platform:sh-sci");
2679 MODULE_AUTHOR("Paul Mundt");
2680 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
2681