1 /*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23
24 #include <linux/slab.h>
25 #include <asm/unaligned.h>
26
27 #include "xhci.h"
28 #include "xhci-trace.h"
29
30 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
32 PORT_RC | PORT_PLC | PORT_PE)
33
34 /* USB 3.0 BOS descriptor and a capability descriptor, combined */
35 static u8 usb_bos_descriptor [] = {
36 USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
37 USB_DT_BOS, /* __u8 bDescriptorType */
38 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
39 0x1, /* __u8 bNumDeviceCaps */
40 /* First device capability */
41 USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
42 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
43 USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
44 0x00, /* bmAttributes, LTM off by default */
45 USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
46 0x03, /* bFunctionalitySupport,
47 USB 3.0 speed only */
48 0x00, /* bU1DevExitLat, set later. */
49 0x00, 0x00 /* __le16 bU2DevExitLat, set later. */
50 };
51
52
xhci_common_hub_descriptor(struct xhci_hcd * xhci,struct usb_hub_descriptor * desc,int ports)53 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
54 struct usb_hub_descriptor *desc, int ports)
55 {
56 u16 temp;
57
58 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
59 desc->bHubContrCurrent = 0;
60
61 desc->bNbrPorts = ports;
62 temp = 0;
63 /* Bits 1:0 - support per-port power switching, or power always on */
64 if (HCC_PPC(xhci->hcc_params))
65 temp |= HUB_CHAR_INDV_PORT_LPSM;
66 else
67 temp |= HUB_CHAR_NO_LPSM;
68 /* Bit 2 - root hubs are not part of a compound device */
69 /* Bits 4:3 - individual port over current protection */
70 temp |= HUB_CHAR_INDV_PORT_OCPM;
71 /* Bits 6:5 - no TTs in root ports */
72 /* Bit 7 - no port indicators */
73 desc->wHubCharacteristics = cpu_to_le16(temp);
74 }
75
76 /* Fill in the USB 2.0 roothub descriptor */
xhci_usb2_hub_descriptor(struct usb_hcd * hcd,struct xhci_hcd * xhci,struct usb_hub_descriptor * desc)77 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
78 struct usb_hub_descriptor *desc)
79 {
80 int ports;
81 u16 temp;
82 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
83 u32 portsc;
84 unsigned int i;
85
86 ports = xhci->num_usb2_ports;
87
88 xhci_common_hub_descriptor(xhci, desc, ports);
89 desc->bDescriptorType = USB_DT_HUB;
90 temp = 1 + (ports / 8);
91 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
92
93 /* The Device Removable bits are reported on a byte granularity.
94 * If the port doesn't exist within that byte, the bit is set to 0.
95 */
96 memset(port_removable, 0, sizeof(port_removable));
97 for (i = 0; i < ports; i++) {
98 portsc = readl(xhci->usb2_ports[i]);
99 /* If a device is removable, PORTSC reports a 0, same as in the
100 * hub descriptor DeviceRemovable bits.
101 */
102 if (portsc & PORT_DEV_REMOVE)
103 /* This math is hairy because bit 0 of DeviceRemovable
104 * is reserved, and bit 1 is for port 1, etc.
105 */
106 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
107 }
108
109 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
110 * ports on it. The USB 2.0 specification says that there are two
111 * variable length fields at the end of the hub descriptor:
112 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
113 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
114 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
115 * 0xFF, so we initialize the both arrays (DeviceRemovable and
116 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
117 * set of ports that actually exist.
118 */
119 memset(desc->u.hs.DeviceRemovable, 0xff,
120 sizeof(desc->u.hs.DeviceRemovable));
121 memset(desc->u.hs.PortPwrCtrlMask, 0xff,
122 sizeof(desc->u.hs.PortPwrCtrlMask));
123
124 for (i = 0; i < (ports + 1 + 7) / 8; i++)
125 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
126 sizeof(__u8));
127 }
128
129 /* Fill in the USB 3.0 roothub descriptor */
xhci_usb3_hub_descriptor(struct usb_hcd * hcd,struct xhci_hcd * xhci,struct usb_hub_descriptor * desc)130 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
131 struct usb_hub_descriptor *desc)
132 {
133 int ports;
134 u16 port_removable;
135 u32 portsc;
136 unsigned int i;
137
138 ports = xhci->num_usb3_ports;
139 xhci_common_hub_descriptor(xhci, desc, ports);
140 desc->bDescriptorType = USB_DT_SS_HUB;
141 desc->bDescLength = USB_DT_SS_HUB_SIZE;
142
143 /* header decode latency should be zero for roothubs,
144 * see section 4.23.5.2.
145 */
146 desc->u.ss.bHubHdrDecLat = 0;
147 desc->u.ss.wHubDelay = 0;
148
149 port_removable = 0;
150 /* bit 0 is reserved, bit 1 is for port 1, etc. */
151 for (i = 0; i < ports; i++) {
152 portsc = readl(xhci->usb3_ports[i]);
153 if (portsc & PORT_DEV_REMOVE)
154 port_removable |= 1 << (i + 1);
155 }
156
157 desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
158 }
159
xhci_hub_descriptor(struct usb_hcd * hcd,struct xhci_hcd * xhci,struct usb_hub_descriptor * desc)160 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
161 struct usb_hub_descriptor *desc)
162 {
163
164 if (hcd->speed == HCD_USB3)
165 xhci_usb3_hub_descriptor(hcd, xhci, desc);
166 else
167 xhci_usb2_hub_descriptor(hcd, xhci, desc);
168
169 }
170
xhci_port_speed(unsigned int port_status)171 static unsigned int xhci_port_speed(unsigned int port_status)
172 {
173 if (DEV_LOWSPEED(port_status))
174 return USB_PORT_STAT_LOW_SPEED;
175 if (DEV_HIGHSPEED(port_status))
176 return USB_PORT_STAT_HIGH_SPEED;
177 /*
178 * FIXME: Yes, we should check for full speed, but the core uses that as
179 * a default in portspeed() in usb/core/hub.c (which is the only place
180 * USB_PORT_STAT_*_SPEED is used).
181 */
182 return 0;
183 }
184
185 /*
186 * These bits are Read Only (RO) and should be saved and written to the
187 * registers: 0, 3, 10:13, 30
188 * connect status, over-current status, port speed, and device removable.
189 * connect status and port speed are also sticky - meaning they're in
190 * the AUX well and they aren't changed by a hot, warm, or cold reset.
191 */
192 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
193 /*
194 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
195 * bits 5:8, 9, 14:15, 25:27
196 * link state, port power, port indicator state, "wake on" enable state
197 */
198 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
199 /*
200 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
201 * bit 4 (port reset)
202 */
203 #define XHCI_PORT_RW1S ((1<<4))
204 /*
205 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
206 * bits 1, 17, 18, 19, 20, 21, 22, 23
207 * port enable/disable, and
208 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
209 * over-current, reset, link state, and L1 change
210 */
211 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
212 /*
213 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
214 * latched in
215 */
216 #define XHCI_PORT_RW ((1<<16))
217 /*
218 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
219 * bits 2, 24, 28:31
220 */
221 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
222
223 /*
224 * Given a port state, this function returns a value that would result in the
225 * port being in the same state, if the value was written to the port status
226 * control register.
227 * Save Read Only (RO) bits and save read/write bits where
228 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
229 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
230 */
xhci_port_state_to_neutral(u32 state)231 u32 xhci_port_state_to_neutral(u32 state)
232 {
233 /* Save read-only status and port state */
234 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
235 }
236
237 /*
238 * find slot id based on port number.
239 * @port: The one-based port number from one of the two split roothubs.
240 */
xhci_find_slot_id_by_port(struct usb_hcd * hcd,struct xhci_hcd * xhci,u16 port)241 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
242 u16 port)
243 {
244 int slot_id;
245 int i;
246 enum usb_device_speed speed;
247
248 slot_id = 0;
249 for (i = 0; i < MAX_HC_SLOTS; i++) {
250 if (!xhci->devs[i])
251 continue;
252 speed = xhci->devs[i]->udev->speed;
253 if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3))
254 && xhci->devs[i]->fake_port == port) {
255 slot_id = i;
256 break;
257 }
258 }
259
260 return slot_id;
261 }
262
263 /*
264 * Stop device
265 * It issues stop endpoint command for EP 0 to 30. And wait the last command
266 * to complete.
267 * suspend will set to 1, if suspend bit need to set in command.
268 */
xhci_stop_device(struct xhci_hcd * xhci,int slot_id,int suspend)269 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
270 {
271 struct xhci_virt_device *virt_dev;
272 struct xhci_command *cmd;
273 unsigned long flags;
274 int ret;
275 int i;
276
277 ret = 0;
278 virt_dev = xhci->devs[slot_id];
279 if (!virt_dev)
280 return -ENODEV;
281
282 cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
283 if (!cmd) {
284 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
285 return -ENOMEM;
286 }
287
288 spin_lock_irqsave(&xhci->lock, flags);
289 for (i = LAST_EP_INDEX; i > 0; i--) {
290 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
291 struct xhci_command *command;
292 command = xhci_alloc_command(xhci, false, false,
293 GFP_NOWAIT);
294 if (!command) {
295 spin_unlock_irqrestore(&xhci->lock, flags);
296 ret = -ENOMEM;
297 goto cmd_cleanup;
298 }
299
300 ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
301 i, suspend);
302 if (ret) {
303 spin_unlock_irqrestore(&xhci->lock, flags);
304 xhci_free_command(xhci, command);
305 goto cmd_cleanup;
306 }
307 }
308 }
309 ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
310 if (ret) {
311 spin_unlock_irqrestore(&xhci->lock, flags);
312 goto cmd_cleanup;
313 }
314
315 xhci_ring_cmd_db(xhci);
316 spin_unlock_irqrestore(&xhci->lock, flags);
317
318 /* Wait for last stop endpoint command to finish */
319 wait_for_completion(cmd->completion);
320
321 if (cmd->status == COMP_CMD_ABORT || cmd->status == COMP_CMD_STOP) {
322 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
323 ret = -ETIME;
324 }
325
326 cmd_cleanup:
327 xhci_free_command(xhci, cmd);
328 return ret;
329 }
330
331 /*
332 * Ring device, it rings the all doorbells unconditionally.
333 */
xhci_ring_device(struct xhci_hcd * xhci,int slot_id)334 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
335 {
336 int i, s;
337 struct xhci_virt_ep *ep;
338
339 for (i = 0; i < LAST_EP_INDEX + 1; i++) {
340 ep = &xhci->devs[slot_id]->eps[i];
341
342 if (ep->ep_state & EP_HAS_STREAMS) {
343 for (s = 1; s < ep->stream_info->num_streams; s++)
344 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
345 } else if (ep->ring && ep->ring->dequeue) {
346 xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
347 }
348 }
349
350 return;
351 }
352
xhci_disable_port(struct usb_hcd * hcd,struct xhci_hcd * xhci,u16 wIndex,__le32 __iomem * addr,u32 port_status)353 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
354 u16 wIndex, __le32 __iomem *addr, u32 port_status)
355 {
356 /* Don't allow the USB core to disable SuperSpeed ports. */
357 if (hcd->speed == HCD_USB3) {
358 xhci_dbg(xhci, "Ignoring request to disable "
359 "SuperSpeed port.\n");
360 return;
361 }
362
363 /* Write 1 to disable the port */
364 writel(port_status | PORT_PE, addr);
365 port_status = readl(addr);
366 xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n",
367 wIndex, port_status);
368 }
369
xhci_clear_port_change_bit(struct xhci_hcd * xhci,u16 wValue,u16 wIndex,__le32 __iomem * addr,u32 port_status)370 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
371 u16 wIndex, __le32 __iomem *addr, u32 port_status)
372 {
373 char *port_change_bit;
374 u32 status;
375
376 switch (wValue) {
377 case USB_PORT_FEAT_C_RESET:
378 status = PORT_RC;
379 port_change_bit = "reset";
380 break;
381 case USB_PORT_FEAT_C_BH_PORT_RESET:
382 status = PORT_WRC;
383 port_change_bit = "warm(BH) reset";
384 break;
385 case USB_PORT_FEAT_C_CONNECTION:
386 status = PORT_CSC;
387 port_change_bit = "connect";
388 break;
389 case USB_PORT_FEAT_C_OVER_CURRENT:
390 status = PORT_OCC;
391 port_change_bit = "over-current";
392 break;
393 case USB_PORT_FEAT_C_ENABLE:
394 status = PORT_PEC;
395 port_change_bit = "enable/disable";
396 break;
397 case USB_PORT_FEAT_C_SUSPEND:
398 status = PORT_PLC;
399 port_change_bit = "suspend/resume";
400 break;
401 case USB_PORT_FEAT_C_PORT_LINK_STATE:
402 status = PORT_PLC;
403 port_change_bit = "link state";
404 break;
405 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
406 status = PORT_CEC;
407 port_change_bit = "config error";
408 break;
409 default:
410 /* Should never happen */
411 return;
412 }
413 /* Change bits are all write 1 to clear */
414 writel(port_status | status, addr);
415 port_status = readl(addr);
416 xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
417 port_change_bit, wIndex, port_status);
418 }
419
xhci_get_ports(struct usb_hcd * hcd,__le32 __iomem *** port_array)420 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
421 {
422 int max_ports;
423 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
424
425 if (hcd->speed == HCD_USB3) {
426 max_ports = xhci->num_usb3_ports;
427 *port_array = xhci->usb3_ports;
428 } else {
429 max_ports = xhci->num_usb2_ports;
430 *port_array = xhci->usb2_ports;
431 }
432
433 return max_ports;
434 }
435
xhci_set_link_state(struct xhci_hcd * xhci,__le32 __iomem ** port_array,int port_id,u32 link_state)436 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
437 int port_id, u32 link_state)
438 {
439 u32 temp;
440
441 temp = readl(port_array[port_id]);
442 temp = xhci_port_state_to_neutral(temp);
443 temp &= ~PORT_PLS_MASK;
444 temp |= PORT_LINK_STROBE | link_state;
445 writel(temp, port_array[port_id]);
446 }
447
xhci_set_remote_wake_mask(struct xhci_hcd * xhci,__le32 __iomem ** port_array,int port_id,u16 wake_mask)448 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
449 __le32 __iomem **port_array, int port_id, u16 wake_mask)
450 {
451 u32 temp;
452
453 temp = readl(port_array[port_id]);
454 temp = xhci_port_state_to_neutral(temp);
455
456 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
457 temp |= PORT_WKCONN_E;
458 else
459 temp &= ~PORT_WKCONN_E;
460
461 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
462 temp |= PORT_WKDISC_E;
463 else
464 temp &= ~PORT_WKDISC_E;
465
466 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
467 temp |= PORT_WKOC_E;
468 else
469 temp &= ~PORT_WKOC_E;
470
471 writel(temp, port_array[port_id]);
472 }
473
474 /* Test and clear port RWC bit */
xhci_test_and_clear_bit(struct xhci_hcd * xhci,__le32 __iomem ** port_array,int port_id,u32 port_bit)475 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
476 int port_id, u32 port_bit)
477 {
478 u32 temp;
479
480 temp = readl(port_array[port_id]);
481 if (temp & port_bit) {
482 temp = xhci_port_state_to_neutral(temp);
483 temp |= port_bit;
484 writel(temp, port_array[port_id]);
485 }
486 }
487
488 /* Updates Link Status for USB 2.1 port */
xhci_hub_report_usb2_link_state(u32 * status,u32 status_reg)489 static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
490 {
491 if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
492 *status |= USB_PORT_STAT_L1;
493 }
494
495 /* Updates Link Status for super Speed port */
xhci_hub_report_usb3_link_state(struct xhci_hcd * xhci,u32 * status,u32 status_reg)496 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
497 u32 *status, u32 status_reg)
498 {
499 u32 pls = status_reg & PORT_PLS_MASK;
500
501 /* resume state is a xHCI internal state.
502 * Do not report it to usb core, instead, pretend to be U3,
503 * thus usb core knows it's not ready for transfer
504 */
505 if (pls == XDEV_RESUME) {
506 *status |= USB_SS_PORT_LS_U3;
507 return;
508 }
509
510 /* When the CAS bit is set then warm reset
511 * should be performed on port
512 */
513 if (status_reg & PORT_CAS) {
514 /* The CAS bit can be set while the port is
515 * in any link state.
516 * Only roothubs have CAS bit, so we
517 * pretend to be in compliance mode
518 * unless we're already in compliance
519 * or the inactive state.
520 */
521 if (pls != USB_SS_PORT_LS_COMP_MOD &&
522 pls != USB_SS_PORT_LS_SS_INACTIVE) {
523 pls = USB_SS_PORT_LS_COMP_MOD;
524 }
525 /* Return also connection bit -
526 * hub state machine resets port
527 * when this bit is set.
528 */
529 pls |= USB_PORT_STAT_CONNECTION;
530 } else {
531 /*
532 * If CAS bit isn't set but the Port is already at
533 * Compliance Mode, fake a connection so the USB core
534 * notices the Compliance state and resets the port.
535 * This resolves an issue generated by the SN65LVPE502CP
536 * in which sometimes the port enters compliance mode
537 * caused by a delay on the host-device negotiation.
538 */
539 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
540 (pls == USB_SS_PORT_LS_COMP_MOD))
541 pls |= USB_PORT_STAT_CONNECTION;
542 }
543
544 /* update status field */
545 *status |= pls;
546 }
547
548 /*
549 * Function for Compliance Mode Quirk.
550 *
551 * This Function verifies if all xhc USB3 ports have entered U0, if so,
552 * the compliance mode timer is deleted. A port won't enter
553 * compliance mode if it has previously entered U0.
554 */
xhci_del_comp_mod_timer(struct xhci_hcd * xhci,u32 status,u16 wIndex)555 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
556 u16 wIndex)
557 {
558 u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
559 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
560
561 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
562 return;
563
564 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
565 xhci->port_status_u0 |= 1 << wIndex;
566 if (xhci->port_status_u0 == all_ports_seen_u0) {
567 del_timer_sync(&xhci->comp_mode_recovery_timer);
568 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
569 "All USB3 ports have entered U0 already!");
570 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
571 "Compliance Mode Recovery Timer Deleted.");
572 }
573 }
574 }
575
576 /*
577 * Converts a raw xHCI port status into the format that external USB 2.0 or USB
578 * 3.0 hubs use.
579 *
580 * Possible side effects:
581 * - Mark a port as being done with device resume,
582 * and ring the endpoint doorbells.
583 * - Stop the Synopsys redriver Compliance Mode polling.
584 * - Drop and reacquire the xHCI lock, in order to wait for port resume.
585 */
xhci_get_port_status(struct usb_hcd * hcd,struct xhci_bus_state * bus_state,__le32 __iomem ** port_array,u16 wIndex,u32 raw_port_status,unsigned long flags)586 static u32 xhci_get_port_status(struct usb_hcd *hcd,
587 struct xhci_bus_state *bus_state,
588 __le32 __iomem **port_array,
589 u16 wIndex, u32 raw_port_status,
590 unsigned long flags)
591 __releases(&xhci->lock)
592 __acquires(&xhci->lock)
593 {
594 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
595 u32 status = 0;
596 int slot_id;
597
598 /* wPortChange bits */
599 if (raw_port_status & PORT_CSC)
600 status |= USB_PORT_STAT_C_CONNECTION << 16;
601 if (raw_port_status & PORT_PEC)
602 status |= USB_PORT_STAT_C_ENABLE << 16;
603 if ((raw_port_status & PORT_OCC))
604 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
605 if ((raw_port_status & PORT_RC))
606 status |= USB_PORT_STAT_C_RESET << 16;
607 /* USB3.0 only */
608 if (hcd->speed == HCD_USB3) {
609 /* Port link change with port in resume state should not be
610 * reported to usbcore, as this is an internal state to be
611 * handled by xhci driver. Reporting PLC to usbcore may
612 * cause usbcore clearing PLC first and port change event
613 * irq won't be generated.
614 */
615 if ((raw_port_status & PORT_PLC) &&
616 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME)
617 status |= USB_PORT_STAT_C_LINK_STATE << 16;
618 if ((raw_port_status & PORT_WRC))
619 status |= USB_PORT_STAT_C_BH_RESET << 16;
620 if ((raw_port_status & PORT_CEC))
621 status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
622 }
623
624 if (hcd->speed != HCD_USB3) {
625 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
626 && (raw_port_status & PORT_POWER))
627 status |= USB_PORT_STAT_SUSPEND;
628 }
629 if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
630 !DEV_SUPERSPEED(raw_port_status)) {
631 if ((raw_port_status & PORT_RESET) ||
632 !(raw_port_status & PORT_PE))
633 return 0xffffffff;
634 /* did port event handler already start resume timing? */
635 if (!bus_state->resume_done[wIndex]) {
636 /* If not, maybe we are in a host initated resume? */
637 if (test_bit(wIndex, &bus_state->resuming_ports)) {
638 /* Host initated resume doesn't time the resume
639 * signalling using resume_done[].
640 * It manually sets RESUME state, sleeps 20ms
641 * and sets U0 state. This should probably be
642 * changed, but not right now.
643 */
644 } else {
645 /* port resume was discovered now and here,
646 * start resume timing
647 */
648 unsigned long timeout = jiffies +
649 msecs_to_jiffies(USB_RESUME_TIMEOUT);
650
651 set_bit(wIndex, &bus_state->resuming_ports);
652 bus_state->resume_done[wIndex] = timeout;
653 mod_timer(&hcd->rh_timer, timeout);
654 }
655 /* Has resume been signalled for USB_RESUME_TIME yet? */
656 } else if (time_after_eq(jiffies,
657 bus_state->resume_done[wIndex])) {
658 int time_left;
659
660 xhci_dbg(xhci, "Resume USB2 port %d\n",
661 wIndex + 1);
662 bus_state->resume_done[wIndex] = 0;
663 clear_bit(wIndex, &bus_state->resuming_ports);
664
665 set_bit(wIndex, &bus_state->rexit_ports);
666
667 xhci_test_and_clear_bit(xhci, port_array, wIndex,
668 PORT_PLC);
669 xhci_set_link_state(xhci, port_array, wIndex,
670 XDEV_U0);
671
672 spin_unlock_irqrestore(&xhci->lock, flags);
673 time_left = wait_for_completion_timeout(
674 &bus_state->rexit_done[wIndex],
675 msecs_to_jiffies(
676 XHCI_MAX_REXIT_TIMEOUT));
677 spin_lock_irqsave(&xhci->lock, flags);
678
679 if (time_left) {
680 slot_id = xhci_find_slot_id_by_port(hcd,
681 xhci, wIndex + 1);
682 if (!slot_id) {
683 xhci_dbg(xhci, "slot_id is zero\n");
684 return 0xffffffff;
685 }
686 xhci_ring_device(xhci, slot_id);
687 } else {
688 int port_status = readl(port_array[wIndex]);
689 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
690 XHCI_MAX_REXIT_TIMEOUT,
691 port_status);
692 status |= USB_PORT_STAT_SUSPEND;
693 clear_bit(wIndex, &bus_state->rexit_ports);
694 }
695
696 bus_state->port_c_suspend |= 1 << wIndex;
697 bus_state->suspended_ports &= ~(1 << wIndex);
698 } else {
699 /*
700 * The resume has been signaling for less than
701 * USB_RESUME_TIME. Report the port status as SUSPEND,
702 * let the usbcore check port status again and clear
703 * resume signaling later.
704 */
705 status |= USB_PORT_STAT_SUSPEND;
706 }
707 }
708 /*
709 * Clear stale usb2 resume signalling variables in case port changed
710 * state during resume signalling. For example on error
711 */
712 if ((bus_state->resume_done[wIndex] ||
713 test_bit(wIndex, &bus_state->resuming_ports)) &&
714 (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
715 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
716 bus_state->resume_done[wIndex] = 0;
717 clear_bit(wIndex, &bus_state->resuming_ports);
718 }
719 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0
720 && (raw_port_status & PORT_POWER)
721 && (bus_state->suspended_ports & (1 << wIndex))) {
722 bus_state->suspended_ports &= ~(1 << wIndex);
723 if (hcd->speed != HCD_USB3)
724 bus_state->port_c_suspend |= 1 << wIndex;
725 }
726 if (raw_port_status & PORT_CONNECT) {
727 status |= USB_PORT_STAT_CONNECTION;
728 status |= xhci_port_speed(raw_port_status);
729 }
730 if (raw_port_status & PORT_PE)
731 status |= USB_PORT_STAT_ENABLE;
732 if (raw_port_status & PORT_OC)
733 status |= USB_PORT_STAT_OVERCURRENT;
734 if (raw_port_status & PORT_RESET)
735 status |= USB_PORT_STAT_RESET;
736 if (raw_port_status & PORT_POWER) {
737 if (hcd->speed == HCD_USB3)
738 status |= USB_SS_PORT_STAT_POWER;
739 else
740 status |= USB_PORT_STAT_POWER;
741 }
742 /* Update Port Link State */
743 if (hcd->speed == HCD_USB3) {
744 xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status);
745 /*
746 * Verify if all USB3 Ports Have entered U0 already.
747 * Delete Compliance Mode Timer if so.
748 */
749 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
750 } else {
751 xhci_hub_report_usb2_link_state(&status, raw_port_status);
752 }
753 if (bus_state->port_c_suspend & (1 << wIndex))
754 status |= 1 << USB_PORT_FEAT_C_SUSPEND;
755
756 return status;
757 }
758
xhci_hub_control(struct usb_hcd * hcd,u16 typeReq,u16 wValue,u16 wIndex,char * buf,u16 wLength)759 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
760 u16 wIndex, char *buf, u16 wLength)
761 {
762 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
763 int max_ports;
764 unsigned long flags;
765 u32 temp, status;
766 int retval = 0;
767 __le32 __iomem **port_array;
768 int slot_id;
769 struct xhci_bus_state *bus_state;
770 u16 link_state = 0;
771 u16 wake_mask = 0;
772 u16 timeout = 0;
773
774 max_ports = xhci_get_ports(hcd, &port_array);
775 bus_state = &xhci->bus_state[hcd_index(hcd)];
776
777 spin_lock_irqsave(&xhci->lock, flags);
778 switch (typeReq) {
779 case GetHubStatus:
780 /* No power source, over-current reported per port */
781 memset(buf, 0, 4);
782 break;
783 case GetHubDescriptor:
784 /* Check to make sure userspace is asking for the USB 3.0 hub
785 * descriptor for the USB 3.0 roothub. If not, we stall the
786 * endpoint, like external hubs do.
787 */
788 if (hcd->speed == HCD_USB3 &&
789 (wLength < USB_DT_SS_HUB_SIZE ||
790 wValue != (USB_DT_SS_HUB << 8))) {
791 xhci_dbg(xhci, "Wrong hub descriptor type for "
792 "USB 3.0 roothub.\n");
793 goto error;
794 }
795 xhci_hub_descriptor(hcd, xhci,
796 (struct usb_hub_descriptor *) buf);
797 break;
798 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
799 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
800 goto error;
801
802 if (hcd->speed != HCD_USB3)
803 goto error;
804
805 /* Set the U1 and U2 exit latencies. */
806 memcpy(buf, &usb_bos_descriptor,
807 USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE);
808 if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
809 temp = readl(&xhci->cap_regs->hcs_params3);
810 buf[12] = HCS_U1_LATENCY(temp);
811 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
812 }
813
814 /* Indicate whether the host has LTM support. */
815 temp = readl(&xhci->cap_regs->hcc_params);
816 if (HCC_LTC(temp))
817 buf[8] |= USB_LTM_SUPPORT;
818
819 spin_unlock_irqrestore(&xhci->lock, flags);
820 return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
821 case GetPortStatus:
822 if (!wIndex || wIndex > max_ports)
823 goto error;
824 wIndex--;
825 temp = readl(port_array[wIndex]);
826 if (temp == 0xffffffff) {
827 retval = -ENODEV;
828 break;
829 }
830 status = xhci_get_port_status(hcd, bus_state, port_array,
831 wIndex, temp, flags);
832 if (status == 0xffffffff)
833 goto error;
834
835 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n",
836 wIndex, temp);
837 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
838
839 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
840 break;
841 case SetPortFeature:
842 if (wValue == USB_PORT_FEAT_LINK_STATE)
843 link_state = (wIndex & 0xff00) >> 3;
844 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
845 wake_mask = wIndex & 0xff00;
846 /* The MSB of wIndex is the U1/U2 timeout */
847 timeout = (wIndex & 0xff00) >> 8;
848 wIndex &= 0xff;
849 if (!wIndex || wIndex > max_ports)
850 goto error;
851 wIndex--;
852 temp = readl(port_array[wIndex]);
853 if (temp == 0xffffffff) {
854 retval = -ENODEV;
855 break;
856 }
857 temp = xhci_port_state_to_neutral(temp);
858 /* FIXME: What new port features do we need to support? */
859 switch (wValue) {
860 case USB_PORT_FEAT_SUSPEND:
861 temp = readl(port_array[wIndex]);
862 if ((temp & PORT_PLS_MASK) != XDEV_U0) {
863 /* Resume the port to U0 first */
864 xhci_set_link_state(xhci, port_array, wIndex,
865 XDEV_U0);
866 spin_unlock_irqrestore(&xhci->lock, flags);
867 msleep(10);
868 spin_lock_irqsave(&xhci->lock, flags);
869 }
870 /* In spec software should not attempt to suspend
871 * a port unless the port reports that it is in the
872 * enabled (PED = ‘1’,PLS < ‘3’) state.
873 */
874 temp = readl(port_array[wIndex]);
875 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
876 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
877 xhci_warn(xhci, "USB core suspending device "
878 "not in U0/U1/U2.\n");
879 goto error;
880 }
881
882 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
883 wIndex + 1);
884 if (!slot_id) {
885 xhci_warn(xhci, "slot_id is zero\n");
886 goto error;
887 }
888 /* unlock to execute stop endpoint commands */
889 spin_unlock_irqrestore(&xhci->lock, flags);
890 xhci_stop_device(xhci, slot_id, 1);
891 spin_lock_irqsave(&xhci->lock, flags);
892
893 xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
894
895 spin_unlock_irqrestore(&xhci->lock, flags);
896 msleep(10); /* wait device to enter */
897 spin_lock_irqsave(&xhci->lock, flags);
898
899 temp = readl(port_array[wIndex]);
900 bus_state->suspended_ports |= 1 << wIndex;
901 break;
902 case USB_PORT_FEAT_LINK_STATE:
903 temp = readl(port_array[wIndex]);
904
905 /* Disable port */
906 if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
907 xhci_dbg(xhci, "Disable port %d\n", wIndex);
908 temp = xhci_port_state_to_neutral(temp);
909 /*
910 * Clear all change bits, so that we get a new
911 * connection event.
912 */
913 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
914 PORT_OCC | PORT_RC | PORT_PLC |
915 PORT_CEC;
916 writel(temp | PORT_PE, port_array[wIndex]);
917 temp = readl(port_array[wIndex]);
918 break;
919 }
920
921 /* Put link in RxDetect (enable port) */
922 if (link_state == USB_SS_PORT_LS_RX_DETECT) {
923 xhci_dbg(xhci, "Enable port %d\n", wIndex);
924 xhci_set_link_state(xhci, port_array, wIndex,
925 link_state);
926 temp = readl(port_array[wIndex]);
927 break;
928 }
929
930 /* Software should not attempt to set
931 * port link state above '3' (U3) and the port
932 * must be enabled.
933 */
934 if ((temp & PORT_PE) == 0 ||
935 (link_state > USB_SS_PORT_LS_U3)) {
936 xhci_warn(xhci, "Cannot set link state.\n");
937 goto error;
938 }
939
940 if (link_state == USB_SS_PORT_LS_U3) {
941 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
942 wIndex + 1);
943 if (slot_id) {
944 /* unlock to execute stop endpoint
945 * commands */
946 spin_unlock_irqrestore(&xhci->lock,
947 flags);
948 xhci_stop_device(xhci, slot_id, 1);
949 spin_lock_irqsave(&xhci->lock, flags);
950 }
951 }
952
953 xhci_set_link_state(xhci, port_array, wIndex,
954 link_state);
955
956 spin_unlock_irqrestore(&xhci->lock, flags);
957 msleep(20); /* wait device to enter */
958 spin_lock_irqsave(&xhci->lock, flags);
959
960 temp = readl(port_array[wIndex]);
961 if (link_state == USB_SS_PORT_LS_U3)
962 bus_state->suspended_ports |= 1 << wIndex;
963 break;
964 case USB_PORT_FEAT_POWER:
965 /*
966 * Turn on ports, even if there isn't per-port switching.
967 * HC will report connect events even before this is set.
968 * However, hub_wq will ignore the roothub events until
969 * the roothub is registered.
970 */
971 writel(temp | PORT_POWER, port_array[wIndex]);
972
973 temp = readl(port_array[wIndex]);
974 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp);
975
976 spin_unlock_irqrestore(&xhci->lock, flags);
977 temp = usb_acpi_power_manageable(hcd->self.root_hub,
978 wIndex);
979 if (temp)
980 usb_acpi_set_power_state(hcd->self.root_hub,
981 wIndex, true);
982 spin_lock_irqsave(&xhci->lock, flags);
983 break;
984 case USB_PORT_FEAT_RESET:
985 temp = (temp | PORT_RESET);
986 writel(temp, port_array[wIndex]);
987
988 temp = readl(port_array[wIndex]);
989 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
990 break;
991 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
992 xhci_set_remote_wake_mask(xhci, port_array,
993 wIndex, wake_mask);
994 temp = readl(port_array[wIndex]);
995 xhci_dbg(xhci, "set port remote wake mask, "
996 "actual port %d status = 0x%x\n",
997 wIndex, temp);
998 break;
999 case USB_PORT_FEAT_BH_PORT_RESET:
1000 temp |= PORT_WR;
1001 writel(temp, port_array[wIndex]);
1002
1003 temp = readl(port_array[wIndex]);
1004 break;
1005 case USB_PORT_FEAT_U1_TIMEOUT:
1006 if (hcd->speed != HCD_USB3)
1007 goto error;
1008 temp = readl(port_array[wIndex] + PORTPMSC);
1009 temp &= ~PORT_U1_TIMEOUT_MASK;
1010 temp |= PORT_U1_TIMEOUT(timeout);
1011 writel(temp, port_array[wIndex] + PORTPMSC);
1012 break;
1013 case USB_PORT_FEAT_U2_TIMEOUT:
1014 if (hcd->speed != HCD_USB3)
1015 goto error;
1016 temp = readl(port_array[wIndex] + PORTPMSC);
1017 temp &= ~PORT_U2_TIMEOUT_MASK;
1018 temp |= PORT_U2_TIMEOUT(timeout);
1019 writel(temp, port_array[wIndex] + PORTPMSC);
1020 break;
1021 default:
1022 goto error;
1023 }
1024 /* unblock any posted writes */
1025 temp = readl(port_array[wIndex]);
1026 break;
1027 case ClearPortFeature:
1028 if (!wIndex || wIndex > max_ports)
1029 goto error;
1030 wIndex--;
1031 temp = readl(port_array[wIndex]);
1032 if (temp == 0xffffffff) {
1033 retval = -ENODEV;
1034 break;
1035 }
1036 /* FIXME: What new port features do we need to support? */
1037 temp = xhci_port_state_to_neutral(temp);
1038 switch (wValue) {
1039 case USB_PORT_FEAT_SUSPEND:
1040 temp = readl(port_array[wIndex]);
1041 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1042 xhci_dbg(xhci, "PORTSC %04x\n", temp);
1043 if (temp & PORT_RESET)
1044 goto error;
1045 if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1046 if ((temp & PORT_PE) == 0)
1047 goto error;
1048
1049 set_bit(wIndex, &bus_state->resuming_ports);
1050 xhci_set_link_state(xhci, port_array, wIndex,
1051 XDEV_RESUME);
1052 spin_unlock_irqrestore(&xhci->lock, flags);
1053 msleep(20);
1054 spin_lock_irqsave(&xhci->lock, flags);
1055 xhci_set_link_state(xhci, port_array, wIndex,
1056 XDEV_U0);
1057 clear_bit(wIndex, &bus_state->resuming_ports);
1058 }
1059 bus_state->port_c_suspend |= 1 << wIndex;
1060
1061 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1062 wIndex + 1);
1063 if (!slot_id) {
1064 xhci_dbg(xhci, "slot_id is zero\n");
1065 goto error;
1066 }
1067 xhci_ring_device(xhci, slot_id);
1068 break;
1069 case USB_PORT_FEAT_C_SUSPEND:
1070 bus_state->port_c_suspend &= ~(1 << wIndex);
1071 case USB_PORT_FEAT_C_RESET:
1072 case USB_PORT_FEAT_C_BH_PORT_RESET:
1073 case USB_PORT_FEAT_C_CONNECTION:
1074 case USB_PORT_FEAT_C_OVER_CURRENT:
1075 case USB_PORT_FEAT_C_ENABLE:
1076 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1077 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1078 xhci_clear_port_change_bit(xhci, wValue, wIndex,
1079 port_array[wIndex], temp);
1080 break;
1081 case USB_PORT_FEAT_ENABLE:
1082 xhci_disable_port(hcd, xhci, wIndex,
1083 port_array[wIndex], temp);
1084 break;
1085 case USB_PORT_FEAT_POWER:
1086 writel(temp & ~PORT_POWER, port_array[wIndex]);
1087
1088 spin_unlock_irqrestore(&xhci->lock, flags);
1089 temp = usb_acpi_power_manageable(hcd->self.root_hub,
1090 wIndex);
1091 if (temp)
1092 usb_acpi_set_power_state(hcd->self.root_hub,
1093 wIndex, false);
1094 spin_lock_irqsave(&xhci->lock, flags);
1095 break;
1096 default:
1097 goto error;
1098 }
1099 break;
1100 default:
1101 error:
1102 /* "stall" on error */
1103 retval = -EPIPE;
1104 }
1105 spin_unlock_irqrestore(&xhci->lock, flags);
1106 return retval;
1107 }
1108
1109 /*
1110 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1111 * Ports are 0-indexed from the HCD point of view,
1112 * and 1-indexed from the USB core pointer of view.
1113 *
1114 * Note that the status change bits will be cleared as soon as a port status
1115 * change event is generated, so we use the saved status from that event.
1116 */
xhci_hub_status_data(struct usb_hcd * hcd,char * buf)1117 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1118 {
1119 unsigned long flags;
1120 u32 temp, status;
1121 u32 mask;
1122 int i, retval;
1123 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1124 int max_ports;
1125 __le32 __iomem **port_array;
1126 struct xhci_bus_state *bus_state;
1127 bool reset_change = false;
1128
1129 max_ports = xhci_get_ports(hcd, &port_array);
1130 bus_state = &xhci->bus_state[hcd_index(hcd)];
1131
1132 /* Initial status is no changes */
1133 retval = (max_ports + 8) / 8;
1134 memset(buf, 0, retval);
1135
1136 /*
1137 * Inform the usbcore about resume-in-progress by returning
1138 * a non-zero value even if there are no status changes.
1139 */
1140 status = bus_state->resuming_ports;
1141
1142 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1143
1144 spin_lock_irqsave(&xhci->lock, flags);
1145 /* For each port, did anything change? If so, set that bit in buf. */
1146 for (i = 0; i < max_ports; i++) {
1147 temp = readl(port_array[i]);
1148 if (temp == 0xffffffff) {
1149 retval = -ENODEV;
1150 break;
1151 }
1152 if ((temp & mask) != 0 ||
1153 (bus_state->port_c_suspend & 1 << i) ||
1154 (bus_state->resume_done[i] && time_after_eq(
1155 jiffies, bus_state->resume_done[i]))) {
1156 buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1157 status = 1;
1158 }
1159 if ((temp & PORT_RC))
1160 reset_change = true;
1161 }
1162 if (!status && !reset_change) {
1163 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1164 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1165 }
1166 spin_unlock_irqrestore(&xhci->lock, flags);
1167 return status ? retval : 0;
1168 }
1169
1170 #ifdef CONFIG_PM
1171
xhci_bus_suspend(struct usb_hcd * hcd)1172 int xhci_bus_suspend(struct usb_hcd *hcd)
1173 {
1174 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1175 int max_ports, port_index;
1176 __le32 __iomem **port_array;
1177 struct xhci_bus_state *bus_state;
1178 unsigned long flags;
1179
1180 max_ports = xhci_get_ports(hcd, &port_array);
1181 bus_state = &xhci->bus_state[hcd_index(hcd)];
1182
1183 spin_lock_irqsave(&xhci->lock, flags);
1184
1185 if (hcd->self.root_hub->do_remote_wakeup) {
1186 if (bus_state->resuming_ports) {
1187 spin_unlock_irqrestore(&xhci->lock, flags);
1188 xhci_dbg(xhci, "suspend failed because "
1189 "a port is resuming\n");
1190 return -EBUSY;
1191 }
1192 }
1193
1194 port_index = max_ports;
1195 bus_state->bus_suspended = 0;
1196 while (port_index--) {
1197 /* suspend the port if the port is not suspended */
1198 u32 t1, t2;
1199 int slot_id;
1200
1201 t1 = readl(port_array[port_index]);
1202 t2 = xhci_port_state_to_neutral(t1);
1203
1204 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
1205 xhci_dbg(xhci, "port %d not suspended\n", port_index);
1206 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1207 port_index + 1);
1208 if (slot_id) {
1209 spin_unlock_irqrestore(&xhci->lock, flags);
1210 xhci_stop_device(xhci, slot_id, 1);
1211 spin_lock_irqsave(&xhci->lock, flags);
1212 }
1213 t2 &= ~PORT_PLS_MASK;
1214 t2 |= PORT_LINK_STROBE | XDEV_U3;
1215 set_bit(port_index, &bus_state->bus_suspended);
1216 }
1217 /* USB core sets remote wake mask for USB 3.0 hubs,
1218 * including the USB 3.0 roothub, but only if CONFIG_PM_RUNTIME
1219 * is enabled, so also enable remote wake here.
1220 */
1221 if (hcd->self.root_hub->do_remote_wakeup) {
1222 if (t1 & PORT_CONNECT) {
1223 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1224 t2 &= ~PORT_WKCONN_E;
1225 } else {
1226 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1227 t2 &= ~PORT_WKDISC_E;
1228 }
1229 } else
1230 t2 &= ~PORT_WAKE_BITS;
1231
1232 t1 = xhci_port_state_to_neutral(t1);
1233 if (t1 != t2)
1234 writel(t2, port_array[port_index]);
1235 }
1236 hcd->state = HC_STATE_SUSPENDED;
1237 bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1238 spin_unlock_irqrestore(&xhci->lock, flags);
1239 return 0;
1240 }
1241
xhci_bus_resume(struct usb_hcd * hcd)1242 int xhci_bus_resume(struct usb_hcd *hcd)
1243 {
1244 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1245 int max_ports, port_index;
1246 __le32 __iomem **port_array;
1247 struct xhci_bus_state *bus_state;
1248 u32 temp;
1249 unsigned long flags;
1250
1251 max_ports = xhci_get_ports(hcd, &port_array);
1252 bus_state = &xhci->bus_state[hcd_index(hcd)];
1253
1254 if (time_before(jiffies, bus_state->next_statechange))
1255 msleep(5);
1256
1257 spin_lock_irqsave(&xhci->lock, flags);
1258 if (!HCD_HW_ACCESSIBLE(hcd)) {
1259 spin_unlock_irqrestore(&xhci->lock, flags);
1260 return -ESHUTDOWN;
1261 }
1262
1263 /* delay the irqs */
1264 temp = readl(&xhci->op_regs->command);
1265 temp &= ~CMD_EIE;
1266 writel(temp, &xhci->op_regs->command);
1267
1268 port_index = max_ports;
1269 while (port_index--) {
1270 /* Check whether need resume ports. If needed
1271 resume port and disable remote wakeup */
1272 u32 temp;
1273 int slot_id;
1274
1275 temp = readl(port_array[port_index]);
1276 if (DEV_SUPERSPEED(temp))
1277 temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1278 else
1279 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
1280 if (test_bit(port_index, &bus_state->bus_suspended) &&
1281 (temp & PORT_PLS_MASK)) {
1282 if (DEV_SUPERSPEED(temp)) {
1283 xhci_set_link_state(xhci, port_array,
1284 port_index, XDEV_U0);
1285 } else {
1286 xhci_set_link_state(xhci, port_array,
1287 port_index, XDEV_RESUME);
1288
1289 spin_unlock_irqrestore(&xhci->lock, flags);
1290 msleep(20);
1291 spin_lock_irqsave(&xhci->lock, flags);
1292
1293 xhci_set_link_state(xhci, port_array,
1294 port_index, XDEV_U0);
1295 }
1296 /* wait for the port to enter U0 and report port link
1297 * state change.
1298 */
1299 spin_unlock_irqrestore(&xhci->lock, flags);
1300 msleep(20);
1301 spin_lock_irqsave(&xhci->lock, flags);
1302
1303 /* Clear PLC */
1304 xhci_test_and_clear_bit(xhci, port_array, port_index,
1305 PORT_PLC);
1306
1307 slot_id = xhci_find_slot_id_by_port(hcd,
1308 xhci, port_index + 1);
1309 if (slot_id)
1310 xhci_ring_device(xhci, slot_id);
1311 } else
1312 writel(temp, port_array[port_index]);
1313 }
1314
1315 (void) readl(&xhci->op_regs->command);
1316
1317 bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1318 /* re-enable irqs */
1319 temp = readl(&xhci->op_regs->command);
1320 temp |= CMD_EIE;
1321 writel(temp, &xhci->op_regs->command);
1322 temp = readl(&xhci->op_regs->command);
1323
1324 spin_unlock_irqrestore(&xhci->lock, flags);
1325 return 0;
1326 }
1327
1328 #endif /* CONFIG_PM */
1329