1 #include <linux/device.h>
2 #include <linux/dma-mapping.h>
3 #include <linux/dmaengine.h>
4 #include <linux/sizes.h>
5 #include <linux/platform_device.h>
6 #include <linux/of.h>
7
8 #include "musb_core.h"
9
10 #define RNDIS_REG(x) (0x80 + ((x - 1) * 4))
11
12 #define EP_MODE_AUTOREQ_NONE 0
13 #define EP_MODE_AUTOREQ_ALL_NEOP 1
14 #define EP_MODE_AUTOREQ_ALWAYS 3
15
16 #define EP_MODE_DMA_TRANSPARENT 0
17 #define EP_MODE_DMA_RNDIS 1
18 #define EP_MODE_DMA_GEN_RNDIS 3
19
20 #define USB_CTRL_TX_MODE 0x70
21 #define USB_CTRL_RX_MODE 0x74
22 #define USB_CTRL_AUTOREQ 0xd0
23 #define USB_TDOWN 0xd8
24
25 struct cppi41_dma_channel {
26 struct dma_channel channel;
27 struct cppi41_dma_controller *controller;
28 struct musb_hw_ep *hw_ep;
29 struct dma_chan *dc;
30 dma_cookie_t cookie;
31 u8 port_num;
32 u8 is_tx;
33 u8 is_allocated;
34 u8 usb_toggle;
35
36 dma_addr_t buf_addr;
37 u32 total_len;
38 u32 prog_len;
39 u32 transferred;
40 u32 packet_sz;
41 struct list_head tx_check;
42 int tx_zlp;
43 };
44
45 #define MUSB_DMA_NUM_CHANNELS 15
46
47 struct cppi41_dma_controller {
48 struct dma_controller controller;
49 struct cppi41_dma_channel rx_channel[MUSB_DMA_NUM_CHANNELS];
50 struct cppi41_dma_channel tx_channel[MUSB_DMA_NUM_CHANNELS];
51 struct musb *musb;
52 struct hrtimer early_tx;
53 struct list_head early_tx_list;
54 u32 rx_mode;
55 u32 tx_mode;
56 u32 auto_req;
57 };
58
save_rx_toggle(struct cppi41_dma_channel * cppi41_channel)59 static void save_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
60 {
61 u16 csr;
62 u8 toggle;
63
64 if (cppi41_channel->is_tx)
65 return;
66 if (!is_host_active(cppi41_channel->controller->musb))
67 return;
68
69 csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR);
70 toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;
71
72 cppi41_channel->usb_toggle = toggle;
73 }
74
update_rx_toggle(struct cppi41_dma_channel * cppi41_channel)75 static void update_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
76 {
77 struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
78 struct musb *musb = hw_ep->musb;
79 u16 csr;
80 u8 toggle;
81
82 if (cppi41_channel->is_tx)
83 return;
84 if (!is_host_active(musb))
85 return;
86
87 musb_ep_select(musb->mregs, hw_ep->epnum);
88 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
89 toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;
90
91 /*
92 * AM335x Advisory 1.0.13: Due to internal synchronisation error the
93 * data toggle may reset from DATA1 to DATA0 during receiving data from
94 * more than one endpoint.
95 */
96 if (!toggle && toggle == cppi41_channel->usb_toggle) {
97 csr |= MUSB_RXCSR_H_DATATOGGLE | MUSB_RXCSR_H_WR_DATATOGGLE;
98 musb_writew(cppi41_channel->hw_ep->regs, MUSB_RXCSR, csr);
99 dev_dbg(cppi41_channel->controller->musb->controller,
100 "Restoring DATA1 toggle.\n");
101 }
102
103 cppi41_channel->usb_toggle = toggle;
104 }
105
musb_is_tx_fifo_empty(struct musb_hw_ep * hw_ep)106 static bool musb_is_tx_fifo_empty(struct musb_hw_ep *hw_ep)
107 {
108 u8 epnum = hw_ep->epnum;
109 struct musb *musb = hw_ep->musb;
110 void __iomem *epio = musb->endpoints[epnum].regs;
111 u16 csr;
112
113 musb_ep_select(musb->mregs, hw_ep->epnum);
114 csr = musb_readw(epio, MUSB_TXCSR);
115 if (csr & MUSB_TXCSR_TXPKTRDY)
116 return false;
117 return true;
118 }
119
120 static void cppi41_dma_callback(void *private_data);
121
cppi41_trans_done(struct cppi41_dma_channel * cppi41_channel)122 static void cppi41_trans_done(struct cppi41_dma_channel *cppi41_channel)
123 {
124 struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
125 struct musb *musb = hw_ep->musb;
126 void __iomem *epio = hw_ep->regs;
127 u16 csr;
128
129 if (!cppi41_channel->prog_len ||
130 (cppi41_channel->channel.status == MUSB_DMA_STATUS_FREE)) {
131
132 /* done, complete */
133 cppi41_channel->channel.actual_len =
134 cppi41_channel->transferred;
135 cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
136 cppi41_channel->channel.rx_packet_done = true;
137
138 /*
139 * transmit ZLP using PIO mode for transfers which size is
140 * multiple of EP packet size.
141 */
142 if (cppi41_channel->tx_zlp && (cppi41_channel->transferred %
143 cppi41_channel->packet_sz) == 0) {
144 musb_ep_select(musb->mregs, hw_ep->epnum);
145 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY;
146 musb_writew(epio, MUSB_TXCSR, csr);
147 }
148 musb_dma_completion(musb, hw_ep->epnum, cppi41_channel->is_tx);
149 } else {
150 /* next iteration, reload */
151 struct dma_chan *dc = cppi41_channel->dc;
152 struct dma_async_tx_descriptor *dma_desc;
153 enum dma_transfer_direction direction;
154 u32 remain_bytes;
155
156 cppi41_channel->buf_addr += cppi41_channel->packet_sz;
157
158 remain_bytes = cppi41_channel->total_len;
159 remain_bytes -= cppi41_channel->transferred;
160 remain_bytes = min(remain_bytes, cppi41_channel->packet_sz);
161 cppi41_channel->prog_len = remain_bytes;
162
163 direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV
164 : DMA_DEV_TO_MEM;
165 dma_desc = dmaengine_prep_slave_single(dc,
166 cppi41_channel->buf_addr,
167 remain_bytes,
168 direction,
169 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
170 if (WARN_ON(!dma_desc))
171 return;
172
173 dma_desc->callback = cppi41_dma_callback;
174 dma_desc->callback_param = &cppi41_channel->channel;
175 cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
176 dma_async_issue_pending(dc);
177
178 if (!cppi41_channel->is_tx) {
179 musb_ep_select(musb->mregs, hw_ep->epnum);
180 csr = musb_readw(epio, MUSB_RXCSR);
181 csr |= MUSB_RXCSR_H_REQPKT;
182 musb_writew(epio, MUSB_RXCSR, csr);
183 }
184 }
185 }
186
cppi41_recheck_tx_req(struct hrtimer * timer)187 static enum hrtimer_restart cppi41_recheck_tx_req(struct hrtimer *timer)
188 {
189 struct cppi41_dma_controller *controller;
190 struct cppi41_dma_channel *cppi41_channel, *n;
191 struct musb *musb;
192 unsigned long flags;
193 enum hrtimer_restart ret = HRTIMER_NORESTART;
194
195 controller = container_of(timer, struct cppi41_dma_controller,
196 early_tx);
197 musb = controller->musb;
198
199 spin_lock_irqsave(&musb->lock, flags);
200 list_for_each_entry_safe(cppi41_channel, n, &controller->early_tx_list,
201 tx_check) {
202 bool empty;
203 struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
204
205 empty = musb_is_tx_fifo_empty(hw_ep);
206 if (empty) {
207 list_del_init(&cppi41_channel->tx_check);
208 cppi41_trans_done(cppi41_channel);
209 }
210 }
211
212 if (!list_empty(&controller->early_tx_list) &&
213 !hrtimer_is_queued(&controller->early_tx)) {
214 ret = HRTIMER_RESTART;
215 hrtimer_forward_now(&controller->early_tx,
216 ktime_set(0, 20 * NSEC_PER_USEC));
217 }
218
219 spin_unlock_irqrestore(&musb->lock, flags);
220 return ret;
221 }
222
cppi41_dma_callback(void * private_data)223 static void cppi41_dma_callback(void *private_data)
224 {
225 struct dma_channel *channel = private_data;
226 struct cppi41_dma_channel *cppi41_channel = channel->private_data;
227 struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
228 struct musb *musb = hw_ep->musb;
229 unsigned long flags;
230 struct dma_tx_state txstate;
231 u32 transferred;
232 bool empty;
233
234 spin_lock_irqsave(&musb->lock, flags);
235
236 dmaengine_tx_status(cppi41_channel->dc, cppi41_channel->cookie,
237 &txstate);
238 transferred = cppi41_channel->prog_len - txstate.residue;
239 cppi41_channel->transferred += transferred;
240
241 dev_dbg(musb->controller, "DMA transfer done on hw_ep=%d bytes=%d/%d\n",
242 hw_ep->epnum, cppi41_channel->transferred,
243 cppi41_channel->total_len);
244
245 update_rx_toggle(cppi41_channel);
246
247 if (cppi41_channel->transferred == cppi41_channel->total_len ||
248 transferred < cppi41_channel->packet_sz)
249 cppi41_channel->prog_len = 0;
250
251 empty = musb_is_tx_fifo_empty(hw_ep);
252 if (empty) {
253 cppi41_trans_done(cppi41_channel);
254 } else {
255 struct cppi41_dma_controller *controller;
256 /*
257 * On AM335x it has been observed that the TX interrupt fires
258 * too early that means the TXFIFO is not yet empty but the DMA
259 * engine says that it is done with the transfer. We don't
260 * receive a FIFO empty interrupt so the only thing we can do is
261 * to poll for the bit. On HS it usually takes 2us, on FS around
262 * 110us - 150us depending on the transfer size.
263 * We spin on HS (no longer than than 25us and setup a timer on
264 * FS to check for the bit and complete the transfer.
265 */
266 controller = cppi41_channel->controller;
267
268 if (musb->g.speed == USB_SPEED_HIGH) {
269 unsigned wait = 25;
270
271 do {
272 empty = musb_is_tx_fifo_empty(hw_ep);
273 if (empty)
274 break;
275 wait--;
276 if (!wait)
277 break;
278 udelay(1);
279 } while (1);
280
281 empty = musb_is_tx_fifo_empty(hw_ep);
282 if (empty) {
283 cppi41_trans_done(cppi41_channel);
284 goto out;
285 }
286 }
287 list_add_tail(&cppi41_channel->tx_check,
288 &controller->early_tx_list);
289 if (!hrtimer_is_queued(&controller->early_tx)) {
290 unsigned long usecs = cppi41_channel->total_len / 10;
291
292 hrtimer_start_range_ns(&controller->early_tx,
293 ktime_set(0, usecs * NSEC_PER_USEC),
294 20 * NSEC_PER_USEC,
295 HRTIMER_MODE_REL);
296 }
297 }
298 out:
299 spin_unlock_irqrestore(&musb->lock, flags);
300 }
301
update_ep_mode(unsigned ep,unsigned mode,u32 old)302 static u32 update_ep_mode(unsigned ep, unsigned mode, u32 old)
303 {
304 unsigned shift;
305
306 shift = (ep - 1) * 2;
307 old &= ~(3 << shift);
308 old |= mode << shift;
309 return old;
310 }
311
cppi41_set_dma_mode(struct cppi41_dma_channel * cppi41_channel,unsigned mode)312 static void cppi41_set_dma_mode(struct cppi41_dma_channel *cppi41_channel,
313 unsigned mode)
314 {
315 struct cppi41_dma_controller *controller = cppi41_channel->controller;
316 u32 port;
317 u32 new_mode;
318 u32 old_mode;
319
320 if (cppi41_channel->is_tx)
321 old_mode = controller->tx_mode;
322 else
323 old_mode = controller->rx_mode;
324 port = cppi41_channel->port_num;
325 new_mode = update_ep_mode(port, mode, old_mode);
326
327 if (new_mode == old_mode)
328 return;
329 if (cppi41_channel->is_tx) {
330 controller->tx_mode = new_mode;
331 musb_writel(controller->musb->ctrl_base, USB_CTRL_TX_MODE,
332 new_mode);
333 } else {
334 controller->rx_mode = new_mode;
335 musb_writel(controller->musb->ctrl_base, USB_CTRL_RX_MODE,
336 new_mode);
337 }
338 }
339
cppi41_set_autoreq_mode(struct cppi41_dma_channel * cppi41_channel,unsigned mode)340 static void cppi41_set_autoreq_mode(struct cppi41_dma_channel *cppi41_channel,
341 unsigned mode)
342 {
343 struct cppi41_dma_controller *controller = cppi41_channel->controller;
344 u32 port;
345 u32 new_mode;
346 u32 old_mode;
347
348 old_mode = controller->auto_req;
349 port = cppi41_channel->port_num;
350 new_mode = update_ep_mode(port, mode, old_mode);
351
352 if (new_mode == old_mode)
353 return;
354 controller->auto_req = new_mode;
355 musb_writel(controller->musb->ctrl_base, USB_CTRL_AUTOREQ, new_mode);
356 }
357
cppi41_configure_channel(struct dma_channel * channel,u16 packet_sz,u8 mode,dma_addr_t dma_addr,u32 len)358 static bool cppi41_configure_channel(struct dma_channel *channel,
359 u16 packet_sz, u8 mode,
360 dma_addr_t dma_addr, u32 len)
361 {
362 struct cppi41_dma_channel *cppi41_channel = channel->private_data;
363 struct dma_chan *dc = cppi41_channel->dc;
364 struct dma_async_tx_descriptor *dma_desc;
365 enum dma_transfer_direction direction;
366 struct musb *musb = cppi41_channel->controller->musb;
367 unsigned use_gen_rndis = 0;
368
369 dev_dbg(musb->controller,
370 "configure ep%d/%x packet_sz=%d, mode=%d, dma_addr=0x%llx, len=%d is_tx=%d\n",
371 cppi41_channel->port_num, RNDIS_REG(cppi41_channel->port_num),
372 packet_sz, mode, (unsigned long long) dma_addr,
373 len, cppi41_channel->is_tx);
374
375 cppi41_channel->buf_addr = dma_addr;
376 cppi41_channel->total_len = len;
377 cppi41_channel->transferred = 0;
378 cppi41_channel->packet_sz = packet_sz;
379 cppi41_channel->tx_zlp = (cppi41_channel->is_tx && mode) ? 1 : 0;
380
381 /*
382 * Due to AM335x' Advisory 1.0.13 we are not allowed to transfer more
383 * than max packet size at a time.
384 */
385 if (cppi41_channel->is_tx)
386 use_gen_rndis = 1;
387
388 if (use_gen_rndis) {
389 /* RNDIS mode */
390 if (len > packet_sz) {
391 musb_writel(musb->ctrl_base,
392 RNDIS_REG(cppi41_channel->port_num), len);
393 /* gen rndis */
394 cppi41_set_dma_mode(cppi41_channel,
395 EP_MODE_DMA_GEN_RNDIS);
396
397 /* auto req */
398 cppi41_set_autoreq_mode(cppi41_channel,
399 EP_MODE_AUTOREQ_ALL_NEOP);
400 } else {
401 musb_writel(musb->ctrl_base,
402 RNDIS_REG(cppi41_channel->port_num), 0);
403 cppi41_set_dma_mode(cppi41_channel,
404 EP_MODE_DMA_TRANSPARENT);
405 cppi41_set_autoreq_mode(cppi41_channel,
406 EP_MODE_AUTOREQ_NONE);
407 }
408 } else {
409 /* fallback mode */
410 cppi41_set_dma_mode(cppi41_channel, EP_MODE_DMA_TRANSPARENT);
411 cppi41_set_autoreq_mode(cppi41_channel, EP_MODE_AUTOREQ_NONE);
412 len = min_t(u32, packet_sz, len);
413 }
414 cppi41_channel->prog_len = len;
415 direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
416 dma_desc = dmaengine_prep_slave_single(dc, dma_addr, len, direction,
417 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
418 if (!dma_desc)
419 return false;
420
421 dma_desc->callback = cppi41_dma_callback;
422 dma_desc->callback_param = channel;
423 cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
424 cppi41_channel->channel.rx_packet_done = false;
425
426 save_rx_toggle(cppi41_channel);
427 dma_async_issue_pending(dc);
428 return true;
429 }
430
cppi41_dma_channel_allocate(struct dma_controller * c,struct musb_hw_ep * hw_ep,u8 is_tx)431 static struct dma_channel *cppi41_dma_channel_allocate(struct dma_controller *c,
432 struct musb_hw_ep *hw_ep, u8 is_tx)
433 {
434 struct cppi41_dma_controller *controller = container_of(c,
435 struct cppi41_dma_controller, controller);
436 struct cppi41_dma_channel *cppi41_channel = NULL;
437 u8 ch_num = hw_ep->epnum - 1;
438
439 if (ch_num >= MUSB_DMA_NUM_CHANNELS)
440 return NULL;
441
442 if (is_tx)
443 cppi41_channel = &controller->tx_channel[ch_num];
444 else
445 cppi41_channel = &controller->rx_channel[ch_num];
446
447 if (!cppi41_channel->dc)
448 return NULL;
449
450 if (cppi41_channel->is_allocated)
451 return NULL;
452
453 cppi41_channel->hw_ep = hw_ep;
454 cppi41_channel->is_allocated = 1;
455
456 return &cppi41_channel->channel;
457 }
458
cppi41_dma_channel_release(struct dma_channel * channel)459 static void cppi41_dma_channel_release(struct dma_channel *channel)
460 {
461 struct cppi41_dma_channel *cppi41_channel = channel->private_data;
462
463 if (cppi41_channel->is_allocated) {
464 cppi41_channel->is_allocated = 0;
465 channel->status = MUSB_DMA_STATUS_FREE;
466 channel->actual_len = 0;
467 }
468 }
469
cppi41_dma_channel_program(struct dma_channel * channel,u16 packet_sz,u8 mode,dma_addr_t dma_addr,u32 len)470 static int cppi41_dma_channel_program(struct dma_channel *channel,
471 u16 packet_sz, u8 mode,
472 dma_addr_t dma_addr, u32 len)
473 {
474 int ret;
475 struct cppi41_dma_channel *cppi41_channel = channel->private_data;
476 int hb_mult = 0;
477
478 BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
479 channel->status == MUSB_DMA_STATUS_BUSY);
480
481 if (is_host_active(cppi41_channel->controller->musb)) {
482 if (cppi41_channel->is_tx)
483 hb_mult = cppi41_channel->hw_ep->out_qh->hb_mult;
484 else
485 hb_mult = cppi41_channel->hw_ep->in_qh->hb_mult;
486 }
487
488 channel->status = MUSB_DMA_STATUS_BUSY;
489 channel->actual_len = 0;
490
491 if (hb_mult)
492 packet_sz = hb_mult * (packet_sz & 0x7FF);
493
494 ret = cppi41_configure_channel(channel, packet_sz, mode, dma_addr, len);
495 if (!ret)
496 channel->status = MUSB_DMA_STATUS_FREE;
497
498 return ret;
499 }
500
cppi41_is_compatible(struct dma_channel * channel,u16 maxpacket,void * buf,u32 length)501 static int cppi41_is_compatible(struct dma_channel *channel, u16 maxpacket,
502 void *buf, u32 length)
503 {
504 struct cppi41_dma_channel *cppi41_channel = channel->private_data;
505 struct cppi41_dma_controller *controller = cppi41_channel->controller;
506 struct musb *musb = controller->musb;
507
508 if (is_host_active(musb)) {
509 WARN_ON(1);
510 return 1;
511 }
512 if (cppi41_channel->hw_ep->ep_in.type != USB_ENDPOINT_XFER_BULK)
513 return 0;
514 if (cppi41_channel->is_tx)
515 return 1;
516 /* AM335x Advisory 1.0.13. No workaround for device RX mode */
517 return 0;
518 }
519
cppi41_dma_channel_abort(struct dma_channel * channel)520 static int cppi41_dma_channel_abort(struct dma_channel *channel)
521 {
522 struct cppi41_dma_channel *cppi41_channel = channel->private_data;
523 struct cppi41_dma_controller *controller = cppi41_channel->controller;
524 struct musb *musb = controller->musb;
525 void __iomem *epio = cppi41_channel->hw_ep->regs;
526 int tdbit;
527 int ret;
528 unsigned is_tx;
529 u16 csr;
530
531 is_tx = cppi41_channel->is_tx;
532 dev_dbg(musb->controller, "abort channel=%d, is_tx=%d\n",
533 cppi41_channel->port_num, is_tx);
534
535 if (cppi41_channel->channel.status == MUSB_DMA_STATUS_FREE)
536 return 0;
537
538 list_del_init(&cppi41_channel->tx_check);
539 if (is_tx) {
540 csr = musb_readw(epio, MUSB_TXCSR);
541 csr &= ~MUSB_TXCSR_DMAENAB;
542 musb_writew(epio, MUSB_TXCSR, csr);
543 } else {
544 cppi41_set_autoreq_mode(cppi41_channel, EP_MODE_AUTOREQ_NONE);
545
546 /* delay to drain to cppi dma pipeline for isoch */
547 udelay(250);
548
549 csr = musb_readw(epio, MUSB_RXCSR);
550 csr &= ~(MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_DMAENAB);
551 musb_writew(epio, MUSB_RXCSR, csr);
552
553 /* wait to drain cppi dma pipe line */
554 udelay(50);
555
556 csr = musb_readw(epio, MUSB_RXCSR);
557 if (csr & MUSB_RXCSR_RXPKTRDY) {
558 csr |= MUSB_RXCSR_FLUSHFIFO;
559 musb_writew(epio, MUSB_RXCSR, csr);
560 musb_writew(epio, MUSB_RXCSR, csr);
561 }
562 }
563
564 tdbit = 1 << cppi41_channel->port_num;
565 if (is_tx)
566 tdbit <<= 16;
567
568 do {
569 if (is_tx)
570 musb_writel(musb->ctrl_base, USB_TDOWN, tdbit);
571 ret = dmaengine_terminate_all(cppi41_channel->dc);
572 } while (ret == -EAGAIN);
573
574 if (is_tx) {
575 musb_writel(musb->ctrl_base, USB_TDOWN, tdbit);
576
577 csr = musb_readw(epio, MUSB_TXCSR);
578 if (csr & MUSB_TXCSR_TXPKTRDY) {
579 csr |= MUSB_TXCSR_FLUSHFIFO;
580 musb_writew(epio, MUSB_TXCSR, csr);
581 }
582 }
583
584 cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
585 return 0;
586 }
587
cppi41_release_all_dma_chans(struct cppi41_dma_controller * ctrl)588 static void cppi41_release_all_dma_chans(struct cppi41_dma_controller *ctrl)
589 {
590 struct dma_chan *dc;
591 int i;
592
593 for (i = 0; i < MUSB_DMA_NUM_CHANNELS; i++) {
594 dc = ctrl->tx_channel[i].dc;
595 if (dc)
596 dma_release_channel(dc);
597 dc = ctrl->rx_channel[i].dc;
598 if (dc)
599 dma_release_channel(dc);
600 }
601 }
602
cppi41_dma_controller_stop(struct cppi41_dma_controller * controller)603 static void cppi41_dma_controller_stop(struct cppi41_dma_controller *controller)
604 {
605 cppi41_release_all_dma_chans(controller);
606 }
607
cppi41_dma_controller_start(struct cppi41_dma_controller * controller)608 static int cppi41_dma_controller_start(struct cppi41_dma_controller *controller)
609 {
610 struct musb *musb = controller->musb;
611 struct device *dev = musb->controller;
612 struct device_node *np = dev->parent->of_node;
613 struct cppi41_dma_channel *cppi41_channel;
614 int count;
615 int i;
616 int ret;
617
618 count = of_property_count_strings(np, "dma-names");
619 if (count < 0)
620 return count;
621
622 for (i = 0; i < count; i++) {
623 struct dma_chan *dc;
624 struct dma_channel *musb_dma;
625 const char *str;
626 unsigned is_tx;
627 unsigned int port;
628
629 ret = of_property_read_string_index(np, "dma-names", i, &str);
630 if (ret)
631 goto err;
632 if (!strncmp(str, "tx", 2))
633 is_tx = 1;
634 else if (!strncmp(str, "rx", 2))
635 is_tx = 0;
636 else {
637 dev_err(dev, "Wrong dmatype %s\n", str);
638 goto err;
639 }
640 ret = kstrtouint(str + 2, 0, &port);
641 if (ret)
642 goto err;
643
644 ret = -EINVAL;
645 if (port > MUSB_DMA_NUM_CHANNELS || !port)
646 goto err;
647 if (is_tx)
648 cppi41_channel = &controller->tx_channel[port - 1];
649 else
650 cppi41_channel = &controller->rx_channel[port - 1];
651
652 cppi41_channel->controller = controller;
653 cppi41_channel->port_num = port;
654 cppi41_channel->is_tx = is_tx;
655 INIT_LIST_HEAD(&cppi41_channel->tx_check);
656
657 musb_dma = &cppi41_channel->channel;
658 musb_dma->private_data = cppi41_channel;
659 musb_dma->status = MUSB_DMA_STATUS_FREE;
660 musb_dma->max_len = SZ_4M;
661
662 dc = dma_request_slave_channel(dev->parent, str);
663 if (!dc) {
664 dev_err(dev, "Failed to request %s.\n", str);
665 ret = -EPROBE_DEFER;
666 goto err;
667 }
668 cppi41_channel->dc = dc;
669 }
670 return 0;
671 err:
672 cppi41_release_all_dma_chans(controller);
673 return ret;
674 }
675
dma_controller_destroy(struct dma_controller * c)676 void dma_controller_destroy(struct dma_controller *c)
677 {
678 struct cppi41_dma_controller *controller = container_of(c,
679 struct cppi41_dma_controller, controller);
680
681 hrtimer_cancel(&controller->early_tx);
682 cppi41_dma_controller_stop(controller);
683 kfree(controller);
684 }
685
dma_controller_create(struct musb * musb,void __iomem * base)686 struct dma_controller *dma_controller_create(struct musb *musb,
687 void __iomem *base)
688 {
689 struct cppi41_dma_controller *controller;
690 int ret = 0;
691
692 if (!musb->controller->parent->of_node) {
693 dev_err(musb->controller, "Need DT for the DMA engine.\n");
694 return NULL;
695 }
696
697 controller = kzalloc(sizeof(*controller), GFP_KERNEL);
698 if (!controller)
699 goto kzalloc_fail;
700
701 hrtimer_init(&controller->early_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
702 controller->early_tx.function = cppi41_recheck_tx_req;
703 INIT_LIST_HEAD(&controller->early_tx_list);
704 controller->musb = musb;
705
706 controller->controller.channel_alloc = cppi41_dma_channel_allocate;
707 controller->controller.channel_release = cppi41_dma_channel_release;
708 controller->controller.channel_program = cppi41_dma_channel_program;
709 controller->controller.channel_abort = cppi41_dma_channel_abort;
710 controller->controller.is_compatible = cppi41_is_compatible;
711
712 ret = cppi41_dma_controller_start(controller);
713 if (ret)
714 goto plat_get_fail;
715 return &controller->controller;
716
717 plat_get_fail:
718 kfree(controller);
719 kzalloc_fail:
720 if (ret == -EPROBE_DEFER)
721 return ERR_PTR(ret);
722 return NULL;
723 }
724