1 /*
2 * MUSB OTG driver host support
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
35
36 #include <linux/module.h>
37 #include <linux/kernel.h>
38 #include <linux/delay.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/errno.h>
42 #include <linux/list.h>
43 #include <linux/dma-mapping.h>
44
45 #include "musb_core.h"
46 #include "musb_host.h"
47
48 /* MUSB HOST status 22-mar-2006
49 *
50 * - There's still lots of partial code duplication for fault paths, so
51 * they aren't handled as consistently as they need to be.
52 *
53 * - PIO mostly behaved when last tested.
54 * + including ep0, with all usbtest cases 9, 10
55 * + usbtest 14 (ep0out) doesn't seem to run at all
56 * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest
57 * configurations, but otherwise double buffering passes basic tests.
58 * + for 2.6.N, for N > ~10, needs API changes for hcd framework.
59 *
60 * - DMA (CPPI) ... partially behaves, not currently recommended
61 * + about 1/15 the speed of typical EHCI implementations (PCI)
62 * + RX, all too often reqpkt seems to misbehave after tx
63 * + TX, no known issues (other than evident silicon issue)
64 *
65 * - DMA (Mentor/OMAP) ...has at least toggle update problems
66 *
67 * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet
68 * starvation ... nothing yet for TX, interrupt, or bulk.
69 *
70 * - Not tested with HNP, but some SRP paths seem to behave.
71 *
72 * NOTE 24-August-2006:
73 *
74 * - Bulk traffic finally uses both sides of hardware ep1, freeing up an
75 * extra endpoint for periodic use enabling hub + keybd + mouse. That
76 * mostly works, except that with "usbnet" it's easy to trigger cases
77 * with "ping" where RX loses. (a) ping to davinci, even "ping -f",
78 * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses
79 * although ARP RX wins. (That test was done with a full speed link.)
80 */
81
82
83 /*
84 * NOTE on endpoint usage:
85 *
86 * CONTROL transfers all go through ep0. BULK ones go through dedicated IN
87 * and OUT endpoints ... hardware is dedicated for those "async" queue(s).
88 * (Yes, bulk _could_ use more of the endpoints than that, and would even
89 * benefit from it.)
90 *
91 * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints.
92 * So far that scheduling is both dumb and optimistic: the endpoint will be
93 * "claimed" until its software queue is no longer refilled. No multiplexing
94 * of transfers between endpoints, or anything clever.
95 */
96
hcd_to_musb(struct usb_hcd * hcd)97 struct musb *hcd_to_musb(struct usb_hcd *hcd)
98 {
99 return *(struct musb **) hcd->hcd_priv;
100 }
101
102
103 static void musb_ep_program(struct musb *musb, u8 epnum,
104 struct urb *urb, int is_out,
105 u8 *buf, u32 offset, u32 len);
106
107 /*
108 * Clear TX fifo. Needed to avoid BABBLE errors.
109 */
musb_h_tx_flush_fifo(struct musb_hw_ep * ep)110 static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
111 {
112 struct musb *musb = ep->musb;
113 void __iomem *epio = ep->regs;
114 u16 csr;
115 u16 lastcsr = 0;
116 int retries = 1000;
117
118 csr = musb_readw(epio, MUSB_TXCSR);
119 while (csr & MUSB_TXCSR_FIFONOTEMPTY) {
120 if (csr != lastcsr)
121 dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
122 lastcsr = csr;
123 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_TXPKTRDY;
124 musb_writew(epio, MUSB_TXCSR, csr);
125 csr = musb_readw(epio, MUSB_TXCSR);
126 if (WARN(retries-- < 1,
127 "Could not flush host TX%d fifo: csr: %04x\n",
128 ep->epnum, csr))
129 return;
130 mdelay(1);
131 }
132 }
133
musb_h_ep0_flush_fifo(struct musb_hw_ep * ep)134 static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep)
135 {
136 void __iomem *epio = ep->regs;
137 u16 csr;
138 int retries = 5;
139
140 /* scrub any data left in the fifo */
141 do {
142 csr = musb_readw(epio, MUSB_TXCSR);
143 if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY)))
144 break;
145 musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO);
146 csr = musb_readw(epio, MUSB_TXCSR);
147 udelay(10);
148 } while (--retries);
149
150 WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n",
151 ep->epnum, csr);
152
153 /* and reset for the next transfer */
154 musb_writew(epio, MUSB_TXCSR, 0);
155 }
156
157 /*
158 * Start transmit. Caller is responsible for locking shared resources.
159 * musb must be locked.
160 */
musb_h_tx_start(struct musb_hw_ep * ep)161 static inline void musb_h_tx_start(struct musb_hw_ep *ep)
162 {
163 u16 txcsr;
164
165 /* NOTE: no locks here; caller should lock and select EP */
166 if (ep->epnum) {
167 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
168 txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS;
169 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
170 } else {
171 txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY;
172 musb_writew(ep->regs, MUSB_CSR0, txcsr);
173 }
174
175 }
176
musb_h_tx_dma_start(struct musb_hw_ep * ep)177 static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep)
178 {
179 u16 txcsr;
180
181 /* NOTE: no locks here; caller should lock and select EP */
182 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
183 txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS;
184 if (is_cppi_enabled())
185 txcsr |= MUSB_TXCSR_DMAMODE;
186 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
187 }
188
musb_ep_set_qh(struct musb_hw_ep * ep,int is_in,struct musb_qh * qh)189 static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh)
190 {
191 if (is_in != 0 || ep->is_shared_fifo)
192 ep->in_qh = qh;
193 if (is_in == 0 || ep->is_shared_fifo)
194 ep->out_qh = qh;
195 }
196
musb_ep_get_qh(struct musb_hw_ep * ep,int is_in)197 static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in)
198 {
199 return is_in ? ep->in_qh : ep->out_qh;
200 }
201
202 /*
203 * Start the URB at the front of an endpoint's queue
204 * end must be claimed from the caller.
205 *
206 * Context: controller locked, irqs blocked
207 */
208 static void
musb_start_urb(struct musb * musb,int is_in,struct musb_qh * qh)209 musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
210 {
211 u16 frame;
212 u32 len;
213 void __iomem *mbase = musb->mregs;
214 struct urb *urb = next_urb(qh);
215 void *buf = urb->transfer_buffer;
216 u32 offset = 0;
217 struct musb_hw_ep *hw_ep = qh->hw_ep;
218 unsigned pipe = urb->pipe;
219 u8 address = usb_pipedevice(pipe);
220 int epnum = hw_ep->epnum;
221
222 /* initialize software qh state */
223 qh->offset = 0;
224 qh->segsize = 0;
225
226 /* gather right source of data */
227 switch (qh->type) {
228 case USB_ENDPOINT_XFER_CONTROL:
229 /* control transfers always start with SETUP */
230 is_in = 0;
231 musb->ep0_stage = MUSB_EP0_START;
232 buf = urb->setup_packet;
233 len = 8;
234 break;
235 case USB_ENDPOINT_XFER_ISOC:
236 qh->iso_idx = 0;
237 qh->frame = 0;
238 offset = urb->iso_frame_desc[0].offset;
239 len = urb->iso_frame_desc[0].length;
240 break;
241 default: /* bulk, interrupt */
242 /* actual_length may be nonzero on retry paths */
243 buf = urb->transfer_buffer + urb->actual_length;
244 len = urb->transfer_buffer_length - urb->actual_length;
245 }
246
247 dev_dbg(musb->controller, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
248 qh, urb, address, qh->epnum,
249 is_in ? "in" : "out",
250 ({char *s; switch (qh->type) {
251 case USB_ENDPOINT_XFER_CONTROL: s = ""; break;
252 case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break;
253 case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break;
254 default: s = "-intr"; break;
255 } s; }),
256 epnum, buf + offset, len);
257
258 /* Configure endpoint */
259 musb_ep_set_qh(hw_ep, is_in, qh);
260 musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len);
261
262 /* transmit may have more work: start it when it is time */
263 if (is_in)
264 return;
265
266 /* determine if the time is right for a periodic transfer */
267 switch (qh->type) {
268 case USB_ENDPOINT_XFER_ISOC:
269 case USB_ENDPOINT_XFER_INT:
270 dev_dbg(musb->controller, "check whether there's still time for periodic Tx\n");
271 frame = musb_readw(mbase, MUSB_FRAME);
272 /* FIXME this doesn't implement that scheduling policy ...
273 * or handle framecounter wrapping
274 */
275 if (1) { /* Always assume URB_ISO_ASAP */
276 /* REVISIT the SOF irq handler shouldn't duplicate
277 * this code; and we don't init urb->start_frame...
278 */
279 qh->frame = 0;
280 goto start;
281 } else {
282 qh->frame = urb->start_frame;
283 /* enable SOF interrupt so we can count down */
284 dev_dbg(musb->controller, "SOF for %d\n", epnum);
285 #if 1 /* ifndef CONFIG_ARCH_DAVINCI */
286 musb_writeb(mbase, MUSB_INTRUSBE, 0xff);
287 #endif
288 }
289 break;
290 default:
291 start:
292 dev_dbg(musb->controller, "Start TX%d %s\n", epnum,
293 hw_ep->tx_channel ? "dma" : "pio");
294
295 if (!hw_ep->tx_channel)
296 musb_h_tx_start(hw_ep);
297 else if (is_cppi_enabled() || tusb_dma_omap())
298 musb_h_tx_dma_start(hw_ep);
299 }
300 }
301
302 /* Context: caller owns controller lock, IRQs are blocked */
musb_giveback(struct musb * musb,struct urb * urb,int status)303 static void musb_giveback(struct musb *musb, struct urb *urb, int status)
304 __releases(musb->lock)
305 __acquires(musb->lock)
306 {
307 dev_dbg(musb->controller,
308 "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n",
309 urb, urb->complete, status,
310 usb_pipedevice(urb->pipe),
311 usb_pipeendpoint(urb->pipe),
312 usb_pipein(urb->pipe) ? "in" : "out",
313 urb->actual_length, urb->transfer_buffer_length
314 );
315
316 usb_hcd_unlink_urb_from_ep(musb->hcd, urb);
317 spin_unlock(&musb->lock);
318 usb_hcd_giveback_urb(musb->hcd, urb, status);
319 spin_lock(&musb->lock);
320 }
321
322 /* For bulk/interrupt endpoints only */
musb_save_toggle(struct musb_qh * qh,int is_in,struct urb * urb)323 static inline void musb_save_toggle(struct musb_qh *qh, int is_in,
324 struct urb *urb)
325 {
326 void __iomem *epio = qh->hw_ep->regs;
327 u16 csr;
328
329 /*
330 * FIXME: the current Mentor DMA code seems to have
331 * problems getting toggle correct.
332 */
333
334 if (is_in)
335 csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE;
336 else
337 csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE;
338
339 usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0);
340 }
341
342 /*
343 * Advance this hardware endpoint's queue, completing the specified URB and
344 * advancing to either the next URB queued to that qh, or else invalidating
345 * that qh and advancing to the next qh scheduled after the current one.
346 *
347 * Context: caller owns controller lock, IRQs are blocked
348 */
musb_advance_schedule(struct musb * musb,struct urb * urb,struct musb_hw_ep * hw_ep,int is_in)349 static void musb_advance_schedule(struct musb *musb, struct urb *urb,
350 struct musb_hw_ep *hw_ep, int is_in)
351 {
352 struct musb_qh *qh = musb_ep_get_qh(hw_ep, is_in);
353 struct musb_hw_ep *ep = qh->hw_ep;
354 int ready = qh->is_ready;
355 int status;
356
357 status = (urb->status == -EINPROGRESS) ? 0 : urb->status;
358
359 /* save toggle eagerly, for paranoia */
360 switch (qh->type) {
361 case USB_ENDPOINT_XFER_BULK:
362 case USB_ENDPOINT_XFER_INT:
363 musb_save_toggle(qh, is_in, urb);
364 break;
365 case USB_ENDPOINT_XFER_ISOC:
366 if (status == 0 && urb->error_count)
367 status = -EXDEV;
368 break;
369 }
370
371 qh->is_ready = 0;
372 musb_giveback(musb, urb, status);
373 qh->is_ready = ready;
374
375 /* reclaim resources (and bandwidth) ASAP; deschedule it, and
376 * invalidate qh as soon as list_empty(&hep->urb_list)
377 */
378 if (list_empty(&qh->hep->urb_list)) {
379 struct list_head *head;
380 struct dma_controller *dma = musb->dma_controller;
381
382 if (is_in) {
383 ep->rx_reinit = 1;
384 if (ep->rx_channel) {
385 dma->channel_release(ep->rx_channel);
386 ep->rx_channel = NULL;
387 }
388 } else {
389 ep->tx_reinit = 1;
390 if (ep->tx_channel) {
391 dma->channel_release(ep->tx_channel);
392 ep->tx_channel = NULL;
393 }
394 }
395
396 /* Clobber old pointers to this qh */
397 musb_ep_set_qh(ep, is_in, NULL);
398 qh->hep->hcpriv = NULL;
399
400 switch (qh->type) {
401
402 case USB_ENDPOINT_XFER_CONTROL:
403 case USB_ENDPOINT_XFER_BULK:
404 /* fifo policy for these lists, except that NAKing
405 * should rotate a qh to the end (for fairness).
406 */
407 if (qh->mux == 1) {
408 head = qh->ring.prev;
409 list_del(&qh->ring);
410 kfree(qh);
411 qh = first_qh(head);
412 break;
413 }
414
415 case USB_ENDPOINT_XFER_ISOC:
416 case USB_ENDPOINT_XFER_INT:
417 /* this is where periodic bandwidth should be
418 * de-allocated if it's tracked and allocated;
419 * and where we'd update the schedule tree...
420 */
421 kfree(qh);
422 qh = NULL;
423 break;
424 }
425 }
426
427 if (qh != NULL && qh->is_ready) {
428 dev_dbg(musb->controller, "... next ep%d %cX urb %p\n",
429 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
430 musb_start_urb(musb, is_in, qh);
431 }
432 }
433
musb_h_flush_rxfifo(struct musb_hw_ep * hw_ep,u16 csr)434 static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)
435 {
436 /* we don't want fifo to fill itself again;
437 * ignore dma (various models),
438 * leave toggle alone (may not have been saved yet)
439 */
440 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY;
441 csr &= ~(MUSB_RXCSR_H_REQPKT
442 | MUSB_RXCSR_H_AUTOREQ
443 | MUSB_RXCSR_AUTOCLEAR);
444
445 /* write 2x to allow double buffering */
446 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
447 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
448
449 /* flush writebuffer */
450 return musb_readw(hw_ep->regs, MUSB_RXCSR);
451 }
452
453 /*
454 * PIO RX for a packet (or part of it).
455 */
456 static bool
musb_host_packet_rx(struct musb * musb,struct urb * urb,u8 epnum,u8 iso_err)457 musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
458 {
459 u16 rx_count;
460 u8 *buf;
461 u16 csr;
462 bool done = false;
463 u32 length;
464 int do_flush = 0;
465 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
466 void __iomem *epio = hw_ep->regs;
467 struct musb_qh *qh = hw_ep->in_qh;
468 int pipe = urb->pipe;
469 void *buffer = urb->transfer_buffer;
470
471 /* musb_ep_select(mbase, epnum); */
472 rx_count = musb_readw(epio, MUSB_RXCOUNT);
473 dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
474 urb->transfer_buffer, qh->offset,
475 urb->transfer_buffer_length);
476
477 /* unload FIFO */
478 if (usb_pipeisoc(pipe)) {
479 int status = 0;
480 struct usb_iso_packet_descriptor *d;
481
482 if (iso_err) {
483 status = -EILSEQ;
484 urb->error_count++;
485 }
486
487 d = urb->iso_frame_desc + qh->iso_idx;
488 buf = buffer + d->offset;
489 length = d->length;
490 if (rx_count > length) {
491 if (status == 0) {
492 status = -EOVERFLOW;
493 urb->error_count++;
494 }
495 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
496 do_flush = 1;
497 } else
498 length = rx_count;
499 urb->actual_length += length;
500 d->actual_length = length;
501
502 d->status = status;
503
504 /* see if we are done */
505 done = (++qh->iso_idx >= urb->number_of_packets);
506 } else {
507 /* non-isoch */
508 buf = buffer + qh->offset;
509 length = urb->transfer_buffer_length - qh->offset;
510 if (rx_count > length) {
511 if (urb->status == -EINPROGRESS)
512 urb->status = -EOVERFLOW;
513 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
514 do_flush = 1;
515 } else
516 length = rx_count;
517 urb->actual_length += length;
518 qh->offset += length;
519
520 /* see if we are done */
521 done = (urb->actual_length == urb->transfer_buffer_length)
522 || (rx_count < qh->maxpacket)
523 || (urb->status != -EINPROGRESS);
524 if (done
525 && (urb->status == -EINPROGRESS)
526 && (urb->transfer_flags & URB_SHORT_NOT_OK)
527 && (urb->actual_length
528 < urb->transfer_buffer_length))
529 urb->status = -EREMOTEIO;
530 }
531
532 musb_read_fifo(hw_ep, length, buf);
533
534 csr = musb_readw(epio, MUSB_RXCSR);
535 csr |= MUSB_RXCSR_H_WZC_BITS;
536 if (unlikely(do_flush))
537 musb_h_flush_rxfifo(hw_ep, csr);
538 else {
539 /* REVISIT this assumes AUTOCLEAR is never set */
540 csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT);
541 if (!done)
542 csr |= MUSB_RXCSR_H_REQPKT;
543 musb_writew(epio, MUSB_RXCSR, csr);
544 }
545
546 return done;
547 }
548
549 /* we don't always need to reinit a given side of an endpoint...
550 * when we do, use tx/rx reinit routine and then construct a new CSR
551 * to address data toggle, NYET, and DMA or PIO.
552 *
553 * it's possible that driver bugs (especially for DMA) or aborting a
554 * transfer might have left the endpoint busier than it should be.
555 * the busy/not-empty tests are basically paranoia.
556 */
557 static void
musb_rx_reinit(struct musb * musb,struct musb_qh * qh,struct musb_hw_ep * ep)558 musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep)
559 {
560 u16 csr;
561
562 /* NOTE: we know the "rx" fifo reinit never triggers for ep0.
563 * That always uses tx_reinit since ep0 repurposes TX register
564 * offsets; the initial SETUP packet is also a kind of OUT.
565 */
566
567 /* if programmed for Tx, put it in RX mode */
568 if (ep->is_shared_fifo) {
569 csr = musb_readw(ep->regs, MUSB_TXCSR);
570 if (csr & MUSB_TXCSR_MODE) {
571 musb_h_tx_flush_fifo(ep);
572 csr = musb_readw(ep->regs, MUSB_TXCSR);
573 musb_writew(ep->regs, MUSB_TXCSR,
574 csr | MUSB_TXCSR_FRCDATATOG);
575 }
576
577 /*
578 * Clear the MODE bit (and everything else) to enable Rx.
579 * NOTE: we mustn't clear the DMAMODE bit before DMAENAB.
580 */
581 if (csr & MUSB_TXCSR_DMAMODE)
582 musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE);
583 musb_writew(ep->regs, MUSB_TXCSR, 0);
584
585 /* scrub all previous state, clearing toggle */
586 }
587 csr = musb_readw(ep->regs, MUSB_RXCSR);
588 if (csr & MUSB_RXCSR_RXPKTRDY)
589 WARNING("rx%d, packet/%d ready?\n", ep->epnum,
590 musb_readw(ep->regs, MUSB_RXCOUNT));
591
592 musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG);
593
594 /* target addr and (for multipoint) hub addr/port */
595 if (musb->is_multipoint) {
596 musb_write_rxfunaddr(ep->target_regs, qh->addr_reg);
597 musb_write_rxhubaddr(ep->target_regs, qh->h_addr_reg);
598 musb_write_rxhubport(ep->target_regs, qh->h_port_reg);
599
600 } else
601 musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg);
602
603 /* protocol/endpoint, interval/NAKlimit, i/o size */
604 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg);
605 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg);
606 /* NOTE: bulk combining rewrites high bits of maxpacket */
607 /* Set RXMAXP with the FIFO size of the endpoint
608 * to disable double buffer mode.
609 */
610 if (musb->double_buffer_not_ok)
611 musb_writew(ep->regs, MUSB_RXMAXP, ep->max_packet_sz_rx);
612 else
613 musb_writew(ep->regs, MUSB_RXMAXP,
614 qh->maxpacket | ((qh->hb_mult - 1) << 11));
615
616 ep->rx_reinit = 0;
617 }
618
musb_tx_dma_program(struct dma_controller * dma,struct musb_hw_ep * hw_ep,struct musb_qh * qh,struct urb * urb,u32 offset,u32 length)619 static bool musb_tx_dma_program(struct dma_controller *dma,
620 struct musb_hw_ep *hw_ep, struct musb_qh *qh,
621 struct urb *urb, u32 offset, u32 length)
622 {
623 struct dma_channel *channel = hw_ep->tx_channel;
624 void __iomem *epio = hw_ep->regs;
625 u16 pkt_size = qh->maxpacket;
626 u16 csr;
627 u8 mode;
628
629 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
630 if (length > channel->max_len)
631 length = channel->max_len;
632
633 csr = musb_readw(epio, MUSB_TXCSR);
634 if (length > pkt_size) {
635 mode = 1;
636 csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB;
637 /* autoset shouldn't be set in high bandwidth */
638 /*
639 * Enable Autoset according to table
640 * below
641 * bulk_split hb_mult Autoset_Enable
642 * 0 1 Yes(Normal)
643 * 0 >1 No(High BW ISO)
644 * 1 1 Yes(HS bulk)
645 * 1 >1 Yes(FS bulk)
646 */
647 if (qh->hb_mult == 1 || (qh->hb_mult > 1 &&
648 can_bulk_split(hw_ep->musb, qh->type)))
649 csr |= MUSB_TXCSR_AUTOSET;
650 } else {
651 mode = 0;
652 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE);
653 csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */
654 }
655 channel->desired_mode = mode;
656 musb_writew(epio, MUSB_TXCSR, csr);
657 #else
658 if (!is_cppi_enabled() && !tusb_dma_omap())
659 return false;
660
661 channel->actual_len = 0;
662
663 /*
664 * TX uses "RNDIS" mode automatically but needs help
665 * to identify the zero-length-final-packet case.
666 */
667 mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0;
668 #endif
669
670 qh->segsize = length;
671
672 /*
673 * Ensure the data reaches to main memory before starting
674 * DMA transfer
675 */
676 wmb();
677
678 if (!dma->channel_program(channel, pkt_size, mode,
679 urb->transfer_dma + offset, length)) {
680 dma->channel_release(channel);
681 hw_ep->tx_channel = NULL;
682
683 csr = musb_readw(epio, MUSB_TXCSR);
684 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
685 musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS);
686 return false;
687 }
688 return true;
689 }
690
691 /*
692 * Program an HDRC endpoint as per the given URB
693 * Context: irqs blocked, controller lock held
694 */
musb_ep_program(struct musb * musb,u8 epnum,struct urb * urb,int is_out,u8 * buf,u32 offset,u32 len)695 static void musb_ep_program(struct musb *musb, u8 epnum,
696 struct urb *urb, int is_out,
697 u8 *buf, u32 offset, u32 len)
698 {
699 struct dma_controller *dma_controller;
700 struct dma_channel *dma_channel;
701 u8 dma_ok;
702 void __iomem *mbase = musb->mregs;
703 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
704 void __iomem *epio = hw_ep->regs;
705 struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out);
706 u16 packet_sz = qh->maxpacket;
707 u8 use_dma = 1;
708 u16 csr;
709
710 dev_dbg(musb->controller, "%s hw%d urb %p spd%d dev%d ep%d%s "
711 "h_addr%02x h_port%02x bytes %d\n",
712 is_out ? "-->" : "<--",
713 epnum, urb, urb->dev->speed,
714 qh->addr_reg, qh->epnum, is_out ? "out" : "in",
715 qh->h_addr_reg, qh->h_port_reg,
716 len);
717
718 musb_ep_select(mbase, epnum);
719
720 if (is_out && !len) {
721 use_dma = 0;
722 csr = musb_readw(epio, MUSB_TXCSR);
723 csr &= ~MUSB_TXCSR_DMAENAB;
724 musb_writew(epio, MUSB_TXCSR, csr);
725 hw_ep->tx_channel = NULL;
726 }
727
728 /* candidate for DMA? */
729 dma_controller = musb->dma_controller;
730 if (use_dma && is_dma_capable() && epnum && dma_controller) {
731 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel;
732 if (!dma_channel) {
733 dma_channel = dma_controller->channel_alloc(
734 dma_controller, hw_ep, is_out);
735 if (is_out)
736 hw_ep->tx_channel = dma_channel;
737 else
738 hw_ep->rx_channel = dma_channel;
739 }
740 } else
741 dma_channel = NULL;
742
743 /* make sure we clear DMAEnab, autoSet bits from previous run */
744
745 /* OUT/transmit/EP0 or IN/receive? */
746 if (is_out) {
747 u16 csr;
748 u16 int_txe;
749 u16 load_count;
750
751 csr = musb_readw(epio, MUSB_TXCSR);
752
753 /* disable interrupt in case we flush */
754 int_txe = musb->intrtxe;
755 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
756
757 /* general endpoint setup */
758 if (epnum) {
759 /* flush all old state, set default */
760 /*
761 * We could be flushing valid
762 * packets in double buffering
763 * case
764 */
765 if (!hw_ep->tx_double_buffered)
766 musb_h_tx_flush_fifo(hw_ep);
767
768 /*
769 * We must not clear the DMAMODE bit before or in
770 * the same cycle with the DMAENAB bit, so we clear
771 * the latter first...
772 */
773 csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT
774 | MUSB_TXCSR_AUTOSET
775 | MUSB_TXCSR_DMAENAB
776 | MUSB_TXCSR_FRCDATATOG
777 | MUSB_TXCSR_H_RXSTALL
778 | MUSB_TXCSR_H_ERROR
779 | MUSB_TXCSR_TXPKTRDY
780 );
781 csr |= MUSB_TXCSR_MODE;
782
783 if (!hw_ep->tx_double_buffered) {
784 if (usb_gettoggle(urb->dev, qh->epnum, 1))
785 csr |= MUSB_TXCSR_H_WR_DATATOGGLE
786 | MUSB_TXCSR_H_DATATOGGLE;
787 else
788 csr |= MUSB_TXCSR_CLRDATATOG;
789 }
790
791 musb_writew(epio, MUSB_TXCSR, csr);
792 /* REVISIT may need to clear FLUSHFIFO ... */
793 csr &= ~MUSB_TXCSR_DMAMODE;
794 musb_writew(epio, MUSB_TXCSR, csr);
795 csr = musb_readw(epio, MUSB_TXCSR);
796 } else {
797 /* endpoint 0: just flush */
798 musb_h_ep0_flush_fifo(hw_ep);
799 }
800
801 /* target addr and (for multipoint) hub addr/port */
802 if (musb->is_multipoint) {
803 musb_write_txfunaddr(mbase, epnum, qh->addr_reg);
804 musb_write_txhubaddr(mbase, epnum, qh->h_addr_reg);
805 musb_write_txhubport(mbase, epnum, qh->h_port_reg);
806 /* FIXME if !epnum, do the same for RX ... */
807 } else
808 musb_writeb(mbase, MUSB_FADDR, qh->addr_reg);
809
810 /* protocol/endpoint/interval/NAKlimit */
811 if (epnum) {
812 musb_writeb(epio, MUSB_TXTYPE, qh->type_reg);
813 if (musb->double_buffer_not_ok) {
814 musb_writew(epio, MUSB_TXMAXP,
815 hw_ep->max_packet_sz_tx);
816 } else if (can_bulk_split(musb, qh->type)) {
817 qh->hb_mult = hw_ep->max_packet_sz_tx
818 / packet_sz;
819 musb_writew(epio, MUSB_TXMAXP, packet_sz
820 | ((qh->hb_mult) - 1) << 11);
821 } else {
822 musb_writew(epio, MUSB_TXMAXP,
823 qh->maxpacket |
824 ((qh->hb_mult - 1) << 11));
825 }
826 musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg);
827 } else {
828 musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg);
829 if (musb->is_multipoint)
830 musb_writeb(epio, MUSB_TYPE0,
831 qh->type_reg);
832 }
833
834 if (can_bulk_split(musb, qh->type))
835 load_count = min((u32) hw_ep->max_packet_sz_tx,
836 len);
837 else
838 load_count = min((u32) packet_sz, len);
839
840 if (dma_channel && musb_tx_dma_program(dma_controller,
841 hw_ep, qh, urb, offset, len))
842 load_count = 0;
843
844 if (load_count) {
845 /* PIO to load FIFO */
846 qh->segsize = load_count;
847 if (!buf) {
848 sg_miter_start(&qh->sg_miter, urb->sg, 1,
849 SG_MITER_ATOMIC
850 | SG_MITER_FROM_SG);
851 if (!sg_miter_next(&qh->sg_miter)) {
852 dev_err(musb->controller,
853 "error: sg"
854 "list empty\n");
855 sg_miter_stop(&qh->sg_miter);
856 goto finish;
857 }
858 buf = qh->sg_miter.addr + urb->sg->offset +
859 urb->actual_length;
860 load_count = min_t(u32, load_count,
861 qh->sg_miter.length);
862 musb_write_fifo(hw_ep, load_count, buf);
863 qh->sg_miter.consumed = load_count;
864 sg_miter_stop(&qh->sg_miter);
865 } else
866 musb_write_fifo(hw_ep, load_count, buf);
867 }
868 finish:
869 /* re-enable interrupt */
870 musb_writew(mbase, MUSB_INTRTXE, int_txe);
871
872 /* IN/receive */
873 } else {
874 u16 csr;
875
876 if (hw_ep->rx_reinit) {
877 musb_rx_reinit(musb, qh, hw_ep);
878
879 /* init new state: toggle and NYET, maybe DMA later */
880 if (usb_gettoggle(urb->dev, qh->epnum, 0))
881 csr = MUSB_RXCSR_H_WR_DATATOGGLE
882 | MUSB_RXCSR_H_DATATOGGLE;
883 else
884 csr = 0;
885 if (qh->type == USB_ENDPOINT_XFER_INT)
886 csr |= MUSB_RXCSR_DISNYET;
887
888 } else {
889 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
890
891 if (csr & (MUSB_RXCSR_RXPKTRDY
892 | MUSB_RXCSR_DMAENAB
893 | MUSB_RXCSR_H_REQPKT))
894 ERR("broken !rx_reinit, ep%d csr %04x\n",
895 hw_ep->epnum, csr);
896
897 /* scrub any stale state, leaving toggle alone */
898 csr &= MUSB_RXCSR_DISNYET;
899 }
900
901 /* kick things off */
902
903 if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) {
904 /* Candidate for DMA */
905 dma_channel->actual_len = 0L;
906 qh->segsize = len;
907
908 /* AUTOREQ is in a DMA register */
909 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
910 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
911
912 /*
913 * Unless caller treats short RX transfers as
914 * errors, we dare not queue multiple transfers.
915 */
916 dma_ok = dma_controller->channel_program(dma_channel,
917 packet_sz, !(urb->transfer_flags &
918 URB_SHORT_NOT_OK),
919 urb->transfer_dma + offset,
920 qh->segsize);
921 if (!dma_ok) {
922 dma_controller->channel_release(dma_channel);
923 hw_ep->rx_channel = dma_channel = NULL;
924 } else
925 csr |= MUSB_RXCSR_DMAENAB;
926 }
927
928 csr |= MUSB_RXCSR_H_REQPKT;
929 dev_dbg(musb->controller, "RXCSR%d := %04x\n", epnum, csr);
930 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
931 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
932 }
933 }
934
935 /* Schedule next QH from musb->in_bulk/out_bulk and move the current qh to
936 * the end; avoids starvation for other endpoints.
937 */
musb_bulk_nak_timeout(struct musb * musb,struct musb_hw_ep * ep,int is_in)938 static void musb_bulk_nak_timeout(struct musb *musb, struct musb_hw_ep *ep,
939 int is_in)
940 {
941 struct dma_channel *dma;
942 struct urb *urb;
943 void __iomem *mbase = musb->mregs;
944 void __iomem *epio = ep->regs;
945 struct musb_qh *cur_qh, *next_qh;
946 u16 rx_csr, tx_csr;
947
948 musb_ep_select(mbase, ep->epnum);
949 if (is_in) {
950 dma = is_dma_capable() ? ep->rx_channel : NULL;
951
952 /*
953 * Need to stop the transaction by clearing REQPKT first
954 * then the NAK Timeout bit ref MUSBMHDRC USB 2.0 HIGH-SPEED
955 * DUAL-ROLE CONTROLLER Programmer's Guide, section 9.2.2
956 */
957 rx_csr = musb_readw(epio, MUSB_RXCSR);
958 rx_csr |= MUSB_RXCSR_H_WZC_BITS;
959 rx_csr &= ~MUSB_RXCSR_H_REQPKT;
960 musb_writew(epio, MUSB_RXCSR, rx_csr);
961 rx_csr &= ~MUSB_RXCSR_DATAERROR;
962 musb_writew(epio, MUSB_RXCSR, rx_csr);
963
964 cur_qh = first_qh(&musb->in_bulk);
965 } else {
966 dma = is_dma_capable() ? ep->tx_channel : NULL;
967
968 /* clear nak timeout bit */
969 tx_csr = musb_readw(epio, MUSB_TXCSR);
970 tx_csr |= MUSB_TXCSR_H_WZC_BITS;
971 tx_csr &= ~MUSB_TXCSR_H_NAKTIMEOUT;
972 musb_writew(epio, MUSB_TXCSR, tx_csr);
973
974 cur_qh = first_qh(&musb->out_bulk);
975 }
976 if (cur_qh) {
977 urb = next_urb(cur_qh);
978 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
979 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
980 musb->dma_controller->channel_abort(dma);
981 urb->actual_length += dma->actual_len;
982 dma->actual_len = 0L;
983 }
984 musb_save_toggle(cur_qh, is_in, urb);
985
986 if (is_in) {
987 /* move cur_qh to end of queue */
988 list_move_tail(&cur_qh->ring, &musb->in_bulk);
989
990 /* get the next qh from musb->in_bulk */
991 next_qh = first_qh(&musb->in_bulk);
992
993 /* set rx_reinit and schedule the next qh */
994 ep->rx_reinit = 1;
995 } else {
996 /* move cur_qh to end of queue */
997 list_move_tail(&cur_qh->ring, &musb->out_bulk);
998
999 /* get the next qh from musb->out_bulk */
1000 next_qh = first_qh(&musb->out_bulk);
1001
1002 /* set tx_reinit and schedule the next qh */
1003 ep->tx_reinit = 1;
1004 }
1005 musb_start_urb(musb, is_in, next_qh);
1006 }
1007 }
1008
1009 /*
1010 * Service the default endpoint (ep0) as host.
1011 * Return true until it's time to start the status stage.
1012 */
musb_h_ep0_continue(struct musb * musb,u16 len,struct urb * urb)1013 static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb)
1014 {
1015 bool more = false;
1016 u8 *fifo_dest = NULL;
1017 u16 fifo_count = 0;
1018 struct musb_hw_ep *hw_ep = musb->control_ep;
1019 struct musb_qh *qh = hw_ep->in_qh;
1020 struct usb_ctrlrequest *request;
1021
1022 switch (musb->ep0_stage) {
1023 case MUSB_EP0_IN:
1024 fifo_dest = urb->transfer_buffer + urb->actual_length;
1025 fifo_count = min_t(size_t, len, urb->transfer_buffer_length -
1026 urb->actual_length);
1027 if (fifo_count < len)
1028 urb->status = -EOVERFLOW;
1029
1030 musb_read_fifo(hw_ep, fifo_count, fifo_dest);
1031
1032 urb->actual_length += fifo_count;
1033 if (len < qh->maxpacket) {
1034 /* always terminate on short read; it's
1035 * rarely reported as an error.
1036 */
1037 } else if (urb->actual_length <
1038 urb->transfer_buffer_length)
1039 more = true;
1040 break;
1041 case MUSB_EP0_START:
1042 request = (struct usb_ctrlrequest *) urb->setup_packet;
1043
1044 if (!request->wLength) {
1045 dev_dbg(musb->controller, "start no-DATA\n");
1046 break;
1047 } else if (request->bRequestType & USB_DIR_IN) {
1048 dev_dbg(musb->controller, "start IN-DATA\n");
1049 musb->ep0_stage = MUSB_EP0_IN;
1050 more = true;
1051 break;
1052 } else {
1053 dev_dbg(musb->controller, "start OUT-DATA\n");
1054 musb->ep0_stage = MUSB_EP0_OUT;
1055 more = true;
1056 }
1057 /* FALLTHROUGH */
1058 case MUSB_EP0_OUT:
1059 fifo_count = min_t(size_t, qh->maxpacket,
1060 urb->transfer_buffer_length -
1061 urb->actual_length);
1062 if (fifo_count) {
1063 fifo_dest = (u8 *) (urb->transfer_buffer
1064 + urb->actual_length);
1065 dev_dbg(musb->controller, "Sending %d byte%s to ep0 fifo %p\n",
1066 fifo_count,
1067 (fifo_count == 1) ? "" : "s",
1068 fifo_dest);
1069 musb_write_fifo(hw_ep, fifo_count, fifo_dest);
1070
1071 urb->actual_length += fifo_count;
1072 more = true;
1073 }
1074 break;
1075 default:
1076 ERR("bogus ep0 stage %d\n", musb->ep0_stage);
1077 break;
1078 }
1079
1080 return more;
1081 }
1082
1083 /*
1084 * Handle default endpoint interrupt as host. Only called in IRQ time
1085 * from musb_interrupt().
1086 *
1087 * called with controller irqlocked
1088 */
musb_h_ep0_irq(struct musb * musb)1089 irqreturn_t musb_h_ep0_irq(struct musb *musb)
1090 {
1091 struct urb *urb;
1092 u16 csr, len;
1093 int status = 0;
1094 void __iomem *mbase = musb->mregs;
1095 struct musb_hw_ep *hw_ep = musb->control_ep;
1096 void __iomem *epio = hw_ep->regs;
1097 struct musb_qh *qh = hw_ep->in_qh;
1098 bool complete = false;
1099 irqreturn_t retval = IRQ_NONE;
1100
1101 /* ep0 only has one queue, "in" */
1102 urb = next_urb(qh);
1103
1104 musb_ep_select(mbase, 0);
1105 csr = musb_readw(epio, MUSB_CSR0);
1106 len = (csr & MUSB_CSR0_RXPKTRDY)
1107 ? musb_readb(epio, MUSB_COUNT0)
1108 : 0;
1109
1110 dev_dbg(musb->controller, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
1111 csr, qh, len, urb, musb->ep0_stage);
1112
1113 /* if we just did status stage, we are done */
1114 if (MUSB_EP0_STATUS == musb->ep0_stage) {
1115 retval = IRQ_HANDLED;
1116 complete = true;
1117 }
1118
1119 /* prepare status */
1120 if (csr & MUSB_CSR0_H_RXSTALL) {
1121 dev_dbg(musb->controller, "STALLING ENDPOINT\n");
1122 status = -EPIPE;
1123
1124 } else if (csr & MUSB_CSR0_H_ERROR) {
1125 dev_dbg(musb->controller, "no response, csr0 %04x\n", csr);
1126 status = -EPROTO;
1127
1128 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) {
1129 dev_dbg(musb->controller, "control NAK timeout\n");
1130
1131 /* NOTE: this code path would be a good place to PAUSE a
1132 * control transfer, if another one is queued, so that
1133 * ep0 is more likely to stay busy. That's already done
1134 * for bulk RX transfers.
1135 *
1136 * if (qh->ring.next != &musb->control), then
1137 * we have a candidate... NAKing is *NOT* an error
1138 */
1139 musb_writew(epio, MUSB_CSR0, 0);
1140 retval = IRQ_HANDLED;
1141 }
1142
1143 if (status) {
1144 dev_dbg(musb->controller, "aborting\n");
1145 retval = IRQ_HANDLED;
1146 if (urb)
1147 urb->status = status;
1148 complete = true;
1149
1150 /* use the proper sequence to abort the transfer */
1151 if (csr & MUSB_CSR0_H_REQPKT) {
1152 csr &= ~MUSB_CSR0_H_REQPKT;
1153 musb_writew(epio, MUSB_CSR0, csr);
1154 csr &= ~MUSB_CSR0_H_NAKTIMEOUT;
1155 musb_writew(epio, MUSB_CSR0, csr);
1156 } else {
1157 musb_h_ep0_flush_fifo(hw_ep);
1158 }
1159
1160 musb_writeb(epio, MUSB_NAKLIMIT0, 0);
1161
1162 /* clear it */
1163 musb_writew(epio, MUSB_CSR0, 0);
1164 }
1165
1166 if (unlikely(!urb)) {
1167 /* stop endpoint since we have no place for its data, this
1168 * SHOULD NEVER HAPPEN! */
1169 ERR("no URB for end 0\n");
1170
1171 musb_h_ep0_flush_fifo(hw_ep);
1172 goto done;
1173 }
1174
1175 if (!complete) {
1176 /* call common logic and prepare response */
1177 if (musb_h_ep0_continue(musb, len, urb)) {
1178 /* more packets required */
1179 csr = (MUSB_EP0_IN == musb->ep0_stage)
1180 ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY;
1181 } else {
1182 /* data transfer complete; perform status phase */
1183 if (usb_pipeout(urb->pipe)
1184 || !urb->transfer_buffer_length)
1185 csr = MUSB_CSR0_H_STATUSPKT
1186 | MUSB_CSR0_H_REQPKT;
1187 else
1188 csr = MUSB_CSR0_H_STATUSPKT
1189 | MUSB_CSR0_TXPKTRDY;
1190
1191 /* disable ping token in status phase */
1192 csr |= MUSB_CSR0_H_DIS_PING;
1193
1194 /* flag status stage */
1195 musb->ep0_stage = MUSB_EP0_STATUS;
1196
1197 dev_dbg(musb->controller, "ep0 STATUS, csr %04x\n", csr);
1198
1199 }
1200 musb_writew(epio, MUSB_CSR0, csr);
1201 retval = IRQ_HANDLED;
1202 } else
1203 musb->ep0_stage = MUSB_EP0_IDLE;
1204
1205 /* call completion handler if done */
1206 if (complete)
1207 musb_advance_schedule(musb, urb, hw_ep, 1);
1208 done:
1209 return retval;
1210 }
1211
1212
1213 #ifdef CONFIG_USB_INVENTRA_DMA
1214
1215 /* Host side TX (OUT) using Mentor DMA works as follows:
1216 submit_urb ->
1217 - if queue was empty, Program Endpoint
1218 - ... which starts DMA to fifo in mode 1 or 0
1219
1220 DMA Isr (transfer complete) -> TxAvail()
1221 - Stop DMA (~DmaEnab) (<--- Alert ... currently happens
1222 only in musb_cleanup_urb)
1223 - TxPktRdy has to be set in mode 0 or for
1224 short packets in mode 1.
1225 */
1226
1227 #endif
1228
1229 /* Service a Tx-Available or dma completion irq for the endpoint */
musb_host_tx(struct musb * musb,u8 epnum)1230 void musb_host_tx(struct musb *musb, u8 epnum)
1231 {
1232 int pipe;
1233 bool done = false;
1234 u16 tx_csr;
1235 size_t length = 0;
1236 size_t offset = 0;
1237 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1238 void __iomem *epio = hw_ep->regs;
1239 struct musb_qh *qh = hw_ep->out_qh;
1240 struct urb *urb = next_urb(qh);
1241 u32 status = 0;
1242 void __iomem *mbase = musb->mregs;
1243 struct dma_channel *dma;
1244 bool transfer_pending = false;
1245
1246 musb_ep_select(mbase, epnum);
1247 tx_csr = musb_readw(epio, MUSB_TXCSR);
1248
1249 /* with CPPI, DMA sometimes triggers "extra" irqs */
1250 if (!urb) {
1251 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1252 return;
1253 }
1254
1255 pipe = urb->pipe;
1256 dma = is_dma_capable() ? hw_ep->tx_channel : NULL;
1257 dev_dbg(musb->controller, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr,
1258 dma ? ", dma" : "");
1259
1260 /* check for errors */
1261 if (tx_csr & MUSB_TXCSR_H_RXSTALL) {
1262 /* dma was disabled, fifo flushed */
1263 dev_dbg(musb->controller, "TX end %d stall\n", epnum);
1264
1265 /* stall; record URB status */
1266 status = -EPIPE;
1267
1268 } else if (tx_csr & MUSB_TXCSR_H_ERROR) {
1269 /* (NON-ISO) dma was disabled, fifo flushed */
1270 dev_dbg(musb->controller, "TX 3strikes on ep=%d\n", epnum);
1271
1272 status = -ETIMEDOUT;
1273
1274 } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {
1275 if (USB_ENDPOINT_XFER_BULK == qh->type && qh->mux == 1
1276 && !list_is_singular(&musb->out_bulk)) {
1277 dev_dbg(musb->controller,
1278 "NAK timeout on TX%d ep\n", epnum);
1279 musb_bulk_nak_timeout(musb, hw_ep, 0);
1280 } else {
1281 dev_dbg(musb->controller,
1282 "TX end=%d device not responding\n", epnum);
1283 /* NOTE: this code path would be a good place to PAUSE a
1284 * transfer, if there's some other (nonperiodic) tx urb
1285 * that could use this fifo. (dma complicates it...)
1286 * That's already done for bulk RX transfers.
1287 *
1288 * if (bulk && qh->ring.next != &musb->out_bulk), then
1289 * we have a candidate... NAKing is *NOT* an error
1290 */
1291 musb_ep_select(mbase, epnum);
1292 musb_writew(epio, MUSB_TXCSR,
1293 MUSB_TXCSR_H_WZC_BITS
1294 | MUSB_TXCSR_TXPKTRDY);
1295 }
1296 return;
1297 }
1298
1299 done:
1300 if (status) {
1301 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1302 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1303 musb->dma_controller->channel_abort(dma);
1304 }
1305
1306 /* do the proper sequence to abort the transfer in the
1307 * usb core; the dma engine should already be stopped.
1308 */
1309 musb_h_tx_flush_fifo(hw_ep);
1310 tx_csr &= ~(MUSB_TXCSR_AUTOSET
1311 | MUSB_TXCSR_DMAENAB
1312 | MUSB_TXCSR_H_ERROR
1313 | MUSB_TXCSR_H_RXSTALL
1314 | MUSB_TXCSR_H_NAKTIMEOUT
1315 );
1316
1317 musb_ep_select(mbase, epnum);
1318 musb_writew(epio, MUSB_TXCSR, tx_csr);
1319 /* REVISIT may need to clear FLUSHFIFO ... */
1320 musb_writew(epio, MUSB_TXCSR, tx_csr);
1321 musb_writeb(epio, MUSB_TXINTERVAL, 0);
1322
1323 done = true;
1324 }
1325
1326 /* second cppi case */
1327 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1328 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1329 return;
1330 }
1331
1332 if (is_dma_capable() && dma && !status) {
1333 /*
1334 * DMA has completed. But if we're using DMA mode 1 (multi
1335 * packet DMA), we need a terminal TXPKTRDY interrupt before
1336 * we can consider this transfer completed, lest we trash
1337 * its last packet when writing the next URB's data. So we
1338 * switch back to mode 0 to get that interrupt; we'll come
1339 * back here once it happens.
1340 */
1341 if (tx_csr & MUSB_TXCSR_DMAMODE) {
1342 /*
1343 * We shouldn't clear DMAMODE with DMAENAB set; so
1344 * clear them in a safe order. That should be OK
1345 * once TXPKTRDY has been set (and I've never seen
1346 * it being 0 at this moment -- DMA interrupt latency
1347 * is significant) but if it hasn't been then we have
1348 * no choice but to stop being polite and ignore the
1349 * programmer's guide... :-)
1350 *
1351 * Note that we must write TXCSR with TXPKTRDY cleared
1352 * in order not to re-trigger the packet send (this bit
1353 * can't be cleared by CPU), and there's another caveat:
1354 * TXPKTRDY may be set shortly and then cleared in the
1355 * double-buffered FIFO mode, so we do an extra TXCSR
1356 * read for debouncing...
1357 */
1358 tx_csr &= musb_readw(epio, MUSB_TXCSR);
1359 if (tx_csr & MUSB_TXCSR_TXPKTRDY) {
1360 tx_csr &= ~(MUSB_TXCSR_DMAENAB |
1361 MUSB_TXCSR_TXPKTRDY);
1362 musb_writew(epio, MUSB_TXCSR,
1363 tx_csr | MUSB_TXCSR_H_WZC_BITS);
1364 }
1365 tx_csr &= ~(MUSB_TXCSR_DMAMODE |
1366 MUSB_TXCSR_TXPKTRDY);
1367 musb_writew(epio, MUSB_TXCSR,
1368 tx_csr | MUSB_TXCSR_H_WZC_BITS);
1369
1370 /*
1371 * There is no guarantee that we'll get an interrupt
1372 * after clearing DMAMODE as we might have done this
1373 * too late (after TXPKTRDY was cleared by controller).
1374 * Re-read TXCSR as we have spoiled its previous value.
1375 */
1376 tx_csr = musb_readw(epio, MUSB_TXCSR);
1377 }
1378
1379 /*
1380 * We may get here from a DMA completion or TXPKTRDY interrupt.
1381 * In any case, we must check the FIFO status here and bail out
1382 * only if the FIFO still has data -- that should prevent the
1383 * "missed" TXPKTRDY interrupts and deal with double-buffered
1384 * FIFO mode too...
1385 */
1386 if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) {
1387 dev_dbg(musb->controller, "DMA complete but packet still in FIFO, "
1388 "CSR %04x\n", tx_csr);
1389 return;
1390 }
1391 }
1392
1393 if (!status || dma || usb_pipeisoc(pipe)) {
1394 if (dma)
1395 length = dma->actual_len;
1396 else
1397 length = qh->segsize;
1398 qh->offset += length;
1399
1400 if (usb_pipeisoc(pipe)) {
1401 struct usb_iso_packet_descriptor *d;
1402
1403 d = urb->iso_frame_desc + qh->iso_idx;
1404 d->actual_length = length;
1405 d->status = status;
1406 if (++qh->iso_idx >= urb->number_of_packets) {
1407 done = true;
1408 } else {
1409 d++;
1410 offset = d->offset;
1411 length = d->length;
1412 }
1413 } else if (dma && urb->transfer_buffer_length == qh->offset) {
1414 done = true;
1415 } else {
1416 /* see if we need to send more data, or ZLP */
1417 if (qh->segsize < qh->maxpacket)
1418 done = true;
1419 else if (qh->offset == urb->transfer_buffer_length
1420 && !(urb->transfer_flags
1421 & URB_ZERO_PACKET))
1422 done = true;
1423 if (!done) {
1424 offset = qh->offset;
1425 length = urb->transfer_buffer_length - offset;
1426 transfer_pending = true;
1427 }
1428 }
1429 }
1430
1431 /* urb->status != -EINPROGRESS means request has been faulted,
1432 * so we must abort this transfer after cleanup
1433 */
1434 if (urb->status != -EINPROGRESS) {
1435 done = true;
1436 if (status == 0)
1437 status = urb->status;
1438 }
1439
1440 if (done) {
1441 /* set status */
1442 urb->status = status;
1443 urb->actual_length = qh->offset;
1444 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT);
1445 return;
1446 } else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) {
1447 if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb,
1448 offset, length)) {
1449 if (is_cppi_enabled() || tusb_dma_omap())
1450 musb_h_tx_dma_start(hw_ep);
1451 return;
1452 }
1453 } else if (tx_csr & MUSB_TXCSR_DMAENAB) {
1454 dev_dbg(musb->controller, "not complete, but DMA enabled?\n");
1455 return;
1456 }
1457
1458 /*
1459 * PIO: start next packet in this URB.
1460 *
1461 * REVISIT: some docs say that when hw_ep->tx_double_buffered,
1462 * (and presumably, FIFO is not half-full) we should write *two*
1463 * packets before updating TXCSR; other docs disagree...
1464 */
1465 if (length > qh->maxpacket)
1466 length = qh->maxpacket;
1467 /* Unmap the buffer so that CPU can use it */
1468 usb_hcd_unmap_urb_for_dma(musb->hcd, urb);
1469
1470 /*
1471 * We need to map sg if the transfer_buffer is
1472 * NULL.
1473 */
1474 if (!urb->transfer_buffer)
1475 qh->use_sg = true;
1476
1477 if (qh->use_sg) {
1478 /* sg_miter_start is already done in musb_ep_program */
1479 if (!sg_miter_next(&qh->sg_miter)) {
1480 dev_err(musb->controller, "error: sg list empty\n");
1481 sg_miter_stop(&qh->sg_miter);
1482 status = -EINVAL;
1483 goto done;
1484 }
1485 urb->transfer_buffer = qh->sg_miter.addr;
1486 length = min_t(u32, length, qh->sg_miter.length);
1487 musb_write_fifo(hw_ep, length, urb->transfer_buffer);
1488 qh->sg_miter.consumed = length;
1489 sg_miter_stop(&qh->sg_miter);
1490 } else {
1491 musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset);
1492 }
1493
1494 qh->segsize = length;
1495
1496 if (qh->use_sg) {
1497 if (offset + length >= urb->transfer_buffer_length)
1498 qh->use_sg = false;
1499 }
1500
1501 musb_ep_select(mbase, epnum);
1502 musb_writew(epio, MUSB_TXCSR,
1503 MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY);
1504 }
1505
1506
1507 #ifdef CONFIG_USB_INVENTRA_DMA
1508
1509 /* Host side RX (IN) using Mentor DMA works as follows:
1510 submit_urb ->
1511 - if queue was empty, ProgramEndpoint
1512 - first IN token is sent out (by setting ReqPkt)
1513 LinuxIsr -> RxReady()
1514 /\ => first packet is received
1515 | - Set in mode 0 (DmaEnab, ~ReqPkt)
1516 | -> DMA Isr (transfer complete) -> RxReady()
1517 | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab)
1518 | - if urb not complete, send next IN token (ReqPkt)
1519 | | else complete urb.
1520 | |
1521 ---------------------------
1522 *
1523 * Nuances of mode 1:
1524 * For short packets, no ack (+RxPktRdy) is sent automatically
1525 * (even if AutoClear is ON)
1526 * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent
1527 * automatically => major problem, as collecting the next packet becomes
1528 * difficult. Hence mode 1 is not used.
1529 *
1530 * REVISIT
1531 * All we care about at this driver level is that
1532 * (a) all URBs terminate with REQPKT cleared and fifo(s) empty;
1533 * (b) termination conditions are: short RX, or buffer full;
1534 * (c) fault modes include
1535 * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO.
1536 * (and that endpoint's dma queue stops immediately)
1537 * - overflow (full, PLUS more bytes in the terminal packet)
1538 *
1539 * So for example, usb-storage sets URB_SHORT_NOT_OK, and would
1540 * thus be a great candidate for using mode 1 ... for all but the
1541 * last packet of one URB's transfer.
1542 */
1543
1544 #endif
1545
1546 /*
1547 * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso,
1548 * and high-bandwidth IN transfer cases.
1549 */
musb_host_rx(struct musb * musb,u8 epnum)1550 void musb_host_rx(struct musb *musb, u8 epnum)
1551 {
1552 struct urb *urb;
1553 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1554 void __iomem *epio = hw_ep->regs;
1555 struct musb_qh *qh = hw_ep->in_qh;
1556 size_t xfer_len;
1557 void __iomem *mbase = musb->mregs;
1558 int pipe;
1559 u16 rx_csr, val;
1560 bool iso_err = false;
1561 bool done = false;
1562 u32 status;
1563 struct dma_channel *dma;
1564 unsigned int sg_flags = SG_MITER_ATOMIC | SG_MITER_TO_SG;
1565
1566 musb_ep_select(mbase, epnum);
1567
1568 urb = next_urb(qh);
1569 dma = is_dma_capable() ? hw_ep->rx_channel : NULL;
1570 status = 0;
1571 xfer_len = 0;
1572
1573 rx_csr = musb_readw(epio, MUSB_RXCSR);
1574 val = rx_csr;
1575
1576 if (unlikely(!urb)) {
1577 /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least
1578 * usbtest #11 (unlinks) triggers it regularly, sometimes
1579 * with fifo full. (Only with DMA??)
1580 */
1581 dev_dbg(musb->controller, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val,
1582 musb_readw(epio, MUSB_RXCOUNT));
1583 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1584 return;
1585 }
1586
1587 pipe = urb->pipe;
1588
1589 dev_dbg(musb->controller, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n",
1590 epnum, rx_csr, urb->actual_length,
1591 dma ? dma->actual_len : 0);
1592
1593 /* check for errors, concurrent stall & unlink is not really
1594 * handled yet! */
1595 if (rx_csr & MUSB_RXCSR_H_RXSTALL) {
1596 dev_dbg(musb->controller, "RX end %d STALL\n", epnum);
1597
1598 /* stall; record URB status */
1599 status = -EPIPE;
1600
1601 } else if (rx_csr & MUSB_RXCSR_H_ERROR) {
1602 dev_dbg(musb->controller, "end %d RX proto error\n", epnum);
1603
1604 status = -EPROTO;
1605 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1606
1607 } else if (rx_csr & MUSB_RXCSR_DATAERROR) {
1608
1609 if (USB_ENDPOINT_XFER_ISOC != qh->type) {
1610 dev_dbg(musb->controller, "RX end %d NAK timeout\n", epnum);
1611
1612 /* NOTE: NAKing is *NOT* an error, so we want to
1613 * continue. Except ... if there's a request for
1614 * another QH, use that instead of starving it.
1615 *
1616 * Devices like Ethernet and serial adapters keep
1617 * reads posted at all times, which will starve
1618 * other devices without this logic.
1619 */
1620 if (usb_pipebulk(urb->pipe)
1621 && qh->mux == 1
1622 && !list_is_singular(&musb->in_bulk)) {
1623 musb_bulk_nak_timeout(musb, hw_ep, 1);
1624 return;
1625 }
1626 musb_ep_select(mbase, epnum);
1627 rx_csr |= MUSB_RXCSR_H_WZC_BITS;
1628 rx_csr &= ~MUSB_RXCSR_DATAERROR;
1629 musb_writew(epio, MUSB_RXCSR, rx_csr);
1630
1631 goto finish;
1632 } else {
1633 dev_dbg(musb->controller, "RX end %d ISO data error\n", epnum);
1634 /* packet error reported later */
1635 iso_err = true;
1636 }
1637 } else if (rx_csr & MUSB_RXCSR_INCOMPRX) {
1638 dev_dbg(musb->controller, "end %d high bandwidth incomplete ISO packet RX\n",
1639 epnum);
1640 status = -EPROTO;
1641 }
1642
1643 /* faults abort the transfer */
1644 if (status) {
1645 /* clean up dma and collect transfer count */
1646 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1647 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1648 musb->dma_controller->channel_abort(dma);
1649 xfer_len = dma->actual_len;
1650 }
1651 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1652 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1653 done = true;
1654 goto finish;
1655 }
1656
1657 if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) {
1658 /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */
1659 ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr);
1660 goto finish;
1661 }
1662
1663 /* thorough shutdown for now ... given more precise fault handling
1664 * and better queueing support, we might keep a DMA pipeline going
1665 * while processing this irq for earlier completions.
1666 */
1667
1668 /* FIXME this is _way_ too much in-line logic for Mentor DMA */
1669
1670 #if !defined(CONFIG_USB_INVENTRA_DMA) && !defined(CONFIG_USB_UX500_DMA)
1671 if (rx_csr & MUSB_RXCSR_H_REQPKT) {
1672 /* REVISIT this happened for a while on some short reads...
1673 * the cleanup still needs investigation... looks bad...
1674 * and also duplicates dma cleanup code above ... plus,
1675 * shouldn't this be the "half full" double buffer case?
1676 */
1677 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1678 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1679 musb->dma_controller->channel_abort(dma);
1680 xfer_len = dma->actual_len;
1681 done = true;
1682 }
1683
1684 dev_dbg(musb->controller, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr,
1685 xfer_len, dma ? ", dma" : "");
1686 rx_csr &= ~MUSB_RXCSR_H_REQPKT;
1687
1688 musb_ep_select(mbase, epnum);
1689 musb_writew(epio, MUSB_RXCSR,
1690 MUSB_RXCSR_H_WZC_BITS | rx_csr);
1691 }
1692 #endif
1693 if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) {
1694 xfer_len = dma->actual_len;
1695
1696 val &= ~(MUSB_RXCSR_DMAENAB
1697 | MUSB_RXCSR_H_AUTOREQ
1698 | MUSB_RXCSR_AUTOCLEAR
1699 | MUSB_RXCSR_RXPKTRDY);
1700 musb_writew(hw_ep->regs, MUSB_RXCSR, val);
1701
1702 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA) || \
1703 defined(CONFIG_USB_TI_CPPI41_DMA)
1704 if (usb_pipeisoc(pipe)) {
1705 struct usb_iso_packet_descriptor *d;
1706
1707 d = urb->iso_frame_desc + qh->iso_idx;
1708 d->actual_length = xfer_len;
1709
1710 /* even if there was an error, we did the dma
1711 * for iso_frame_desc->length
1712 */
1713 if (d->status != -EILSEQ && d->status != -EOVERFLOW)
1714 d->status = 0;
1715
1716 if (++qh->iso_idx >= urb->number_of_packets) {
1717 done = true;
1718 } else {
1719 #if defined(CONFIG_USB_TI_CPPI41_DMA)
1720 struct dma_controller *c;
1721 dma_addr_t *buf;
1722 u32 length, ret;
1723
1724 c = musb->dma_controller;
1725 buf = (void *)
1726 urb->iso_frame_desc[qh->iso_idx].offset
1727 + (u32)urb->transfer_dma;
1728
1729 length =
1730 urb->iso_frame_desc[qh->iso_idx].length;
1731
1732 val |= MUSB_RXCSR_DMAENAB;
1733 musb_writew(hw_ep->regs, MUSB_RXCSR, val);
1734
1735 ret = c->channel_program(dma, qh->maxpacket,
1736 0, (u32) buf, length);
1737 #endif
1738 done = false;
1739 }
1740
1741 } else {
1742 /* done if urb buffer is full or short packet is recd */
1743 done = (urb->actual_length + xfer_len >=
1744 urb->transfer_buffer_length
1745 || dma->actual_len < qh->maxpacket
1746 || dma->rx_packet_done);
1747 }
1748
1749 /* send IN token for next packet, without AUTOREQ */
1750 if (!done) {
1751 val |= MUSB_RXCSR_H_REQPKT;
1752 musb_writew(epio, MUSB_RXCSR,
1753 MUSB_RXCSR_H_WZC_BITS | val);
1754 }
1755
1756 dev_dbg(musb->controller, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
1757 done ? "off" : "reset",
1758 musb_readw(epio, MUSB_RXCSR),
1759 musb_readw(epio, MUSB_RXCOUNT));
1760 #else
1761 done = true;
1762 #endif
1763 } else if (urb->status == -EINPROGRESS) {
1764 /* if no errors, be sure a packet is ready for unloading */
1765 if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) {
1766 status = -EPROTO;
1767 ERR("Rx interrupt with no errors or packet!\n");
1768
1769 /* FIXME this is another "SHOULD NEVER HAPPEN" */
1770
1771 /* SCRUB (RX) */
1772 /* do the proper sequence to abort the transfer */
1773 musb_ep_select(mbase, epnum);
1774 val &= ~MUSB_RXCSR_H_REQPKT;
1775 musb_writew(epio, MUSB_RXCSR, val);
1776 goto finish;
1777 }
1778
1779 /* we are expecting IN packets */
1780 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA) || \
1781 defined(CONFIG_USB_TI_CPPI41_DMA)
1782 if (dma) {
1783 struct dma_controller *c;
1784 u16 rx_count;
1785 int ret, length;
1786 dma_addr_t buf;
1787
1788 rx_count = musb_readw(epio, MUSB_RXCOUNT);
1789
1790 dev_dbg(musb->controller, "RX%d count %d, buffer 0x%llx len %d/%d\n",
1791 epnum, rx_count,
1792 (unsigned long long) urb->transfer_dma
1793 + urb->actual_length,
1794 qh->offset,
1795 urb->transfer_buffer_length);
1796
1797 c = musb->dma_controller;
1798
1799 if (usb_pipeisoc(pipe)) {
1800 int d_status = 0;
1801 struct usb_iso_packet_descriptor *d;
1802
1803 d = urb->iso_frame_desc + qh->iso_idx;
1804
1805 if (iso_err) {
1806 d_status = -EILSEQ;
1807 urb->error_count++;
1808 }
1809 if (rx_count > d->length) {
1810 if (d_status == 0) {
1811 d_status = -EOVERFLOW;
1812 urb->error_count++;
1813 }
1814 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n",\
1815 rx_count, d->length);
1816
1817 length = d->length;
1818 } else
1819 length = rx_count;
1820 d->status = d_status;
1821 buf = urb->transfer_dma + d->offset;
1822 } else {
1823 length = rx_count;
1824 buf = urb->transfer_dma +
1825 urb->actual_length;
1826 }
1827
1828 dma->desired_mode = 0;
1829 #ifdef USE_MODE1
1830 /* because of the issue below, mode 1 will
1831 * only rarely behave with correct semantics.
1832 */
1833 if ((urb->transfer_flags &
1834 URB_SHORT_NOT_OK)
1835 && (urb->transfer_buffer_length -
1836 urb->actual_length)
1837 > qh->maxpacket)
1838 dma->desired_mode = 1;
1839 if (rx_count < hw_ep->max_packet_sz_rx) {
1840 length = rx_count;
1841 dma->desired_mode = 0;
1842 } else {
1843 length = urb->transfer_buffer_length;
1844 }
1845 #endif
1846
1847 /* Disadvantage of using mode 1:
1848 * It's basically usable only for mass storage class; essentially all
1849 * other protocols also terminate transfers on short packets.
1850 *
1851 * Details:
1852 * An extra IN token is sent at the end of the transfer (due to AUTOREQ)
1853 * If you try to use mode 1 for (transfer_buffer_length - 512), and try
1854 * to use the extra IN token to grab the last packet using mode 0, then
1855 * the problem is that you cannot be sure when the device will send the
1856 * last packet and RxPktRdy set. Sometimes the packet is recd too soon
1857 * such that it gets lost when RxCSR is re-set at the end of the mode 1
1858 * transfer, while sometimes it is recd just a little late so that if you
1859 * try to configure for mode 0 soon after the mode 1 transfer is
1860 * completed, you will find rxcount 0. Okay, so you might think why not
1861 * wait for an interrupt when the pkt is recd. Well, you won't get any!
1862 */
1863
1864 val = musb_readw(epio, MUSB_RXCSR);
1865 val &= ~MUSB_RXCSR_H_REQPKT;
1866
1867 if (dma->desired_mode == 0)
1868 val &= ~MUSB_RXCSR_H_AUTOREQ;
1869 else
1870 val |= MUSB_RXCSR_H_AUTOREQ;
1871 val |= MUSB_RXCSR_DMAENAB;
1872
1873 /* autoclear shouldn't be set in high bandwidth */
1874 if (qh->hb_mult == 1)
1875 val |= MUSB_RXCSR_AUTOCLEAR;
1876
1877 musb_writew(epio, MUSB_RXCSR,
1878 MUSB_RXCSR_H_WZC_BITS | val);
1879
1880 /* REVISIT if when actual_length != 0,
1881 * transfer_buffer_length needs to be
1882 * adjusted first...
1883 */
1884 ret = c->channel_program(
1885 dma, qh->maxpacket,
1886 dma->desired_mode, buf, length);
1887
1888 if (!ret) {
1889 c->channel_release(dma);
1890 hw_ep->rx_channel = NULL;
1891 dma = NULL;
1892 val = musb_readw(epio, MUSB_RXCSR);
1893 val &= ~(MUSB_RXCSR_DMAENAB
1894 | MUSB_RXCSR_H_AUTOREQ
1895 | MUSB_RXCSR_AUTOCLEAR);
1896 musb_writew(epio, MUSB_RXCSR, val);
1897 }
1898 }
1899 #endif /* Mentor DMA */
1900
1901 if (!dma) {
1902 unsigned int received_len;
1903
1904 /* Unmap the buffer so that CPU can use it */
1905 usb_hcd_unmap_urb_for_dma(musb->hcd, urb);
1906
1907 /*
1908 * We need to map sg if the transfer_buffer is
1909 * NULL.
1910 */
1911 if (!urb->transfer_buffer) {
1912 qh->use_sg = true;
1913 sg_miter_start(&qh->sg_miter, urb->sg, 1,
1914 sg_flags);
1915 }
1916
1917 if (qh->use_sg) {
1918 if (!sg_miter_next(&qh->sg_miter)) {
1919 dev_err(musb->controller, "error: sg list empty\n");
1920 sg_miter_stop(&qh->sg_miter);
1921 status = -EINVAL;
1922 done = true;
1923 goto finish;
1924 }
1925 urb->transfer_buffer = qh->sg_miter.addr;
1926 received_len = urb->actual_length;
1927 qh->offset = 0x0;
1928 done = musb_host_packet_rx(musb, urb, epnum,
1929 iso_err);
1930 /* Calculate the number of bytes received */
1931 received_len = urb->actual_length -
1932 received_len;
1933 qh->sg_miter.consumed = received_len;
1934 sg_miter_stop(&qh->sg_miter);
1935 } else {
1936 done = musb_host_packet_rx(musb, urb,
1937 epnum, iso_err);
1938 }
1939 dev_dbg(musb->controller, "read %spacket\n", done ? "last " : "");
1940 }
1941 }
1942
1943 finish:
1944 urb->actual_length += xfer_len;
1945 qh->offset += xfer_len;
1946 if (done) {
1947 if (qh->use_sg)
1948 qh->use_sg = false;
1949
1950 if (urb->status == -EINPROGRESS)
1951 urb->status = status;
1952 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN);
1953 }
1954 }
1955
1956 /* schedule nodes correspond to peripheral endpoints, like an OHCI QH.
1957 * the software schedule associates multiple such nodes with a given
1958 * host side hardware endpoint + direction; scheduling may activate
1959 * that hardware endpoint.
1960 */
musb_schedule(struct musb * musb,struct musb_qh * qh,int is_in)1961 static int musb_schedule(
1962 struct musb *musb,
1963 struct musb_qh *qh,
1964 int is_in)
1965 {
1966 int idle = 0;
1967 int best_diff;
1968 int best_end, epnum;
1969 struct musb_hw_ep *hw_ep = NULL;
1970 struct list_head *head = NULL;
1971 u8 toggle;
1972 u8 txtype;
1973 struct urb *urb = next_urb(qh);
1974
1975 /* use fixed hardware for control and bulk */
1976 if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
1977 head = &musb->control;
1978 hw_ep = musb->control_ep;
1979 goto success;
1980 }
1981
1982 /* else, periodic transfers get muxed to other endpoints */
1983
1984 /*
1985 * We know this qh hasn't been scheduled, so all we need to do
1986 * is choose which hardware endpoint to put it on ...
1987 *
1988 * REVISIT what we really want here is a regular schedule tree
1989 * like e.g. OHCI uses.
1990 */
1991 best_diff = 4096;
1992 best_end = -1;
1993
1994 for (epnum = 1, hw_ep = musb->endpoints + 1;
1995 epnum < musb->nr_endpoints;
1996 epnum++, hw_ep++) {
1997 int diff;
1998
1999 if (musb_ep_get_qh(hw_ep, is_in) != NULL)
2000 continue;
2001
2002 if (hw_ep == musb->bulk_ep)
2003 continue;
2004
2005 if (is_in)
2006 diff = hw_ep->max_packet_sz_rx;
2007 else
2008 diff = hw_ep->max_packet_sz_tx;
2009 diff -= (qh->maxpacket * qh->hb_mult);
2010
2011 if (diff >= 0 && best_diff > diff) {
2012
2013 /*
2014 * Mentor controller has a bug in that if we schedule
2015 * a BULK Tx transfer on an endpoint that had earlier
2016 * handled ISOC then the BULK transfer has to start on
2017 * a zero toggle. If the BULK transfer starts on a 1
2018 * toggle then this transfer will fail as the mentor
2019 * controller starts the Bulk transfer on a 0 toggle
2020 * irrespective of the programming of the toggle bits
2021 * in the TXCSR register. Check for this condition
2022 * while allocating the EP for a Tx Bulk transfer. If
2023 * so skip this EP.
2024 */
2025 hw_ep = musb->endpoints + epnum;
2026 toggle = usb_gettoggle(urb->dev, qh->epnum, !is_in);
2027 txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE)
2028 >> 4) & 0x3;
2029 if (!is_in && (qh->type == USB_ENDPOINT_XFER_BULK) &&
2030 toggle && (txtype == USB_ENDPOINT_XFER_ISOC))
2031 continue;
2032
2033 best_diff = diff;
2034 best_end = epnum;
2035 }
2036 }
2037 /* use bulk reserved ep1 if no other ep is free */
2038 if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) {
2039 hw_ep = musb->bulk_ep;
2040 if (is_in)
2041 head = &musb->in_bulk;
2042 else
2043 head = &musb->out_bulk;
2044
2045 /* Enable bulk RX/TX NAK timeout scheme when bulk requests are
2046 * multiplexed. This scheme does not work in high speed to full
2047 * speed scenario as NAK interrupts are not coming from a
2048 * full speed device connected to a high speed device.
2049 * NAK timeout interval is 8 (128 uframe or 16ms) for HS and
2050 * 4 (8 frame or 8ms) for FS device.
2051 */
2052 if (qh->dev)
2053 qh->intv_reg =
2054 (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4;
2055 goto success;
2056 } else if (best_end < 0) {
2057 return -ENOSPC;
2058 }
2059
2060 idle = 1;
2061 qh->mux = 0;
2062 hw_ep = musb->endpoints + best_end;
2063 dev_dbg(musb->controller, "qh %p periodic slot %d\n", qh, best_end);
2064 success:
2065 if (head) {
2066 idle = list_empty(head);
2067 list_add_tail(&qh->ring, head);
2068 qh->mux = 1;
2069 }
2070 qh->hw_ep = hw_ep;
2071 qh->hep->hcpriv = qh;
2072 if (idle)
2073 musb_start_urb(musb, is_in, qh);
2074 return 0;
2075 }
2076
musb_urb_enqueue(struct usb_hcd * hcd,struct urb * urb,gfp_t mem_flags)2077 static int musb_urb_enqueue(
2078 struct usb_hcd *hcd,
2079 struct urb *urb,
2080 gfp_t mem_flags)
2081 {
2082 unsigned long flags;
2083 struct musb *musb = hcd_to_musb(hcd);
2084 struct usb_host_endpoint *hep = urb->ep;
2085 struct musb_qh *qh;
2086 struct usb_endpoint_descriptor *epd = &hep->desc;
2087 int ret;
2088 unsigned type_reg;
2089 unsigned interval;
2090
2091 /* host role must be active */
2092 if (!is_host_active(musb) || !musb->is_active)
2093 return -ENODEV;
2094
2095 spin_lock_irqsave(&musb->lock, flags);
2096 ret = usb_hcd_link_urb_to_ep(hcd, urb);
2097 qh = ret ? NULL : hep->hcpriv;
2098 if (qh)
2099 urb->hcpriv = qh;
2100 spin_unlock_irqrestore(&musb->lock, flags);
2101
2102 /* DMA mapping was already done, if needed, and this urb is on
2103 * hep->urb_list now ... so we're done, unless hep wasn't yet
2104 * scheduled onto a live qh.
2105 *
2106 * REVISIT best to keep hep->hcpriv valid until the endpoint gets
2107 * disabled, testing for empty qh->ring and avoiding qh setup costs
2108 * except for the first urb queued after a config change.
2109 */
2110 if (qh || ret)
2111 return ret;
2112
2113 /* Allocate and initialize qh, minimizing the work done each time
2114 * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it.
2115 *
2116 * REVISIT consider a dedicated qh kmem_cache, so it's harder
2117 * for bugs in other kernel code to break this driver...
2118 */
2119 qh = kzalloc(sizeof *qh, mem_flags);
2120 if (!qh) {
2121 spin_lock_irqsave(&musb->lock, flags);
2122 usb_hcd_unlink_urb_from_ep(hcd, urb);
2123 spin_unlock_irqrestore(&musb->lock, flags);
2124 return -ENOMEM;
2125 }
2126
2127 qh->hep = hep;
2128 qh->dev = urb->dev;
2129 INIT_LIST_HEAD(&qh->ring);
2130 qh->is_ready = 1;
2131
2132 qh->maxpacket = usb_endpoint_maxp(epd);
2133 qh->type = usb_endpoint_type(epd);
2134
2135 /* Bits 11 & 12 of wMaxPacketSize encode high bandwidth multiplier.
2136 * Some musb cores don't support high bandwidth ISO transfers; and
2137 * we don't (yet!) support high bandwidth interrupt transfers.
2138 */
2139 qh->hb_mult = 1 + ((qh->maxpacket >> 11) & 0x03);
2140 if (qh->hb_mult > 1) {
2141 int ok = (qh->type == USB_ENDPOINT_XFER_ISOC);
2142
2143 if (ok)
2144 ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx)
2145 || (usb_pipeout(urb->pipe) && musb->hb_iso_tx);
2146 if (!ok) {
2147 ret = -EMSGSIZE;
2148 goto done;
2149 }
2150 qh->maxpacket &= 0x7ff;
2151 }
2152
2153 qh->epnum = usb_endpoint_num(epd);
2154
2155 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */
2156 qh->addr_reg = (u8) usb_pipedevice(urb->pipe);
2157
2158 /* precompute rxtype/txtype/type0 register */
2159 type_reg = (qh->type << 4) | qh->epnum;
2160 switch (urb->dev->speed) {
2161 case USB_SPEED_LOW:
2162 type_reg |= 0xc0;
2163 break;
2164 case USB_SPEED_FULL:
2165 type_reg |= 0x80;
2166 break;
2167 default:
2168 type_reg |= 0x40;
2169 }
2170 qh->type_reg = type_reg;
2171
2172 /* Precompute RXINTERVAL/TXINTERVAL register */
2173 switch (qh->type) {
2174 case USB_ENDPOINT_XFER_INT:
2175 /*
2176 * Full/low speeds use the linear encoding,
2177 * high speed uses the logarithmic encoding.
2178 */
2179 if (urb->dev->speed <= USB_SPEED_FULL) {
2180 interval = max_t(u8, epd->bInterval, 1);
2181 break;
2182 }
2183 /* FALLTHROUGH */
2184 case USB_ENDPOINT_XFER_ISOC:
2185 /* ISO always uses logarithmic encoding */
2186 interval = min_t(u8, epd->bInterval, 16);
2187 break;
2188 default:
2189 /* REVISIT we actually want to use NAK limits, hinting to the
2190 * transfer scheduling logic to try some other qh, e.g. try
2191 * for 2 msec first:
2192 *
2193 * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2;
2194 *
2195 * The downside of disabling this is that transfer scheduling
2196 * gets VERY unfair for nonperiodic transfers; a misbehaving
2197 * peripheral could make that hurt. That's perfectly normal
2198 * for reads from network or serial adapters ... so we have
2199 * partial NAKlimit support for bulk RX.
2200 *
2201 * The upside of disabling it is simpler transfer scheduling.
2202 */
2203 interval = 0;
2204 }
2205 qh->intv_reg = interval;
2206
2207 /* precompute addressing for external hub/tt ports */
2208 if (musb->is_multipoint) {
2209 struct usb_device *parent = urb->dev->parent;
2210
2211 if (parent != hcd->self.root_hub) {
2212 qh->h_addr_reg = (u8) parent->devnum;
2213
2214 /* set up tt info if needed */
2215 if (urb->dev->tt) {
2216 qh->h_port_reg = (u8) urb->dev->ttport;
2217 if (urb->dev->tt->hub)
2218 qh->h_addr_reg =
2219 (u8) urb->dev->tt->hub->devnum;
2220 if (urb->dev->tt->multi)
2221 qh->h_addr_reg |= 0x80;
2222 }
2223 }
2224 }
2225
2226 /* invariant: hep->hcpriv is null OR the qh that's already scheduled.
2227 * until we get real dma queues (with an entry for each urb/buffer),
2228 * we only have work to do in the former case.
2229 */
2230 spin_lock_irqsave(&musb->lock, flags);
2231 if (hep->hcpriv || !next_urb(qh)) {
2232 /* some concurrent activity submitted another urb to hep...
2233 * odd, rare, error prone, but legal.
2234 */
2235 kfree(qh);
2236 qh = NULL;
2237 ret = 0;
2238 } else
2239 ret = musb_schedule(musb, qh,
2240 epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK);
2241
2242 if (ret == 0) {
2243 urb->hcpriv = qh;
2244 /* FIXME set urb->start_frame for iso/intr, it's tested in
2245 * musb_start_urb(), but otherwise only konicawc cares ...
2246 */
2247 }
2248 spin_unlock_irqrestore(&musb->lock, flags);
2249
2250 done:
2251 if (ret != 0) {
2252 spin_lock_irqsave(&musb->lock, flags);
2253 usb_hcd_unlink_urb_from_ep(hcd, urb);
2254 spin_unlock_irqrestore(&musb->lock, flags);
2255 kfree(qh);
2256 }
2257 return ret;
2258 }
2259
2260
2261 /*
2262 * abort a transfer that's at the head of a hardware queue.
2263 * called with controller locked, irqs blocked
2264 * that hardware queue advances to the next transfer, unless prevented
2265 */
musb_cleanup_urb(struct urb * urb,struct musb_qh * qh)2266 static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh)
2267 {
2268 struct musb_hw_ep *ep = qh->hw_ep;
2269 struct musb *musb = ep->musb;
2270 void __iomem *epio = ep->regs;
2271 unsigned hw_end = ep->epnum;
2272 void __iomem *regs = ep->musb->mregs;
2273 int is_in = usb_pipein(urb->pipe);
2274 int status = 0;
2275 u16 csr;
2276
2277 musb_ep_select(regs, hw_end);
2278
2279 if (is_dma_capable()) {
2280 struct dma_channel *dma;
2281
2282 dma = is_in ? ep->rx_channel : ep->tx_channel;
2283 if (dma) {
2284 status = ep->musb->dma_controller->channel_abort(dma);
2285 dev_dbg(musb->controller,
2286 "abort %cX%d DMA for urb %p --> %d\n",
2287 is_in ? 'R' : 'T', ep->epnum,
2288 urb, status);
2289 urb->actual_length += dma->actual_len;
2290 }
2291 }
2292
2293 /* turn off DMA requests, discard state, stop polling ... */
2294 if (ep->epnum && is_in) {
2295 /* giveback saves bulk toggle */
2296 csr = musb_h_flush_rxfifo(ep, 0);
2297
2298 /* REVISIT we still get an irq; should likely clear the
2299 * endpoint's irq status here to avoid bogus irqs.
2300 * clearing that status is platform-specific...
2301 */
2302 } else if (ep->epnum) {
2303 musb_h_tx_flush_fifo(ep);
2304 csr = musb_readw(epio, MUSB_TXCSR);
2305 csr &= ~(MUSB_TXCSR_AUTOSET
2306 | MUSB_TXCSR_DMAENAB
2307 | MUSB_TXCSR_H_RXSTALL
2308 | MUSB_TXCSR_H_NAKTIMEOUT
2309 | MUSB_TXCSR_H_ERROR
2310 | MUSB_TXCSR_TXPKTRDY);
2311 musb_writew(epio, MUSB_TXCSR, csr);
2312 /* REVISIT may need to clear FLUSHFIFO ... */
2313 musb_writew(epio, MUSB_TXCSR, csr);
2314 /* flush cpu writebuffer */
2315 csr = musb_readw(epio, MUSB_TXCSR);
2316 } else {
2317 musb_h_ep0_flush_fifo(ep);
2318 }
2319 if (status == 0)
2320 musb_advance_schedule(ep->musb, urb, ep, is_in);
2321 return status;
2322 }
2323
musb_urb_dequeue(struct usb_hcd * hcd,struct urb * urb,int status)2324 static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
2325 {
2326 struct musb *musb = hcd_to_musb(hcd);
2327 struct musb_qh *qh;
2328 unsigned long flags;
2329 int is_in = usb_pipein(urb->pipe);
2330 int ret;
2331
2332 dev_dbg(musb->controller, "urb=%p, dev%d ep%d%s\n", urb,
2333 usb_pipedevice(urb->pipe),
2334 usb_pipeendpoint(urb->pipe),
2335 is_in ? "in" : "out");
2336
2337 spin_lock_irqsave(&musb->lock, flags);
2338 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
2339 if (ret)
2340 goto done;
2341
2342 qh = urb->hcpriv;
2343 if (!qh)
2344 goto done;
2345
2346 /*
2347 * Any URB not actively programmed into endpoint hardware can be
2348 * immediately given back; that's any URB not at the head of an
2349 * endpoint queue, unless someday we get real DMA queues. And even
2350 * if it's at the head, it might not be known to the hardware...
2351 *
2352 * Otherwise abort current transfer, pending DMA, etc.; urb->status
2353 * has already been updated. This is a synchronous abort; it'd be
2354 * OK to hold off until after some IRQ, though.
2355 *
2356 * NOTE: qh is invalid unless !list_empty(&hep->urb_list)
2357 */
2358 if (!qh->is_ready
2359 || urb->urb_list.prev != &qh->hep->urb_list
2360 || musb_ep_get_qh(qh->hw_ep, is_in) != qh) {
2361 int ready = qh->is_ready;
2362
2363 qh->is_ready = 0;
2364 musb_giveback(musb, urb, 0);
2365 qh->is_ready = ready;
2366
2367 /* If nothing else (usually musb_giveback) is using it
2368 * and its URB list has emptied, recycle this qh.
2369 */
2370 if (ready && list_empty(&qh->hep->urb_list)) {
2371 qh->hep->hcpriv = NULL;
2372 list_del(&qh->ring);
2373 kfree(qh);
2374 }
2375 } else
2376 ret = musb_cleanup_urb(urb, qh);
2377 done:
2378 spin_unlock_irqrestore(&musb->lock, flags);
2379 return ret;
2380 }
2381
2382 /* disable an endpoint */
2383 static void
musb_h_disable(struct usb_hcd * hcd,struct usb_host_endpoint * hep)2384 musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
2385 {
2386 u8 is_in = hep->desc.bEndpointAddress & USB_DIR_IN;
2387 unsigned long flags;
2388 struct musb *musb = hcd_to_musb(hcd);
2389 struct musb_qh *qh;
2390 struct urb *urb;
2391
2392 spin_lock_irqsave(&musb->lock, flags);
2393
2394 qh = hep->hcpriv;
2395 if (qh == NULL)
2396 goto exit;
2397
2398 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
2399
2400 /* Kick the first URB off the hardware, if needed */
2401 qh->is_ready = 0;
2402 if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) {
2403 urb = next_urb(qh);
2404
2405 /* make software (then hardware) stop ASAP */
2406 if (!urb->unlinked)
2407 urb->status = -ESHUTDOWN;
2408
2409 /* cleanup */
2410 musb_cleanup_urb(urb, qh);
2411
2412 /* Then nuke all the others ... and advance the
2413 * queue on hw_ep (e.g. bulk ring) when we're done.
2414 */
2415 while (!list_empty(&hep->urb_list)) {
2416 urb = next_urb(qh);
2417 urb->status = -ESHUTDOWN;
2418 musb_advance_schedule(musb, urb, qh->hw_ep, is_in);
2419 }
2420 } else {
2421 /* Just empty the queue; the hardware is busy with
2422 * other transfers, and since !qh->is_ready nothing
2423 * will activate any of these as it advances.
2424 */
2425 while (!list_empty(&hep->urb_list))
2426 musb_giveback(musb, next_urb(qh), -ESHUTDOWN);
2427
2428 hep->hcpriv = NULL;
2429 list_del(&qh->ring);
2430 kfree(qh);
2431 }
2432 exit:
2433 spin_unlock_irqrestore(&musb->lock, flags);
2434 }
2435
musb_h_get_frame_number(struct usb_hcd * hcd)2436 static int musb_h_get_frame_number(struct usb_hcd *hcd)
2437 {
2438 struct musb *musb = hcd_to_musb(hcd);
2439
2440 return musb_readw(musb->mregs, MUSB_FRAME);
2441 }
2442
musb_h_start(struct usb_hcd * hcd)2443 static int musb_h_start(struct usb_hcd *hcd)
2444 {
2445 struct musb *musb = hcd_to_musb(hcd);
2446
2447 /* NOTE: musb_start() is called when the hub driver turns
2448 * on port power, or when (OTG) peripheral starts.
2449 */
2450 hcd->state = HC_STATE_RUNNING;
2451 musb->port1_status = 0;
2452 return 0;
2453 }
2454
musb_h_stop(struct usb_hcd * hcd)2455 static void musb_h_stop(struct usb_hcd *hcd)
2456 {
2457 musb_stop(hcd_to_musb(hcd));
2458 hcd->state = HC_STATE_HALT;
2459 }
2460
musb_bus_suspend(struct usb_hcd * hcd)2461 static int musb_bus_suspend(struct usb_hcd *hcd)
2462 {
2463 struct musb *musb = hcd_to_musb(hcd);
2464 u8 devctl;
2465
2466 musb_port_suspend(musb, true);
2467
2468 if (!is_host_active(musb))
2469 return 0;
2470
2471 switch (musb->xceiv->state) {
2472 case OTG_STATE_A_SUSPEND:
2473 return 0;
2474 case OTG_STATE_A_WAIT_VRISE:
2475 /* ID could be grounded even if there's no device
2476 * on the other end of the cable. NOTE that the
2477 * A_WAIT_VRISE timers are messy with MUSB...
2478 */
2479 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2480 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
2481 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
2482 break;
2483 default:
2484 break;
2485 }
2486
2487 if (musb->is_active) {
2488 WARNING("trying to suspend as %s while active\n",
2489 usb_otg_state_string(musb->xceiv->state));
2490 return -EBUSY;
2491 } else
2492 return 0;
2493 }
2494
musb_bus_resume(struct usb_hcd * hcd)2495 static int musb_bus_resume(struct usb_hcd *hcd)
2496 {
2497 struct musb *musb = hcd_to_musb(hcd);
2498
2499 if (musb->config &&
2500 musb->config->host_port_deassert_reset_at_resume)
2501 musb_port_reset(musb, false);
2502
2503 return 0;
2504 }
2505
2506 #ifndef CONFIG_MUSB_PIO_ONLY
2507
2508 #define MUSB_USB_DMA_ALIGN 4
2509
2510 struct musb_temp_buffer {
2511 void *kmalloc_ptr;
2512 void *old_xfer_buffer;
2513 u8 data[0];
2514 };
2515
musb_free_temp_buffer(struct urb * urb)2516 static void musb_free_temp_buffer(struct urb *urb)
2517 {
2518 enum dma_data_direction dir;
2519 struct musb_temp_buffer *temp;
2520
2521 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
2522 return;
2523
2524 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
2525
2526 temp = container_of(urb->transfer_buffer, struct musb_temp_buffer,
2527 data);
2528
2529 if (dir == DMA_FROM_DEVICE) {
2530 memcpy(temp->old_xfer_buffer, temp->data,
2531 urb->transfer_buffer_length);
2532 }
2533 urb->transfer_buffer = temp->old_xfer_buffer;
2534 kfree(temp->kmalloc_ptr);
2535
2536 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
2537 }
2538
musb_alloc_temp_buffer(struct urb * urb,gfp_t mem_flags)2539 static int musb_alloc_temp_buffer(struct urb *urb, gfp_t mem_flags)
2540 {
2541 enum dma_data_direction dir;
2542 struct musb_temp_buffer *temp;
2543 void *kmalloc_ptr;
2544 size_t kmalloc_size;
2545
2546 if (urb->num_sgs || urb->sg ||
2547 urb->transfer_buffer_length == 0 ||
2548 !((uintptr_t)urb->transfer_buffer & (MUSB_USB_DMA_ALIGN - 1)))
2549 return 0;
2550
2551 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
2552
2553 /* Allocate a buffer with enough padding for alignment */
2554 kmalloc_size = urb->transfer_buffer_length +
2555 sizeof(struct musb_temp_buffer) + MUSB_USB_DMA_ALIGN - 1;
2556
2557 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
2558 if (!kmalloc_ptr)
2559 return -ENOMEM;
2560
2561 /* Position our struct temp_buffer such that data is aligned */
2562 temp = PTR_ALIGN(kmalloc_ptr, MUSB_USB_DMA_ALIGN);
2563
2564
2565 temp->kmalloc_ptr = kmalloc_ptr;
2566 temp->old_xfer_buffer = urb->transfer_buffer;
2567 if (dir == DMA_TO_DEVICE)
2568 memcpy(temp->data, urb->transfer_buffer,
2569 urb->transfer_buffer_length);
2570 urb->transfer_buffer = temp->data;
2571
2572 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
2573
2574 return 0;
2575 }
2576
musb_map_urb_for_dma(struct usb_hcd * hcd,struct urb * urb,gfp_t mem_flags)2577 static int musb_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
2578 gfp_t mem_flags)
2579 {
2580 struct musb *musb = hcd_to_musb(hcd);
2581 int ret;
2582
2583 /*
2584 * The DMA engine in RTL1.8 and above cannot handle
2585 * DMA addresses that are not aligned to a 4 byte boundary.
2586 * For such engine implemented (un)map_urb_for_dma hooks.
2587 * Do not use these hooks for RTL<1.8
2588 */
2589 if (musb->hwvers < MUSB_HWVERS_1800)
2590 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2591
2592 ret = musb_alloc_temp_buffer(urb, mem_flags);
2593 if (ret)
2594 return ret;
2595
2596 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2597 if (ret)
2598 musb_free_temp_buffer(urb);
2599
2600 return ret;
2601 }
2602
musb_unmap_urb_for_dma(struct usb_hcd * hcd,struct urb * urb)2603 static void musb_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
2604 {
2605 struct musb *musb = hcd_to_musb(hcd);
2606
2607 usb_hcd_unmap_urb_for_dma(hcd, urb);
2608
2609 /* Do not use this hook for RTL<1.8 (see description above) */
2610 if (musb->hwvers < MUSB_HWVERS_1800)
2611 return;
2612
2613 musb_free_temp_buffer(urb);
2614 }
2615 #endif /* !CONFIG_MUSB_PIO_ONLY */
2616
2617 static const struct hc_driver musb_hc_driver = {
2618 .description = "musb-hcd",
2619 .product_desc = "MUSB HDRC host driver",
2620 .hcd_priv_size = sizeof(struct musb *),
2621 .flags = HCD_USB2 | HCD_MEMORY,
2622
2623 /* not using irq handler or reset hooks from usbcore, since
2624 * those must be shared with peripheral code for OTG configs
2625 */
2626
2627 .start = musb_h_start,
2628 .stop = musb_h_stop,
2629
2630 .get_frame_number = musb_h_get_frame_number,
2631
2632 .urb_enqueue = musb_urb_enqueue,
2633 .urb_dequeue = musb_urb_dequeue,
2634 .endpoint_disable = musb_h_disable,
2635
2636 #ifndef CONFIG_MUSB_PIO_ONLY
2637 .map_urb_for_dma = musb_map_urb_for_dma,
2638 .unmap_urb_for_dma = musb_unmap_urb_for_dma,
2639 #endif
2640
2641 .hub_status_data = musb_hub_status_data,
2642 .hub_control = musb_hub_control,
2643 .bus_suspend = musb_bus_suspend,
2644 .bus_resume = musb_bus_resume,
2645 /* .start_port_reset = NULL, */
2646 /* .hub_irq_enable = NULL, */
2647 };
2648
musb_host_alloc(struct musb * musb)2649 int musb_host_alloc(struct musb *musb)
2650 {
2651 struct device *dev = musb->controller;
2652
2653 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
2654 musb->hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
2655 if (!musb->hcd)
2656 return -EINVAL;
2657
2658 *musb->hcd->hcd_priv = (unsigned long) musb;
2659 musb->hcd->self.uses_pio_for_control = 1;
2660 musb->hcd->uses_new_polling = 1;
2661 musb->hcd->has_tt = 1;
2662
2663 return 0;
2664 }
2665
musb_host_cleanup(struct musb * musb)2666 void musb_host_cleanup(struct musb *musb)
2667 {
2668 if (musb->port_mode == MUSB_PORT_MODE_GADGET)
2669 return;
2670 usb_remove_hcd(musb->hcd);
2671 }
2672
musb_host_free(struct musb * musb)2673 void musb_host_free(struct musb *musb)
2674 {
2675 usb_put_hcd(musb->hcd);
2676 }
2677
musb_host_setup(struct musb * musb,int power_budget)2678 int musb_host_setup(struct musb *musb, int power_budget)
2679 {
2680 int ret;
2681 struct usb_hcd *hcd = musb->hcd;
2682
2683 MUSB_HST_MODE(musb);
2684 musb->xceiv->otg->default_a = 1;
2685 musb->xceiv->state = OTG_STATE_A_IDLE;
2686
2687 otg_set_host(musb->xceiv->otg, &hcd->self);
2688 hcd->self.otg_port = 1;
2689 musb->xceiv->otg->host = &hcd->self;
2690 hcd->power_budget = 2 * (power_budget ? : 250);
2691
2692 ret = usb_add_hcd(hcd, 0, 0);
2693 if (ret < 0)
2694 return ret;
2695
2696 device_wakeup_enable(hcd->self.controller);
2697 return 0;
2698 }
2699
musb_host_resume_root_hub(struct musb * musb)2700 void musb_host_resume_root_hub(struct musb *musb)
2701 {
2702 usb_hcd_resume_root_hub(musb->hcd);
2703 }
2704
musb_host_poke_root_hub(struct musb * musb)2705 void musb_host_poke_root_hub(struct musb *musb)
2706 {
2707 MUSB_HST_MODE(musb);
2708 if (musb->hcd->status_urb)
2709 usb_hcd_poll_rh_status(musb->hcd);
2710 else
2711 usb_hcd_resume_root_hub(musb->hcd);
2712 }
2713