1 /*
2 * HDMI driver definition for TI OMAP4 Processor.
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #ifndef _HDMI_H
20 #define _HDMI_H
21
22 #include <linux/delay.h>
23 #include <linux/io.h>
24 #include <linux/platform_device.h>
25 #include <linux/hdmi.h>
26 #include <video/omapdss.h>
27
28 #include "dss.h"
29
30 /* HDMI Wrapper */
31
32 #define HDMI_WP_REVISION 0x0
33 #define HDMI_WP_SYSCONFIG 0x10
34 #define HDMI_WP_IRQSTATUS_RAW 0x24
35 #define HDMI_WP_IRQSTATUS 0x28
36 #define HDMI_WP_IRQENABLE_SET 0x2C
37 #define HDMI_WP_IRQENABLE_CLR 0x30
38 #define HDMI_WP_IRQWAKEEN 0x34
39 #define HDMI_WP_PWR_CTRL 0x40
40 #define HDMI_WP_DEBOUNCE 0x44
41 #define HDMI_WP_VIDEO_CFG 0x50
42 #define HDMI_WP_VIDEO_SIZE 0x60
43 #define HDMI_WP_VIDEO_TIMING_H 0x68
44 #define HDMI_WP_VIDEO_TIMING_V 0x6C
45 #define HDMI_WP_CLK 0x70
46 #define HDMI_WP_AUDIO_CFG 0x80
47 #define HDMI_WP_AUDIO_CFG2 0x84
48 #define HDMI_WP_AUDIO_CTRL 0x88
49 #define HDMI_WP_AUDIO_DATA 0x8C
50
51 /* HDMI WP IRQ flags */
52 #define HDMI_IRQ_CORE (1 << 0)
53 #define HDMI_IRQ_OCP_TIMEOUT (1 << 4)
54 #define HDMI_IRQ_AUDIO_FIFO_UNDERFLOW (1 << 8)
55 #define HDMI_IRQ_AUDIO_FIFO_OVERFLOW (1 << 9)
56 #define HDMI_IRQ_AUDIO_FIFO_SAMPLE_REQ (1 << 10)
57 #define HDMI_IRQ_VIDEO_VSYNC (1 << 16)
58 #define HDMI_IRQ_VIDEO_FRAME_DONE (1 << 17)
59 #define HDMI_IRQ_PHY_LINE5V_ASSERT (1 << 24)
60 #define HDMI_IRQ_LINK_CONNECT (1 << 25)
61 #define HDMI_IRQ_LINK_DISCONNECT (1 << 26)
62 #define HDMI_IRQ_PLL_LOCK (1 << 29)
63 #define HDMI_IRQ_PLL_UNLOCK (1 << 30)
64 #define HDMI_IRQ_PLL_RECAL (1 << 31)
65
66 /* HDMI PLL */
67
68 #define PLLCTRL_PLL_CONTROL 0x0
69 #define PLLCTRL_PLL_STATUS 0x4
70 #define PLLCTRL_PLL_GO 0x8
71 #define PLLCTRL_CFG1 0xC
72 #define PLLCTRL_CFG2 0x10
73 #define PLLCTRL_CFG3 0x14
74 #define PLLCTRL_SSC_CFG1 0x18
75 #define PLLCTRL_SSC_CFG2 0x1C
76 #define PLLCTRL_CFG4 0x20
77
78 /* HDMI PHY */
79
80 #define HDMI_TXPHY_TX_CTRL 0x0
81 #define HDMI_TXPHY_DIGITAL_CTRL 0x4
82 #define HDMI_TXPHY_POWER_CTRL 0x8
83 #define HDMI_TXPHY_PAD_CFG_CTRL 0xC
84 #define HDMI_TXPHY_BIST_CONTROL 0x1C
85
86 enum hdmi_pll_pwr {
87 HDMI_PLLPWRCMD_ALLOFF = 0,
88 HDMI_PLLPWRCMD_PLLONLY = 1,
89 HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,
90 HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3
91 };
92
93 enum hdmi_phy_pwr {
94 HDMI_PHYPWRCMD_OFF = 0,
95 HDMI_PHYPWRCMD_LDOON = 1,
96 HDMI_PHYPWRCMD_TXON = 2
97 };
98
99 enum hdmi_core_hdmi_dvi {
100 HDMI_DVI = 0,
101 HDMI_HDMI = 1
102 };
103
104 enum hdmi_clk_refsel {
105 HDMI_REFSEL_PCLK = 0,
106 HDMI_REFSEL_REF1 = 1,
107 HDMI_REFSEL_REF2 = 2,
108 HDMI_REFSEL_SYSCLK = 3
109 };
110
111 enum hdmi_packing_mode {
112 HDMI_PACK_10b_RGB_YUV444 = 0,
113 HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,
114 HDMI_PACK_20b_YUV422 = 2,
115 HDMI_PACK_ALREADYPACKED = 7
116 };
117
118 enum hdmi_stereo_channels {
119 HDMI_AUDIO_STEREO_NOCHANNELS = 0,
120 HDMI_AUDIO_STEREO_ONECHANNEL = 1,
121 HDMI_AUDIO_STEREO_TWOCHANNELS = 2,
122 HDMI_AUDIO_STEREO_THREECHANNELS = 3,
123 HDMI_AUDIO_STEREO_FOURCHANNELS = 4
124 };
125
126 enum hdmi_audio_type {
127 HDMI_AUDIO_TYPE_LPCM = 0,
128 HDMI_AUDIO_TYPE_IEC = 1
129 };
130
131 enum hdmi_audio_justify {
132 HDMI_AUDIO_JUSTIFY_LEFT = 0,
133 HDMI_AUDIO_JUSTIFY_RIGHT = 1
134 };
135
136 enum hdmi_audio_sample_order {
137 HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0,
138 HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1
139 };
140
141 enum hdmi_audio_samples_perword {
142 HDMI_AUDIO_ONEWORD_ONESAMPLE = 0,
143 HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1
144 };
145
146 enum hdmi_audio_sample_size_omap {
147 HDMI_AUDIO_SAMPLE_16BITS = 0,
148 HDMI_AUDIO_SAMPLE_24BITS = 1
149 };
150
151 enum hdmi_audio_transf_mode {
152 HDMI_AUDIO_TRANSF_DMA = 0,
153 HDMI_AUDIO_TRANSF_IRQ = 1
154 };
155
156 enum hdmi_audio_blk_strt_end_sig {
157 HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0,
158 HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1
159 };
160
161 enum hdmi_core_audio_layout {
162 HDMI_AUDIO_LAYOUT_2CH = 0,
163 HDMI_AUDIO_LAYOUT_8CH = 1
164 };
165
166 enum hdmi_core_cts_mode {
167 HDMI_AUDIO_CTS_MODE_HW = 0,
168 HDMI_AUDIO_CTS_MODE_SW = 1
169 };
170
171 enum hdmi_audio_mclk_mode {
172 HDMI_AUDIO_MCLK_128FS = 0,
173 HDMI_AUDIO_MCLK_256FS = 1,
174 HDMI_AUDIO_MCLK_384FS = 2,
175 HDMI_AUDIO_MCLK_512FS = 3,
176 HDMI_AUDIO_MCLK_768FS = 4,
177 HDMI_AUDIO_MCLK_1024FS = 5,
178 HDMI_AUDIO_MCLK_1152FS = 6,
179 HDMI_AUDIO_MCLK_192FS = 7
180 };
181
182 struct hdmi_video_format {
183 enum hdmi_packing_mode packing_mode;
184 u32 y_res; /* Line per panel */
185 u32 x_res; /* pixel per line */
186 };
187
188 struct hdmi_config {
189 struct omap_video_timings timings;
190 struct hdmi_avi_infoframe infoframe;
191 enum hdmi_core_hdmi_dvi hdmi_dvi_mode;
192 };
193
194 /* HDMI PLL structure */
195 struct hdmi_pll_info {
196 u16 regn;
197 u16 regm;
198 u32 regmf;
199 u16 regm2;
200 u16 regsd;
201 u16 dcofreq;
202 enum hdmi_clk_refsel refsel;
203 };
204
205 struct hdmi_audio_format {
206 enum hdmi_stereo_channels stereo_channels;
207 u8 active_chnnls_msk;
208 enum hdmi_audio_type type;
209 enum hdmi_audio_justify justification;
210 enum hdmi_audio_sample_order sample_order;
211 enum hdmi_audio_samples_perword samples_per_word;
212 enum hdmi_audio_sample_size_omap sample_size;
213 enum hdmi_audio_blk_strt_end_sig en_sig_blk_strt_end;
214 };
215
216 struct hdmi_audio_dma {
217 u8 transfer_size;
218 u8 block_size;
219 enum hdmi_audio_transf_mode mode;
220 u16 fifo_threshold;
221 };
222
223 struct hdmi_core_audio_i2s_config {
224 u8 in_length_bits;
225 u8 justification;
226 u8 sck_edge_mode;
227 u8 vbit;
228 u8 direction;
229 u8 shift;
230 u8 active_sds;
231 };
232
233 struct hdmi_core_audio_config {
234 struct hdmi_core_audio_i2s_config i2s_cfg;
235 struct snd_aes_iec958 *iec60958_cfg;
236 bool fs_override;
237 u32 n;
238 u32 cts;
239 u32 aud_par_busclk;
240 enum hdmi_core_audio_layout layout;
241 enum hdmi_core_cts_mode cts_mode;
242 bool use_mclk;
243 enum hdmi_audio_mclk_mode mclk_mode;
244 bool en_acr_pkt;
245 bool en_dsd_audio;
246 bool en_parallel_aud_input;
247 bool en_spdif;
248 };
249
250 struct hdmi_wp_data {
251 void __iomem *base;
252 };
253
254 struct hdmi_pll_data {
255 void __iomem *base;
256
257 struct hdmi_pll_info info;
258 };
259
260 struct hdmi_phy_data {
261 void __iomem *base;
262
263 u8 lane_function[4];
264 u8 lane_polarity[4];
265 };
266
267 struct hdmi_core_data {
268 void __iomem *base;
269 };
270
hdmi_write_reg(void __iomem * base_addr,const u32 idx,u32 val)271 static inline void hdmi_write_reg(void __iomem *base_addr, const u32 idx,
272 u32 val)
273 {
274 __raw_writel(val, base_addr + idx);
275 }
276
hdmi_read_reg(void __iomem * base_addr,const u32 idx)277 static inline u32 hdmi_read_reg(void __iomem *base_addr, const u32 idx)
278 {
279 return __raw_readl(base_addr + idx);
280 }
281
282 #define REG_FLD_MOD(base, idx, val, start, end) \
283 hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
284 val, start, end))
285 #define REG_GET(base, idx, start, end) \
286 FLD_GET(hdmi_read_reg(base, idx), start, end)
287
hdmi_wait_for_bit_change(void __iomem * base_addr,const u32 idx,int b2,int b1,u32 val)288 static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
289 const u32 idx, int b2, int b1, u32 val)
290 {
291 u32 t = 0, v;
292 while (val != (v = REG_GET(base_addr, idx, b2, b1))) {
293 if (t++ > 10000)
294 return v;
295 udelay(1);
296 }
297 return v;
298 }
299
300 /* HDMI wrapper funcs */
301 int hdmi_wp_video_start(struct hdmi_wp_data *wp);
302 void hdmi_wp_video_stop(struct hdmi_wp_data *wp);
303 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);
304 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);
305 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);
306 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);
307 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);
308 int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);
309 int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val);
310 void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
311 struct hdmi_video_format *video_fmt);
312 void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
313 struct omap_video_timings *timings);
314 void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
315 struct omap_video_timings *timings);
316 void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
317 struct omap_video_timings *timings, struct hdmi_config *param);
318 int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp);
319
320 /* HDMI PLL funcs */
321 int hdmi_pll_enable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp);
322 void hdmi_pll_disable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp);
323 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s);
324 void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin, int phy);
325 int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll);
326
327 /* HDMI PHY funcs */
328 int hdmi_phy_configure(struct hdmi_phy_data *phy, struct hdmi_config *cfg);
329 void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s);
330 int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy);
331 int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes);
332
333 /* HDMI common funcs */
334 int hdmi_parse_lanes_of(struct platform_device *pdev, struct device_node *ep,
335 struct hdmi_phy_data *phy);
336
337 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) || defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
338 int hdmi_compute_acr(u32 pclk, u32 sample_freq, u32 *n, u32 *cts);
339 int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable);
340 int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable);
341 void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,
342 struct hdmi_audio_format *aud_fmt);
343 void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,
344 struct hdmi_audio_dma *aud_dma);
hdmi_mode_has_audio(int mode)345 static inline bool hdmi_mode_has_audio(int mode)
346 {
347 return mode == HDMI_HDMI ? true : false;
348 }
349 #endif
350 #endif
351