1 /*
2 * Generic EDAC defs
3 *
4 * Author: Dave Jiang <djiang@mvista.com>
5 *
6 * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 */
12 #ifndef _LINUX_EDAC_H_
13 #define _LINUX_EDAC_H_
14
15 #include <linux/atomic.h>
16 #include <linux/device.h>
17 #include <linux/completion.h>
18 #include <linux/workqueue.h>
19 #include <linux/debugfs.h>
20
21 struct device;
22
23 #define EDAC_OPSTATE_INVAL -1
24 #define EDAC_OPSTATE_POLL 0
25 #define EDAC_OPSTATE_NMI 1
26 #define EDAC_OPSTATE_INT 2
27
28 extern int edac_op_state;
29 extern int edac_err_assert;
30 extern atomic_t edac_handlers;
31 extern struct bus_type edac_subsys;
32
33 extern int edac_handler_set(void);
34 extern void edac_atomic_assert_error(void);
35 extern struct bus_type *edac_get_sysfs_subsys(void);
36 extern void edac_put_sysfs_subsys(void);
37
38 enum {
39 EDAC_REPORTING_ENABLED,
40 EDAC_REPORTING_DISABLED,
41 EDAC_REPORTING_FORCE
42 };
43
44 extern int edac_report_status;
45 #ifdef CONFIG_EDAC
get_edac_report_status(void)46 static inline int get_edac_report_status(void)
47 {
48 return edac_report_status;
49 }
50
set_edac_report_status(int new)51 static inline void set_edac_report_status(int new)
52 {
53 edac_report_status = new;
54 }
55 #else
get_edac_report_status(void)56 static inline int get_edac_report_status(void)
57 {
58 return EDAC_REPORTING_DISABLED;
59 }
60
set_edac_report_status(int new)61 static inline void set_edac_report_status(int new)
62 {
63 }
64 #endif
65
opstate_init(void)66 static inline void opstate_init(void)
67 {
68 switch (edac_op_state) {
69 case EDAC_OPSTATE_POLL:
70 case EDAC_OPSTATE_NMI:
71 break;
72 default:
73 edac_op_state = EDAC_OPSTATE_POLL;
74 }
75 return;
76 }
77
78 /* Max length of a DIMM label*/
79 #define EDAC_MC_LABEL_LEN 31
80
81 /* Maximum size of the location string */
82 #define LOCATION_SIZE 256
83
84 /* Defines the maximum number of labels that can be reported */
85 #define EDAC_MAX_LABELS 8
86
87 /* String used to join two or more labels */
88 #define OTHER_LABEL " or "
89
90 /**
91 * enum dev_type - describe the type of memory DRAM chips used at the stick
92 * @DEV_UNKNOWN: Can't be determined, or MC doesn't support detect it
93 * @DEV_X1: 1 bit for data
94 * @DEV_X2: 2 bits for data
95 * @DEV_X4: 4 bits for data
96 * @DEV_X8: 8 bits for data
97 * @DEV_X16: 16 bits for data
98 * @DEV_X32: 32 bits for data
99 * @DEV_X64: 64 bits for data
100 *
101 * Typical values are x4 and x8.
102 */
103 enum dev_type {
104 DEV_UNKNOWN = 0,
105 DEV_X1,
106 DEV_X2,
107 DEV_X4,
108 DEV_X8,
109 DEV_X16,
110 DEV_X32, /* Do these parts exist? */
111 DEV_X64 /* Do these parts exist? */
112 };
113
114 #define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
115 #define DEV_FLAG_X1 BIT(DEV_X1)
116 #define DEV_FLAG_X2 BIT(DEV_X2)
117 #define DEV_FLAG_X4 BIT(DEV_X4)
118 #define DEV_FLAG_X8 BIT(DEV_X8)
119 #define DEV_FLAG_X16 BIT(DEV_X16)
120 #define DEV_FLAG_X32 BIT(DEV_X32)
121 #define DEV_FLAG_X64 BIT(DEV_X64)
122
123 /**
124 * enum hw_event_mc_err_type - type of the detected error
125 *
126 * @HW_EVENT_ERR_CORRECTED: Corrected Error - Indicates that an ECC
127 * corrected error was detected
128 * @HW_EVENT_ERR_UNCORRECTED: Uncorrected Error - Indicates an error that
129 * can't be corrected by ECC, but it is not
130 * fatal (maybe it is on an unused memory area,
131 * or the memory controller could recover from
132 * it for example, by re-trying the operation).
133 * @HW_EVENT_ERR_FATAL: Fatal Error - Uncorrected error that could not
134 * be recovered.
135 */
136 enum hw_event_mc_err_type {
137 HW_EVENT_ERR_CORRECTED,
138 HW_EVENT_ERR_UNCORRECTED,
139 HW_EVENT_ERR_FATAL,
140 HW_EVENT_ERR_INFO,
141 };
142
mc_event_error_type(const unsigned int err_type)143 static inline char *mc_event_error_type(const unsigned int err_type)
144 {
145 switch (err_type) {
146 case HW_EVENT_ERR_CORRECTED:
147 return "Corrected";
148 case HW_EVENT_ERR_UNCORRECTED:
149 return "Uncorrected";
150 case HW_EVENT_ERR_FATAL:
151 return "Fatal";
152 default:
153 case HW_EVENT_ERR_INFO:
154 return "Info";
155 }
156 }
157
158 /**
159 * enum mem_type - memory types. For a more detailed reference, please see
160 * http://en.wikipedia.org/wiki/DRAM
161 *
162 * @MEM_EMPTY Empty csrow
163 * @MEM_RESERVED: Reserved csrow type
164 * @MEM_UNKNOWN: Unknown csrow type
165 * @MEM_FPM: FPM - Fast Page Mode, used on systems up to 1995.
166 * @MEM_EDO: EDO - Extended data out, used on systems up to 1998.
167 * @MEM_BEDO: BEDO - Burst Extended data out, an EDO variant.
168 * @MEM_SDR: SDR - Single data rate SDRAM
169 * http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory
170 * They use 3 pins for chip select: Pins 0 and 2 are
171 * for rank 0; pins 1 and 3 are for rank 1, if the memory
172 * is dual-rank.
173 * @MEM_RDR: Registered SDR SDRAM
174 * @MEM_DDR: Double data rate SDRAM
175 * http://en.wikipedia.org/wiki/DDR_SDRAM
176 * @MEM_RDDR: Registered Double data rate SDRAM
177 * This is a variant of the DDR memories.
178 * A registered memory has a buffer inside it, hiding
179 * part of the memory details to the memory controller.
180 * @MEM_RMBS: Rambus DRAM, used on a few Pentium III/IV controllers.
181 * @MEM_DDR2: DDR2 RAM, as described at JEDEC JESD79-2F.
182 * Those memories are labed as "PC2-" instead of "PC" to
183 * differenciate from DDR.
184 * @MEM_FB_DDR2: Fully-Buffered DDR2, as described at JEDEC Std No. 205
185 * and JESD206.
186 * Those memories are accessed per DIMM slot, and not by
187 * a chip select signal.
188 * @MEM_RDDR2: Registered DDR2 RAM
189 * This is a variant of the DDR2 memories.
190 * @MEM_XDR: Rambus XDR
191 * It is an evolution of the original RAMBUS memories,
192 * created to compete with DDR2. Weren't used on any
193 * x86 arch, but cell_edac PPC memory controller uses it.
194 * @MEM_DDR3: DDR3 RAM
195 * @MEM_RDDR3: Registered DDR3 RAM
196 * This is a variant of the DDR3 memories.
197 * @MEM_DDR4: DDR4 RAM
198 * @MEM_RDDR4: Registered DDR4 RAM
199 * This is a variant of the DDR4 memories.
200 */
201 enum mem_type {
202 MEM_EMPTY = 0,
203 MEM_RESERVED,
204 MEM_UNKNOWN,
205 MEM_FPM,
206 MEM_EDO,
207 MEM_BEDO,
208 MEM_SDR,
209 MEM_RDR,
210 MEM_DDR,
211 MEM_RDDR,
212 MEM_RMBS,
213 MEM_DDR2,
214 MEM_FB_DDR2,
215 MEM_RDDR2,
216 MEM_XDR,
217 MEM_DDR3,
218 MEM_RDDR3,
219 MEM_DDR4,
220 MEM_RDDR4,
221 };
222
223 #define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
224 #define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
225 #define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN)
226 #define MEM_FLAG_FPM BIT(MEM_FPM)
227 #define MEM_FLAG_EDO BIT(MEM_EDO)
228 #define MEM_FLAG_BEDO BIT(MEM_BEDO)
229 #define MEM_FLAG_SDR BIT(MEM_SDR)
230 #define MEM_FLAG_RDR BIT(MEM_RDR)
231 #define MEM_FLAG_DDR BIT(MEM_DDR)
232 #define MEM_FLAG_RDDR BIT(MEM_RDDR)
233 #define MEM_FLAG_RMBS BIT(MEM_RMBS)
234 #define MEM_FLAG_DDR2 BIT(MEM_DDR2)
235 #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2)
236 #define MEM_FLAG_RDDR2 BIT(MEM_RDDR2)
237 #define MEM_FLAG_XDR BIT(MEM_XDR)
238 #define MEM_FLAG_DDR3 BIT(MEM_DDR3)
239 #define MEM_FLAG_RDDR3 BIT(MEM_RDDR3)
240
241 /**
242 * enum edac-type - Error Detection and Correction capabilities and mode
243 * @EDAC_UNKNOWN: Unknown if ECC is available
244 * @EDAC_NONE: Doesn't support ECC
245 * @EDAC_RESERVED: Reserved ECC type
246 * @EDAC_PARITY: Detects parity errors
247 * @EDAC_EC: Error Checking - no correction
248 * @EDAC_SECDED: Single bit error correction, Double detection
249 * @EDAC_S2ECD2ED: Chipkill x2 devices - do these exist?
250 * @EDAC_S4ECD4ED: Chipkill x4 devices
251 * @EDAC_S8ECD8ED: Chipkill x8 devices
252 * @EDAC_S16ECD16ED: Chipkill x16 devices
253 */
254 enum edac_type {
255 EDAC_UNKNOWN = 0,
256 EDAC_NONE,
257 EDAC_RESERVED,
258 EDAC_PARITY,
259 EDAC_EC,
260 EDAC_SECDED,
261 EDAC_S2ECD2ED,
262 EDAC_S4ECD4ED,
263 EDAC_S8ECD8ED,
264 EDAC_S16ECD16ED,
265 };
266
267 #define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
268 #define EDAC_FLAG_NONE BIT(EDAC_NONE)
269 #define EDAC_FLAG_PARITY BIT(EDAC_PARITY)
270 #define EDAC_FLAG_EC BIT(EDAC_EC)
271 #define EDAC_FLAG_SECDED BIT(EDAC_SECDED)
272 #define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED)
273 #define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED)
274 #define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
275 #define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
276
277 /**
278 * enum scrub_type - scrubbing capabilities
279 * @SCRUB_UNKNOWN Unknown if scrubber is available
280 * @SCRUB_NONE: No scrubber
281 * @SCRUB_SW_PROG: SW progressive (sequential) scrubbing
282 * @SCRUB_SW_SRC: Software scrub only errors
283 * @SCRUB_SW_PROG_SRC: Progressive software scrub from an error
284 * @SCRUB_SW_TUNABLE: Software scrub frequency is tunable
285 * @SCRUB_HW_PROG: HW progressive (sequential) scrubbing
286 * @SCRUB_HW_SRC: Hardware scrub only errors
287 * @SCRUB_HW_PROG_SRC: Progressive hardware scrub from an error
288 * SCRUB_HW_TUNABLE: Hardware scrub frequency is tunable
289 */
290 enum scrub_type {
291 SCRUB_UNKNOWN = 0,
292 SCRUB_NONE,
293 SCRUB_SW_PROG,
294 SCRUB_SW_SRC,
295 SCRUB_SW_PROG_SRC,
296 SCRUB_SW_TUNABLE,
297 SCRUB_HW_PROG,
298 SCRUB_HW_SRC,
299 SCRUB_HW_PROG_SRC,
300 SCRUB_HW_TUNABLE
301 };
302
303 #define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
304 #define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC)
305 #define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC)
306 #define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE)
307 #define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG)
308 #define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC)
309 #define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC)
310 #define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE)
311
312 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
313
314 /* EDAC internal operation states */
315 #define OP_ALLOC 0x100
316 #define OP_RUNNING_POLL 0x201
317 #define OP_RUNNING_INTERRUPT 0x202
318 #define OP_RUNNING_POLL_INTR 0x203
319 #define OP_OFFLINE 0x300
320
321 /*
322 * Concepts used at the EDAC subsystem
323 *
324 * There are several things to be aware of that aren't at all obvious:
325 *
326 * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
327 *
328 * These are some of the many terms that are thrown about that don't always
329 * mean what people think they mean (Inconceivable!). In the interest of
330 * creating a common ground for discussion, terms and their definitions
331 * will be established.
332 *
333 * Memory devices: The individual DRAM chips on a memory stick. These
334 * devices commonly output 4 and 8 bits each (x4, x8).
335 * Grouping several of these in parallel provides the
336 * number of bits that the memory controller expects:
337 * typically 72 bits, in order to provide 64 bits +
338 * 8 bits of ECC data.
339 *
340 * Memory Stick: A printed circuit board that aggregates multiple
341 * memory devices in parallel. In general, this is the
342 * Field Replaceable Unit (FRU) which gets replaced, in
343 * the case of excessive errors. Most often it is also
344 * called DIMM (Dual Inline Memory Module).
345 *
346 * Memory Socket: A physical connector on the motherboard that accepts
347 * a single memory stick. Also called as "slot" on several
348 * datasheets.
349 *
350 * Channel: A memory controller channel, responsible to communicate
351 * with a group of DIMMs. Each channel has its own
352 * independent control (command) and data bus, and can
353 * be used independently or grouped with other channels.
354 *
355 * Branch: It is typically the highest hierarchy on a
356 * Fully-Buffered DIMM memory controller.
357 * Typically, it contains two channels.
358 * Two channels at the same branch can be used in single
359 * mode or in lockstep mode.
360 * When lockstep is enabled, the cacheline is doubled,
361 * but it generally brings some performance penalty.
362 * Also, it is generally not possible to point to just one
363 * memory stick when an error occurs, as the error
364 * correction code is calculated using two DIMMs instead
365 * of one. Due to that, it is capable of correcting more
366 * errors than on single mode.
367 *
368 * Single-channel: The data accessed by the memory controller is contained
369 * into one dimm only. E. g. if the data is 64 bits-wide,
370 * the data flows to the CPU using one 64 bits parallel
371 * access.
372 * Typically used with SDR, DDR, DDR2 and DDR3 memories.
373 * FB-DIMM and RAMBUS use a different concept for channel,
374 * so this concept doesn't apply there.
375 *
376 * Double-channel: The data size accessed by the memory controller is
377 * interlaced into two dimms, accessed at the same time.
378 * E. g. if the DIMM is 64 bits-wide (72 bits with ECC),
379 * the data flows to the CPU using a 128 bits parallel
380 * access.
381 *
382 * Chip-select row: This is the name of the DRAM signal used to select the
383 * DRAM ranks to be accessed. Common chip-select rows for
384 * single channel are 64 bits, for dual channel 128 bits.
385 * It may not be visible by the memory controller, as some
386 * DIMM types have a memory buffer that can hide direct
387 * access to it from the Memory Controller.
388 *
389 * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memory.
390 * Motherboards commonly drive two chip-select pins to
391 * a memory stick. A single-ranked stick, will occupy
392 * only one of those rows. The other will be unused.
393 *
394 * Double-Ranked stick: A double-ranked stick has two chip-select rows which
395 * access different sets of memory devices. The two
396 * rows cannot be accessed concurrently.
397 *
398 * Double-sided stick: DEPRECATED TERM, see Double-Ranked stick.
399 * A double-sided stick has two chip-select rows which
400 * access different sets of memory devices. The two
401 * rows cannot be accessed concurrently. "Double-sided"
402 * is irrespective of the memory devices being mounted
403 * on both sides of the memory stick.
404 *
405 * Socket set: All of the memory sticks that are required for
406 * a single memory access or all of the memory sticks
407 * spanned by a chip-select row. A single socket set
408 * has two chip-select rows and if double-sided sticks
409 * are used these will occupy those chip-select rows.
410 *
411 * Bank: This term is avoided because it is unclear when
412 * needing to distinguish between chip-select rows and
413 * socket sets.
414 *
415 * Controller pages:
416 *
417 * Physical pages:
418 *
419 * Virtual pages:
420 *
421 *
422 * STRUCTURE ORGANIZATION AND CHOICES
423 *
424 *
425 *
426 * PS - I enjoyed writing all that about as much as you enjoyed reading it.
427 */
428
429 /**
430 * enum edac_mc_layer - memory controller hierarchy layer
431 *
432 * @EDAC_MC_LAYER_BRANCH: memory layer is named "branch"
433 * @EDAC_MC_LAYER_CHANNEL: memory layer is named "channel"
434 * @EDAC_MC_LAYER_SLOT: memory layer is named "slot"
435 * @EDAC_MC_LAYER_CHIP_SELECT: memory layer is named "chip select"
436 * @EDAC_MC_LAYER_ALL_MEM: memory layout is unknown. All memory is mapped
437 * as a single memory area. This is used when
438 * retrieving errors from a firmware driven driver.
439 *
440 * This enum is used by the drivers to tell edac_mc_sysfs what name should
441 * be used when describing a memory stick location.
442 */
443 enum edac_mc_layer_type {
444 EDAC_MC_LAYER_BRANCH,
445 EDAC_MC_LAYER_CHANNEL,
446 EDAC_MC_LAYER_SLOT,
447 EDAC_MC_LAYER_CHIP_SELECT,
448 EDAC_MC_LAYER_ALL_MEM,
449 };
450
451 /**
452 * struct edac_mc_layer - describes the memory controller hierarchy
453 * @layer: layer type
454 * @size: number of components per layer. For example,
455 * if the channel layer has two channels, size = 2
456 * @is_virt_csrow: This layer is part of the "csrow" when old API
457 * compatibility mode is enabled. Otherwise, it is
458 * a channel
459 */
460 struct edac_mc_layer {
461 enum edac_mc_layer_type type;
462 unsigned size;
463 bool is_virt_csrow;
464 };
465
466 /*
467 * Maximum number of layers used by the memory controller to uniquely
468 * identify a single memory stick.
469 * NOTE: Changing this constant requires not only to change the constant
470 * below, but also to change the existing code at the core, as there are
471 * some code there that are optimized for 3 layers.
472 */
473 #define EDAC_MAX_LAYERS 3
474
475 /**
476 * EDAC_DIMM_OFF - Macro responsible to get a pointer offset inside a pointer array
477 * for the element given by [layer0,layer1,layer2] position
478 *
479 * @layers: a struct edac_mc_layer array, describing how many elements
480 * were allocated for each layer
481 * @n_layers: Number of layers at the @layers array
482 * @layer0: layer0 position
483 * @layer1: layer1 position. Unused if n_layers < 2
484 * @layer2: layer2 position. Unused if n_layers < 3
485 *
486 * For 1 layer, this macro returns &var[layer0] - &var
487 * For 2 layers, this macro is similar to allocate a bi-dimensional array
488 * and to return "&var[layer0][layer1] - &var"
489 * For 3 layers, this macro is similar to allocate a tri-dimensional array
490 * and to return "&var[layer0][layer1][layer2] - &var"
491 *
492 * A loop could be used here to make it more generic, but, as we only have
493 * 3 layers, this is a little faster.
494 * By design, layers can never be 0 or more than 3. If that ever happens,
495 * a NULL is returned, causing an OOPS during the memory allocation routine,
496 * with would point to the developer that he's doing something wrong.
497 */
498 #define EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2) ({ \
499 int __i; \
500 if ((nlayers) == 1) \
501 __i = layer0; \
502 else if ((nlayers) == 2) \
503 __i = (layer1) + ((layers[1]).size * (layer0)); \
504 else if ((nlayers) == 3) \
505 __i = (layer2) + ((layers[2]).size * ((layer1) + \
506 ((layers[1]).size * (layer0)))); \
507 else \
508 __i = -EINVAL; \
509 __i; \
510 })
511
512 /**
513 * EDAC_DIMM_PTR - Macro responsible to get a pointer inside a pointer array
514 * for the element given by [layer0,layer1,layer2] position
515 *
516 * @layers: a struct edac_mc_layer array, describing how many elements
517 * were allocated for each layer
518 * @var: name of the var where we want to get the pointer
519 * (like mci->dimms)
520 * @n_layers: Number of layers at the @layers array
521 * @layer0: layer0 position
522 * @layer1: layer1 position. Unused if n_layers < 2
523 * @layer2: layer2 position. Unused if n_layers < 3
524 *
525 * For 1 layer, this macro returns &var[layer0]
526 * For 2 layers, this macro is similar to allocate a bi-dimensional array
527 * and to return "&var[layer0][layer1]"
528 * For 3 layers, this macro is similar to allocate a tri-dimensional array
529 * and to return "&var[layer0][layer1][layer2]"
530 */
531 #define EDAC_DIMM_PTR(layers, var, nlayers, layer0, layer1, layer2) ({ \
532 typeof(*var) __p; \
533 int ___i = EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2); \
534 if (___i < 0) \
535 __p = NULL; \
536 else \
537 __p = (var)[___i]; \
538 __p; \
539 })
540
541 struct dimm_info {
542 struct device dev;
543
544 char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */
545
546 /* Memory location data */
547 unsigned location[EDAC_MAX_LAYERS];
548
549 struct mem_ctl_info *mci; /* the parent */
550
551 u32 grain; /* granularity of reported error in bytes */
552 enum dev_type dtype; /* memory device type */
553 enum mem_type mtype; /* memory dimm type */
554 enum edac_type edac_mode; /* EDAC mode for this dimm */
555
556 u32 nr_pages; /* number of pages on this dimm */
557
558 unsigned csrow, cschannel; /* Points to the old API data */
559 };
560
561 /**
562 * struct rank_info - contains the information for one DIMM rank
563 *
564 * @chan_idx: channel number where the rank is (typically, 0 or 1)
565 * @ce_count: number of correctable errors for this rank
566 * @csrow: A pointer to the chip select row structure (the parent
567 * structure). The location of the rank is given by
568 * the (csrow->csrow_idx, chan_idx) vector.
569 * @dimm: A pointer to the DIMM structure, where the DIMM label
570 * information is stored.
571 *
572 * FIXME: Currently, the EDAC core model will assume one DIMM per rank.
573 * This is a bad assumption, but it makes this patch easier. Later
574 * patches in this series will fix this issue.
575 */
576 struct rank_info {
577 int chan_idx;
578 struct csrow_info *csrow;
579 struct dimm_info *dimm;
580
581 u32 ce_count; /* Correctable Errors for this csrow */
582 };
583
584 struct csrow_info {
585 struct device dev;
586
587 /* Used only by edac_mc_find_csrow_by_page() */
588 unsigned long first_page; /* first page number in csrow */
589 unsigned long last_page; /* last page number in csrow */
590 unsigned long page_mask; /* used for interleaving -
591 * 0UL for non intlv */
592
593 int csrow_idx; /* the chip-select row */
594
595 u32 ue_count; /* Uncorrectable Errors for this csrow */
596 u32 ce_count; /* Correctable Errors for this csrow */
597
598 struct mem_ctl_info *mci; /* the parent */
599
600 /* channel information for this csrow */
601 u32 nr_channels;
602 struct rank_info **channels;
603 };
604
605 /*
606 * struct errcount_attribute - used to store the several error counts
607 */
608 struct errcount_attribute_data {
609 int n_layers;
610 int pos[EDAC_MAX_LAYERS];
611 int layer0, layer1, layer2;
612 };
613
614 /**
615 * edac_raw_error_desc - Raw error report structure
616 * @grain: minimum granularity for an error report, in bytes
617 * @error_count: number of errors of the same type
618 * @top_layer: top layer of the error (layer[0])
619 * @mid_layer: middle layer of the error (layer[1])
620 * @low_layer: low layer of the error (layer[2])
621 * @page_frame_number: page where the error happened
622 * @offset_in_page: page offset
623 * @syndrome: syndrome of the error (or 0 if unknown or if
624 * the syndrome is not applicable)
625 * @msg: error message
626 * @location: location of the error
627 * @label: label of the affected DIMM(s)
628 * @other_detail: other driver-specific detail about the error
629 * @enable_per_layer_report: if false, the error affects all layers
630 * (typically, a memory controller error)
631 */
632 struct edac_raw_error_desc {
633 /*
634 * NOTE: everything before grain won't be cleaned by
635 * edac_raw_error_desc_clean()
636 */
637 char location[LOCATION_SIZE];
638 char label[(EDAC_MC_LABEL_LEN + 1 + sizeof(OTHER_LABEL)) * EDAC_MAX_LABELS];
639 long grain;
640
641 /* the vars below and grain will be cleaned on every new error report */
642 u16 error_count;
643 int top_layer;
644 int mid_layer;
645 int low_layer;
646 unsigned long page_frame_number;
647 unsigned long offset_in_page;
648 unsigned long syndrome;
649 const char *msg;
650 const char *other_detail;
651 bool enable_per_layer_report;
652 };
653
654 /* MEMORY controller information structure
655 */
656 struct mem_ctl_info {
657 struct device dev;
658 struct bus_type *bus;
659
660 struct list_head link; /* for global list of mem_ctl_info structs */
661
662 struct module *owner; /* Module owner of this control struct */
663
664 unsigned long mtype_cap; /* memory types supported by mc */
665 unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */
666 unsigned long edac_cap; /* configuration capabilities - this is
667 * closely related to edac_ctl_cap. The
668 * difference is that the controller may be
669 * capable of s4ecd4ed which would be listed
670 * in edac_ctl_cap, but if channels aren't
671 * capable of s4ecd4ed then the edac_cap would
672 * not have that capability.
673 */
674 unsigned long scrub_cap; /* chipset scrub capabilities */
675 enum scrub_type scrub_mode; /* current scrub mode */
676
677 /* Translates sdram memory scrub rate given in bytes/sec to the
678 internal representation and configures whatever else needs
679 to be configured.
680 */
681 int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw);
682
683 /* Get the current sdram memory scrub rate from the internal
684 representation and converts it to the closest matching
685 bandwidth in bytes/sec.
686 */
687 int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci);
688
689
690 /* pointer to edac checking routine */
691 void (*edac_check) (struct mem_ctl_info * mci);
692
693 /*
694 * Remaps memory pages: controller pages to physical pages.
695 * For most MC's, this will be NULL.
696 */
697 /* FIXME - why not send the phys page to begin with? */
698 unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
699 unsigned long page);
700 int mc_idx;
701 struct csrow_info **csrows;
702 unsigned nr_csrows, num_cschannel;
703
704 /*
705 * Memory Controller hierarchy
706 *
707 * There are basically two types of memory controller: the ones that
708 * sees memory sticks ("dimms"), and the ones that sees memory ranks.
709 * All old memory controllers enumerate memories per rank, but most
710 * of the recent drivers enumerate memories per DIMM, instead.
711 * When the memory controller is per rank, csbased is true.
712 */
713 unsigned n_layers;
714 struct edac_mc_layer *layers;
715 bool csbased;
716
717 /*
718 * DIMM info. Will eventually remove the entire csrows_info some day
719 */
720 unsigned tot_dimms;
721 struct dimm_info **dimms;
722
723 /*
724 * FIXME - what about controllers on other busses? - IDs must be
725 * unique. dev pointer should be sufficiently unique, but
726 * BUS:SLOT.FUNC numbers may not be unique.
727 */
728 struct device *pdev;
729 const char *mod_name;
730 const char *mod_ver;
731 const char *ctl_name;
732 const char *dev_name;
733 void *pvt_info;
734 unsigned long start_time; /* mci load start time (in jiffies) */
735
736 /*
737 * drivers shouldn't access those fields directly, as the core
738 * already handles that.
739 */
740 u32 ce_noinfo_count, ue_noinfo_count;
741 u32 ue_mc, ce_mc;
742 u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS];
743
744 struct completion complete;
745
746 /* Additional top controller level attributes, but specified
747 * by the low level driver.
748 *
749 * Set by the low level driver to provide attributes at the
750 * controller level.
751 * An array of structures, NULL terminated
752 *
753 * If attributes are desired, then set to array of attributes
754 * If no attributes are desired, leave NULL
755 */
756 const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
757
758 /* work struct for this MC */
759 struct delayed_work work;
760
761 /*
762 * Used to report an error - by being at the global struct
763 * makes the memory allocated by the EDAC core
764 */
765 struct edac_raw_error_desc error_desc;
766
767 /* the internal state of this controller instance */
768 int op_state;
769
770 #ifdef CONFIG_EDAC_DEBUG
771 struct dentry *debugfs;
772 u8 fake_inject_layer[EDAC_MAX_LAYERS];
773 u32 fake_inject_ue;
774 u16 fake_inject_count;
775 #endif
776 };
777
778 /*
779 * Maximum number of memory controllers in the coherent fabric.
780 */
781 #define EDAC_MAX_MCS 16
782
783 #endif
784