1 #ifndef _LINUX_IRQ_H
2 #define _LINUX_IRQ_H
3
4 /*
5 * Please do not include this file in generic code. There is currently
6 * no requirement for any architecture to implement anything held
7 * within this file.
8 *
9 * Thanks. --rmk
10 */
11
12 #include <linux/smp.h>
13 #include <linux/linkage.h>
14 #include <linux/cache.h>
15 #include <linux/spinlock.h>
16 #include <linux/cpumask.h>
17 #include <linux/gfp.h>
18 #include <linux/irqreturn.h>
19 #include <linux/irqnr.h>
20 #include <linux/errno.h>
21 #include <linux/topology.h>
22 #include <linux/wait.h>
23 #include <linux/io.h>
24
25 #include <asm/irq.h>
26 #include <asm/ptrace.h>
27 #include <asm/irq_regs.h>
28
29 struct seq_file;
30 struct module;
31 struct irq_desc;
32 struct irq_data;
33 typedef void (*irq_flow_handler_t)(unsigned int irq,
34 struct irq_desc *desc);
35 typedef void (*irq_preflow_handler_t)(struct irq_data *data);
36
37 /*
38 * IRQ line status.
39 *
40 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
41 *
42 * IRQ_TYPE_NONE - default, unspecified type
43 * IRQ_TYPE_EDGE_RISING - rising edge triggered
44 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
45 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
46 * IRQ_TYPE_LEVEL_HIGH - high level triggered
47 * IRQ_TYPE_LEVEL_LOW - low level triggered
48 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
49 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
50 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type
51 * to setup the HW to a sane default (used
52 * by irqdomain map() callbacks to synchronize
53 * the HW state and SW flags for a newly
54 * allocated descriptor).
55 *
56 * IRQ_TYPE_PROBE - Special flag for probing in progress
57 *
58 * Bits which can be modified via irq_set/clear/modify_status_flags()
59 * IRQ_LEVEL - Interrupt is level type. Will be also
60 * updated in the code when the above trigger
61 * bits are modified via irq_set_irq_type()
62 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
63 * it from affinity setting
64 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
65 * IRQ_NOREQUEST - Interrupt cannot be requested via
66 * request_irq()
67 * IRQ_NOTHREAD - Interrupt cannot be threaded
68 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
69 * request/setup_irq()
70 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
71 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
72 * IRQ_NESTED_TRHEAD - Interrupt nests into another thread
73 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
74 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude
75 * it from the spurious interrupt detection
76 * mechanism and from core side polling.
77 */
78 enum {
79 IRQ_TYPE_NONE = 0x00000000,
80 IRQ_TYPE_EDGE_RISING = 0x00000001,
81 IRQ_TYPE_EDGE_FALLING = 0x00000002,
82 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
83 IRQ_TYPE_LEVEL_HIGH = 0x00000004,
84 IRQ_TYPE_LEVEL_LOW = 0x00000008,
85 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
86 IRQ_TYPE_SENSE_MASK = 0x0000000f,
87 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK,
88
89 IRQ_TYPE_PROBE = 0x00000010,
90
91 IRQ_LEVEL = (1 << 8),
92 IRQ_PER_CPU = (1 << 9),
93 IRQ_NOPROBE = (1 << 10),
94 IRQ_NOREQUEST = (1 << 11),
95 IRQ_NOAUTOEN = (1 << 12),
96 IRQ_NO_BALANCING = (1 << 13),
97 IRQ_MOVE_PCNTXT = (1 << 14),
98 IRQ_NESTED_THREAD = (1 << 15),
99 IRQ_NOTHREAD = (1 << 16),
100 IRQ_PER_CPU_DEVID = (1 << 17),
101 IRQ_IS_POLLED = (1 << 18),
102 };
103
104 #define IRQF_MODIFY_MASK \
105 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
106 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
107 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
108 IRQ_IS_POLLED)
109
110 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
111
112 /*
113 * Return value for chip->irq_set_affinity()
114 *
115 * IRQ_SET_MASK_OK - OK, core updates irq_data.affinity
116 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_data.affinity
117 */
118 enum {
119 IRQ_SET_MASK_OK = 0,
120 IRQ_SET_MASK_OK_NOCOPY,
121 };
122
123 struct msi_desc;
124 struct irq_domain;
125
126 /**
127 * struct irq_data - per irq and irq chip data passed down to chip functions
128 * @mask: precomputed bitmask for accessing the chip registers
129 * @irq: interrupt number
130 * @hwirq: hardware interrupt number, local to the interrupt domain
131 * @node: node index useful for balancing
132 * @state_use_accessors: status information for irq chip functions.
133 * Use accessor functions to deal with it
134 * @chip: low level interrupt hardware access
135 * @domain: Interrupt translation domain; responsible for mapping
136 * between hwirq number and linux irq number.
137 * @handler_data: per-IRQ data for the irq_chip methods
138 * @chip_data: platform-specific per-chip private data for the chip
139 * methods, to allow shared chip implementations
140 * @msi_desc: MSI descriptor
141 * @affinity: IRQ affinity on SMP
142 *
143 * The fields here need to overlay the ones in irq_desc until we
144 * cleaned up the direct references and switched everything over to
145 * irq_data.
146 */
147 struct irq_data {
148 u32 mask;
149 unsigned int irq;
150 unsigned long hwirq;
151 unsigned int node;
152 unsigned int state_use_accessors;
153 struct irq_chip *chip;
154 struct irq_domain *domain;
155 void *handler_data;
156 void *chip_data;
157 struct msi_desc *msi_desc;
158 cpumask_var_t affinity;
159 };
160
161 /*
162 * Bit masks for irq_data.state
163 *
164 * IRQD_TRIGGER_MASK - Mask for the trigger type bits
165 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
166 * IRQD_NO_BALANCING - Balancing disabled for this IRQ
167 * IRQD_PER_CPU - Interrupt is per cpu
168 * IRQD_AFFINITY_SET - Interrupt affinity was set
169 * IRQD_LEVEL - Interrupt is level triggered
170 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
171 * from suspend
172 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process
173 * context
174 * IRQD_IRQ_DISABLED - Disabled state of the interrupt
175 * IRQD_IRQ_MASKED - Masked state of the interrupt
176 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
177 * IRQD_WAKEUP_ARMED - Wakeup mode armed
178 */
179 enum {
180 IRQD_TRIGGER_MASK = 0xf,
181 IRQD_SETAFFINITY_PENDING = (1 << 8),
182 IRQD_NO_BALANCING = (1 << 10),
183 IRQD_PER_CPU = (1 << 11),
184 IRQD_AFFINITY_SET = (1 << 12),
185 IRQD_LEVEL = (1 << 13),
186 IRQD_WAKEUP_STATE = (1 << 14),
187 IRQD_MOVE_PCNTXT = (1 << 15),
188 IRQD_IRQ_DISABLED = (1 << 16),
189 IRQD_IRQ_MASKED = (1 << 17),
190 IRQD_IRQ_INPROGRESS = (1 << 18),
191 IRQD_WAKEUP_ARMED = (1 << 19),
192 };
193
irqd_is_setaffinity_pending(struct irq_data * d)194 static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
195 {
196 return d->state_use_accessors & IRQD_SETAFFINITY_PENDING;
197 }
198
irqd_is_per_cpu(struct irq_data * d)199 static inline bool irqd_is_per_cpu(struct irq_data *d)
200 {
201 return d->state_use_accessors & IRQD_PER_CPU;
202 }
203
irqd_can_balance(struct irq_data * d)204 static inline bool irqd_can_balance(struct irq_data *d)
205 {
206 return !(d->state_use_accessors & (IRQD_PER_CPU | IRQD_NO_BALANCING));
207 }
208
irqd_affinity_was_set(struct irq_data * d)209 static inline bool irqd_affinity_was_set(struct irq_data *d)
210 {
211 return d->state_use_accessors & IRQD_AFFINITY_SET;
212 }
213
irqd_mark_affinity_was_set(struct irq_data * d)214 static inline void irqd_mark_affinity_was_set(struct irq_data *d)
215 {
216 d->state_use_accessors |= IRQD_AFFINITY_SET;
217 }
218
irqd_get_trigger_type(struct irq_data * d)219 static inline u32 irqd_get_trigger_type(struct irq_data *d)
220 {
221 return d->state_use_accessors & IRQD_TRIGGER_MASK;
222 }
223
224 /*
225 * Must only be called inside irq_chip.irq_set_type() functions.
226 */
irqd_set_trigger_type(struct irq_data * d,u32 type)227 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
228 {
229 d->state_use_accessors &= ~IRQD_TRIGGER_MASK;
230 d->state_use_accessors |= type & IRQD_TRIGGER_MASK;
231 }
232
irqd_is_level_type(struct irq_data * d)233 static inline bool irqd_is_level_type(struct irq_data *d)
234 {
235 return d->state_use_accessors & IRQD_LEVEL;
236 }
237
irqd_is_wakeup_set(struct irq_data * d)238 static inline bool irqd_is_wakeup_set(struct irq_data *d)
239 {
240 return d->state_use_accessors & IRQD_WAKEUP_STATE;
241 }
242
irqd_can_move_in_process_context(struct irq_data * d)243 static inline bool irqd_can_move_in_process_context(struct irq_data *d)
244 {
245 return d->state_use_accessors & IRQD_MOVE_PCNTXT;
246 }
247
irqd_irq_disabled(struct irq_data * d)248 static inline bool irqd_irq_disabled(struct irq_data *d)
249 {
250 return d->state_use_accessors & IRQD_IRQ_DISABLED;
251 }
252
irqd_irq_masked(struct irq_data * d)253 static inline bool irqd_irq_masked(struct irq_data *d)
254 {
255 return d->state_use_accessors & IRQD_IRQ_MASKED;
256 }
257
irqd_irq_inprogress(struct irq_data * d)258 static inline bool irqd_irq_inprogress(struct irq_data *d)
259 {
260 return d->state_use_accessors & IRQD_IRQ_INPROGRESS;
261 }
262
irqd_is_wakeup_armed(struct irq_data * d)263 static inline bool irqd_is_wakeup_armed(struct irq_data *d)
264 {
265 return d->state_use_accessors & IRQD_WAKEUP_ARMED;
266 }
267
268
269 /*
270 * Functions for chained handlers which can be enabled/disabled by the
271 * standard disable_irq/enable_irq calls. Must be called with
272 * irq_desc->lock held.
273 */
irqd_set_chained_irq_inprogress(struct irq_data * d)274 static inline void irqd_set_chained_irq_inprogress(struct irq_data *d)
275 {
276 d->state_use_accessors |= IRQD_IRQ_INPROGRESS;
277 }
278
irqd_clr_chained_irq_inprogress(struct irq_data * d)279 static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d)
280 {
281 d->state_use_accessors &= ~IRQD_IRQ_INPROGRESS;
282 }
283
irqd_to_hwirq(struct irq_data * d)284 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
285 {
286 return d->hwirq;
287 }
288
289 /**
290 * struct irq_chip - hardware interrupt chip descriptor
291 *
292 * @name: name for /proc/interrupts
293 * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
294 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
295 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
296 * @irq_disable: disable the interrupt
297 * @irq_ack: start of a new interrupt
298 * @irq_mask: mask an interrupt source
299 * @irq_mask_ack: ack and mask an interrupt source
300 * @irq_unmask: unmask an interrupt source
301 * @irq_eoi: end of interrupt
302 * @irq_set_affinity: set the CPU affinity on SMP machines
303 * @irq_retrigger: resend an IRQ to the CPU
304 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
305 * @irq_set_wake: enable/disable power-management wake-on of an IRQ
306 * @irq_bus_lock: function to lock access to slow bus (i2c) chips
307 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
308 * @irq_cpu_online: configure an interrupt source for a secondary CPU
309 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
310 * @irq_suspend: function called from core code on suspend once per chip
311 * @irq_resume: function called from core code on resume once per chip
312 * @irq_pm_shutdown: function called from core code on shutdown once per chip
313 * @irq_calc_mask: Optional function to set irq_data.mask for special cases
314 * @irq_print_chip: optional to print special chip info in show_interrupts
315 * @irq_request_resources: optional to request resources before calling
316 * any other callback related to this irq
317 * @irq_release_resources: optional to release resources acquired with
318 * irq_request_resources
319 * @flags: chip specific flags
320 */
321 struct irq_chip {
322 const char *name;
323 unsigned int (*irq_startup)(struct irq_data *data);
324 void (*irq_shutdown)(struct irq_data *data);
325 void (*irq_enable)(struct irq_data *data);
326 void (*irq_disable)(struct irq_data *data);
327
328 void (*irq_ack)(struct irq_data *data);
329 void (*irq_mask)(struct irq_data *data);
330 void (*irq_mask_ack)(struct irq_data *data);
331 void (*irq_unmask)(struct irq_data *data);
332 void (*irq_eoi)(struct irq_data *data);
333
334 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
335 int (*irq_retrigger)(struct irq_data *data);
336 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
337 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
338
339 void (*irq_bus_lock)(struct irq_data *data);
340 void (*irq_bus_sync_unlock)(struct irq_data *data);
341
342 void (*irq_cpu_online)(struct irq_data *data);
343 void (*irq_cpu_offline)(struct irq_data *data);
344
345 void (*irq_suspend)(struct irq_data *data);
346 void (*irq_resume)(struct irq_data *data);
347 void (*irq_pm_shutdown)(struct irq_data *data);
348
349 void (*irq_calc_mask)(struct irq_data *data);
350
351 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p);
352 int (*irq_request_resources)(struct irq_data *data);
353 void (*irq_release_resources)(struct irq_data *data);
354
355 unsigned long flags;
356 };
357
358 /*
359 * irq_chip specific flags
360 *
361 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
362 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
363 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
364 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
365 * when irq enabled
366 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip
367 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask
368 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode
369 */
370 enum {
371 IRQCHIP_SET_TYPE_MASKED = (1 << 0),
372 IRQCHIP_EOI_IF_HANDLED = (1 << 1),
373 IRQCHIP_MASK_ON_SUSPEND = (1 << 2),
374 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3),
375 IRQCHIP_SKIP_SET_WAKE = (1 << 4),
376 IRQCHIP_ONESHOT_SAFE = (1 << 5),
377 IRQCHIP_EOI_THREADED = (1 << 6),
378 };
379
380 /* This include will go away once we isolated irq_desc usage to core code */
381 #include <linux/irqdesc.h>
382
383 /*
384 * Pick up the arch-dependent methods:
385 */
386 #include <asm/hw_irq.h>
387
388 #ifndef NR_IRQS_LEGACY
389 # define NR_IRQS_LEGACY 0
390 #endif
391
392 #ifndef ARCH_IRQ_INIT_FLAGS
393 # define ARCH_IRQ_INIT_FLAGS 0
394 #endif
395
396 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
397
398 struct irqaction;
399 extern int setup_irq(unsigned int irq, struct irqaction *new);
400 extern void remove_irq(unsigned int irq, struct irqaction *act);
401 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new);
402 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act);
403
404 extern void irq_cpu_online(void);
405 extern void irq_cpu_offline(void);
406 extern int irq_set_affinity_locked(struct irq_data *data,
407 const struct cpumask *cpumask, bool force);
408
409 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
410 void irq_move_irq(struct irq_data *data);
411 void irq_move_masked_irq(struct irq_data *data);
412 #else
irq_move_irq(struct irq_data * data)413 static inline void irq_move_irq(struct irq_data *data) { }
irq_move_masked_irq(struct irq_data * data)414 static inline void irq_move_masked_irq(struct irq_data *data) { }
415 #endif
416
417 extern int no_irq_affinity;
418
419 #ifdef CONFIG_HARDIRQS_SW_RESEND
420 int irq_set_parent(int irq, int parent_irq);
421 #else
irq_set_parent(int irq,int parent_irq)422 static inline int irq_set_parent(int irq, int parent_irq)
423 {
424 return 0;
425 }
426 #endif
427
428 /*
429 * Built-in IRQ handlers for various IRQ types,
430 * callable via desc->handle_irq()
431 */
432 extern void handle_level_irq(unsigned int irq, struct irq_desc *desc);
433 extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc);
434 extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc);
435 extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc);
436 extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc);
437 extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc);
438 extern void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc);
439 extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc);
440 extern void handle_nested_irq(unsigned int irq);
441
442 /* Handling of unhandled and spurious interrupts: */
443 extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
444 irqreturn_t action_ret);
445
446
447 /* Enable/disable irq debugging output: */
448 extern int noirqdebug_setup(char *str);
449
450 /* Checks whether the interrupt can be requested by request_irq(): */
451 extern int can_request_irq(unsigned int irq, unsigned long irqflags);
452
453 /* Dummy irq-chip implementations: */
454 extern struct irq_chip no_irq_chip;
455 extern struct irq_chip dummy_irq_chip;
456
457 extern void
458 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
459 irq_flow_handler_t handle, const char *name);
460
irq_set_chip_and_handler(unsigned int irq,struct irq_chip * chip,irq_flow_handler_t handle)461 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip,
462 irq_flow_handler_t handle)
463 {
464 irq_set_chip_and_handler_name(irq, chip, handle, NULL);
465 }
466
467 extern int irq_set_percpu_devid(unsigned int irq);
468
469 extern void
470 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
471 const char *name);
472
473 static inline void
irq_set_handler(unsigned int irq,irq_flow_handler_t handle)474 irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
475 {
476 __irq_set_handler(irq, handle, 0, NULL);
477 }
478
479 /*
480 * Set a highlevel chained flow handler for a given IRQ.
481 * (a chained handler is automatically enabled and set to
482 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
483 */
484 static inline void
irq_set_chained_handler(unsigned int irq,irq_flow_handler_t handle)485 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
486 {
487 __irq_set_handler(irq, handle, 1, NULL);
488 }
489
490 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
491
irq_set_status_flags(unsigned int irq,unsigned long set)492 static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
493 {
494 irq_modify_status(irq, 0, set);
495 }
496
irq_clear_status_flags(unsigned int irq,unsigned long clr)497 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
498 {
499 irq_modify_status(irq, clr, 0);
500 }
501
irq_set_noprobe(unsigned int irq)502 static inline void irq_set_noprobe(unsigned int irq)
503 {
504 irq_modify_status(irq, 0, IRQ_NOPROBE);
505 }
506
irq_set_probe(unsigned int irq)507 static inline void irq_set_probe(unsigned int irq)
508 {
509 irq_modify_status(irq, IRQ_NOPROBE, 0);
510 }
511
irq_set_nothread(unsigned int irq)512 static inline void irq_set_nothread(unsigned int irq)
513 {
514 irq_modify_status(irq, 0, IRQ_NOTHREAD);
515 }
516
irq_set_thread(unsigned int irq)517 static inline void irq_set_thread(unsigned int irq)
518 {
519 irq_modify_status(irq, IRQ_NOTHREAD, 0);
520 }
521
irq_set_nested_thread(unsigned int irq,bool nest)522 static inline void irq_set_nested_thread(unsigned int irq, bool nest)
523 {
524 if (nest)
525 irq_set_status_flags(irq, IRQ_NESTED_THREAD);
526 else
527 irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
528 }
529
irq_set_percpu_devid_flags(unsigned int irq)530 static inline void irq_set_percpu_devid_flags(unsigned int irq)
531 {
532 irq_set_status_flags(irq,
533 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD |
534 IRQ_NOPROBE | IRQ_PER_CPU_DEVID);
535 }
536
537 /* Set/get chip/data for an IRQ: */
538 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip);
539 extern int irq_set_handler_data(unsigned int irq, void *data);
540 extern int irq_set_chip_data(unsigned int irq, void *data);
541 extern int irq_set_irq_type(unsigned int irq, unsigned int type);
542 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
543 extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
544 struct msi_desc *entry);
545 extern struct irq_data *irq_get_irq_data(unsigned int irq);
546
irq_get_chip(unsigned int irq)547 static inline struct irq_chip *irq_get_chip(unsigned int irq)
548 {
549 struct irq_data *d = irq_get_irq_data(irq);
550 return d ? d->chip : NULL;
551 }
552
irq_data_get_irq_chip(struct irq_data * d)553 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
554 {
555 return d->chip;
556 }
557
irq_get_chip_data(unsigned int irq)558 static inline void *irq_get_chip_data(unsigned int irq)
559 {
560 struct irq_data *d = irq_get_irq_data(irq);
561 return d ? d->chip_data : NULL;
562 }
563
irq_data_get_irq_chip_data(struct irq_data * d)564 static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
565 {
566 return d->chip_data;
567 }
568
irq_get_handler_data(unsigned int irq)569 static inline void *irq_get_handler_data(unsigned int irq)
570 {
571 struct irq_data *d = irq_get_irq_data(irq);
572 return d ? d->handler_data : NULL;
573 }
574
irq_data_get_irq_handler_data(struct irq_data * d)575 static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
576 {
577 return d->handler_data;
578 }
579
irq_get_msi_desc(unsigned int irq)580 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
581 {
582 struct irq_data *d = irq_get_irq_data(irq);
583 return d ? d->msi_desc : NULL;
584 }
585
irq_data_get_msi(struct irq_data * d)586 static inline struct msi_desc *irq_data_get_msi(struct irq_data *d)
587 {
588 return d->msi_desc;
589 }
590
irq_get_trigger_type(unsigned int irq)591 static inline u32 irq_get_trigger_type(unsigned int irq)
592 {
593 struct irq_data *d = irq_get_irq_data(irq);
594 return d ? irqd_get_trigger_type(d) : 0;
595 }
596
597 unsigned int arch_dynirq_lower_bound(unsigned int from);
598
599 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
600 struct module *owner);
601
602 /* use macros to avoid needing export.h for THIS_MODULE */
603 #define irq_alloc_descs(irq, from, cnt, node) \
604 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE)
605
606 #define irq_alloc_desc(node) \
607 irq_alloc_descs(-1, 0, 1, node)
608
609 #define irq_alloc_desc_at(at, node) \
610 irq_alloc_descs(at, at, 1, node)
611
612 #define irq_alloc_desc_from(from, node) \
613 irq_alloc_descs(-1, from, 1, node)
614
615 #define irq_alloc_descs_from(from, cnt, node) \
616 irq_alloc_descs(-1, from, cnt, node)
617
618 void irq_free_descs(unsigned int irq, unsigned int cnt);
irq_free_desc(unsigned int irq)619 static inline void irq_free_desc(unsigned int irq)
620 {
621 irq_free_descs(irq, 1);
622 }
623
624 #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
625 unsigned int irq_alloc_hwirqs(int cnt, int node);
irq_alloc_hwirq(int node)626 static inline unsigned int irq_alloc_hwirq(int node)
627 {
628 return irq_alloc_hwirqs(1, node);
629 }
630 void irq_free_hwirqs(unsigned int from, int cnt);
irq_free_hwirq(unsigned int irq)631 static inline void irq_free_hwirq(unsigned int irq)
632 {
633 return irq_free_hwirqs(irq, 1);
634 }
635 int arch_setup_hwirq(unsigned int irq, int node);
636 void arch_teardown_hwirq(unsigned int irq);
637 #endif
638
639 #ifdef CONFIG_GENERIC_IRQ_LEGACY
640 void irq_init_desc(unsigned int irq);
641 #endif
642
643 /**
644 * struct irq_chip_regs - register offsets for struct irq_gci
645 * @enable: Enable register offset to reg_base
646 * @disable: Disable register offset to reg_base
647 * @mask: Mask register offset to reg_base
648 * @ack: Ack register offset to reg_base
649 * @eoi: Eoi register offset to reg_base
650 * @type: Type configuration register offset to reg_base
651 * @polarity: Polarity configuration register offset to reg_base
652 */
653 struct irq_chip_regs {
654 unsigned long enable;
655 unsigned long disable;
656 unsigned long mask;
657 unsigned long ack;
658 unsigned long eoi;
659 unsigned long type;
660 unsigned long polarity;
661 };
662
663 /**
664 * struct irq_chip_type - Generic interrupt chip instance for a flow type
665 * @chip: The real interrupt chip which provides the callbacks
666 * @regs: Register offsets for this chip
667 * @handler: Flow handler associated with this chip
668 * @type: Chip can handle these flow types
669 * @mask_cache_priv: Cached mask register private to the chip type
670 * @mask_cache: Pointer to cached mask register
671 *
672 * A irq_generic_chip can have several instances of irq_chip_type when
673 * it requires different functions and register offsets for different
674 * flow types.
675 */
676 struct irq_chip_type {
677 struct irq_chip chip;
678 struct irq_chip_regs regs;
679 irq_flow_handler_t handler;
680 u32 type;
681 u32 mask_cache_priv;
682 u32 *mask_cache;
683 };
684
685 /**
686 * struct irq_chip_generic - Generic irq chip data structure
687 * @lock: Lock to protect register and cache data access
688 * @reg_base: Register base address (virtual)
689 * @irq_base: Interrupt base nr for this chip
690 * @irq_cnt: Number of interrupts handled by this chip
691 * @mask_cache: Cached mask register shared between all chip types
692 * @type_cache: Cached type register
693 * @polarity_cache: Cached polarity register
694 * @wake_enabled: Interrupt can wakeup from suspend
695 * @wake_active: Interrupt is marked as an wakeup from suspend source
696 * @num_ct: Number of available irq_chip_type instances (usually 1)
697 * @private: Private data for non generic chip callbacks
698 * @installed: bitfield to denote installed interrupts
699 * @unused: bitfield to denote unused interrupts
700 * @domain: irq domain pointer
701 * @list: List head for keeping track of instances
702 * @chip_types: Array of interrupt irq_chip_types
703 *
704 * Note, that irq_chip_generic can have multiple irq_chip_type
705 * implementations which can be associated to a particular irq line of
706 * an irq_chip_generic instance. That allows to share and protect
707 * state in an irq_chip_generic instance when we need to implement
708 * different flow mechanisms (level/edge) for it.
709 */
710 struct irq_chip_generic {
711 raw_spinlock_t lock;
712 void __iomem *reg_base;
713 unsigned int irq_base;
714 unsigned int irq_cnt;
715 u32 mask_cache;
716 u32 type_cache;
717 u32 polarity_cache;
718 u32 wake_enabled;
719 u32 wake_active;
720 unsigned int num_ct;
721 void *private;
722 unsigned long installed;
723 unsigned long unused;
724 struct irq_domain *domain;
725 struct list_head list;
726 struct irq_chip_type chip_types[0];
727 };
728
729 /**
730 * enum irq_gc_flags - Initialization flags for generic irq chips
731 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg
732 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
733 * irq chips which need to call irq_set_wake() on
734 * the parent irq. Usually GPIO implementations
735 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
736 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
737 */
738 enum irq_gc_flags {
739 IRQ_GC_INIT_MASK_CACHE = 1 << 0,
740 IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
741 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
742 IRQ_GC_NO_MASK = 1 << 3,
743 };
744
745 /*
746 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
747 * @irqs_per_chip: Number of interrupts per chip
748 * @num_chips: Number of chips
749 * @irq_flags_to_set: IRQ* flags to set on irq setup
750 * @irq_flags_to_clear: IRQ* flags to clear on irq setup
751 * @gc_flags: Generic chip specific setup flags
752 * @gc: Array of pointers to generic interrupt chips
753 */
754 struct irq_domain_chip_generic {
755 unsigned int irqs_per_chip;
756 unsigned int num_chips;
757 unsigned int irq_flags_to_clear;
758 unsigned int irq_flags_to_set;
759 enum irq_gc_flags gc_flags;
760 struct irq_chip_generic *gc[0];
761 };
762
763 /* Generic chip callback functions */
764 void irq_gc_noop(struct irq_data *d);
765 void irq_gc_mask_disable_reg(struct irq_data *d);
766 void irq_gc_mask_set_bit(struct irq_data *d);
767 void irq_gc_mask_clr_bit(struct irq_data *d);
768 void irq_gc_unmask_enable_reg(struct irq_data *d);
769 void irq_gc_ack_set_bit(struct irq_data *d);
770 void irq_gc_ack_clr_bit(struct irq_data *d);
771 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d);
772 void irq_gc_eoi(struct irq_data *d);
773 int irq_gc_set_wake(struct irq_data *d, unsigned int on);
774
775 /* Setup functions for irq_chip_generic */
776 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
777 irq_hw_number_t hw_irq);
778 struct irq_chip_generic *
779 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
780 void __iomem *reg_base, irq_flow_handler_t handler);
781 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
782 enum irq_gc_flags flags, unsigned int clr,
783 unsigned int set);
784 int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
785 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
786 unsigned int clr, unsigned int set);
787
788 struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq);
789 int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
790 int num_ct, const char *name,
791 irq_flow_handler_t handler,
792 unsigned int clr, unsigned int set,
793 enum irq_gc_flags flags);
794
795
irq_data_get_chip_type(struct irq_data * d)796 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
797 {
798 return container_of(d->chip, struct irq_chip_type, chip);
799 }
800
801 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
802
803 #ifdef CONFIG_SMP
irq_gc_lock(struct irq_chip_generic * gc)804 static inline void irq_gc_lock(struct irq_chip_generic *gc)
805 {
806 raw_spin_lock(&gc->lock);
807 }
808
irq_gc_unlock(struct irq_chip_generic * gc)809 static inline void irq_gc_unlock(struct irq_chip_generic *gc)
810 {
811 raw_spin_unlock(&gc->lock);
812 }
813 #else
irq_gc_lock(struct irq_chip_generic * gc)814 static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
irq_gc_unlock(struct irq_chip_generic * gc)815 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
816 #endif
817
818 /*
819 * The irqsave variants are for usage in non interrupt code. Do not use
820 * them in irq_chip callbacks. Use irq_gc_lock() instead.
821 */
822 #define irq_gc_lock_irqsave(gc, flags) \
823 raw_spin_lock_irqsave(&(gc)->lock, flags)
824
825 #define irq_gc_unlock_irqrestore(gc, flags) \
826 raw_spin_unlock_irqrestore(&(gc)->lock, flags)
827
irq_reg_writel(struct irq_chip_generic * gc,u32 val,int reg_offset)828 static inline void irq_reg_writel(struct irq_chip_generic *gc,
829 u32 val, int reg_offset)
830 {
831 writel(val, gc->reg_base + reg_offset);
832 }
833
irq_reg_readl(struct irq_chip_generic * gc,int reg_offset)834 static inline u32 irq_reg_readl(struct irq_chip_generic *gc,
835 int reg_offset)
836 {
837 return readl(gc->reg_base + reg_offset);
838 }
839
840 #endif /* _LINUX_IRQ_H */
841