1 #ifndef MFD_TMIO_H 2 #define MFD_TMIO_H 3 4 #include <linux/device.h> 5 #include <linux/fb.h> 6 #include <linux/io.h> 7 #include <linux/jiffies.h> 8 #include <linux/mmc/card.h> 9 #include <linux/platform_device.h> 10 #include <linux/pm_runtime.h> 11 12 #define tmio_ioread8(addr) readb(addr) 13 #define tmio_ioread16(addr) readw(addr) 14 #define tmio_ioread16_rep(r, b, l) readsw(r, b, l) 15 #define tmio_ioread32(addr) \ 16 (((u32) readw((addr))) | (((u32) readw((addr) + 2)) << 16)) 17 18 #define tmio_iowrite8(val, addr) writeb((val), (addr)) 19 #define tmio_iowrite16(val, addr) writew((val), (addr)) 20 #define tmio_iowrite16_rep(r, b, l) writesw(r, b, l) 21 #define tmio_iowrite32(val, addr) \ 22 do { \ 23 writew((val), (addr)); \ 24 writew((val) >> 16, (addr) + 2); \ 25 } while (0) 26 27 #define CNF_CMD 0x04 28 #define CNF_CTL_BASE 0x10 29 #define CNF_INT_PIN 0x3d 30 #define CNF_STOP_CLK_CTL 0x40 31 #define CNF_GCLK_CTL 0x41 32 #define CNF_SD_CLK_MODE 0x42 33 #define CNF_PIN_STATUS 0x44 34 #define CNF_PWR_CTL_1 0x48 35 #define CNF_PWR_CTL_2 0x49 36 #define CNF_PWR_CTL_3 0x4a 37 #define CNF_CARD_DETECT_MODE 0x4c 38 #define CNF_SD_SLOT 0x50 39 #define CNF_EXT_GCLK_CTL_1 0xf0 40 #define CNF_EXT_GCLK_CTL_2 0xf1 41 #define CNF_EXT_GCLK_CTL_3 0xf9 42 #define CNF_SD_LED_EN_1 0xfa 43 #define CNF_SD_LED_EN_2 0xfe 44 45 #define SDCREN 0x2 /* Enable access to MMC CTL regs. (flag in COMMAND_REG)*/ 46 47 #define sd_config_write8(base, shift, reg, val) \ 48 tmio_iowrite8((val), (base) + ((reg) << (shift))) 49 #define sd_config_write16(base, shift, reg, val) \ 50 tmio_iowrite16((val), (base) + ((reg) << (shift))) 51 #define sd_config_write32(base, shift, reg, val) \ 52 do { \ 53 tmio_iowrite16((val), (base) + ((reg) << (shift))); \ 54 tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \ 55 } while (0) 56 57 /* tmio MMC platform flags */ 58 #define TMIO_MMC_WRPROTECT_DISABLE (1 << 0) 59 /* 60 * Some controllers can support a 2-byte block size when the bus width 61 * is configured in 4-bit mode. 62 */ 63 #define TMIO_MMC_BLKSZ_2BYTES (1 << 1) 64 /* 65 * Some controllers can support SDIO IRQ signalling. 66 */ 67 #define TMIO_MMC_SDIO_IRQ (1 << 2) 68 /* 69 * Some controllers require waiting for the SD bus to become 70 * idle before writing to some registers. 71 */ 72 #define TMIO_MMC_HAS_IDLE_WAIT (1 << 4) 73 /* 74 * A GPIO is used for card hotplug detection. We need an extra flag for this, 75 * because 0 is a valid GPIO number too, and requiring users to specify 76 * cd_gpio < 0 to disable GPIO hotplug would break backwards compatibility. 77 */ 78 #define TMIO_MMC_USE_GPIO_CD (1 << 5) 79 80 /* 81 * Some controllers doesn't have over 0x100 register. 82 * it is used to checking accessibility of 83 * CTL_SD_CARD_CLK_CTL / CTL_CLK_AND_WAIT_CTL 84 */ 85 #define TMIO_MMC_HAVE_HIGH_REG (1 << 6) 86 87 /* 88 * Some controllers have CMD12 automatically 89 * issue/non-issue register 90 */ 91 #define TMIO_MMC_HAVE_CMD12_CTRL (1 << 7) 92 93 /* 94 * Some controllers needs to set 1 on SDIO status reserved bits 95 */ 96 #define TMIO_MMC_SDIO_STATUS_QUIRK (1 << 8) 97 98 /* 99 * Some controllers have DMA enable/disable register 100 */ 101 #define TMIO_MMC_HAVE_CTL_DMA_REG (1 << 9) 102 103 /* 104 * Some controllers allows to set SDx actual clock 105 */ 106 #define TMIO_MMC_CLK_ACTUAL (1 << 10) 107 108 int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base); 109 int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base); 110 void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state); 111 void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state); 112 113 struct dma_chan; 114 115 struct tmio_mmc_dma { 116 void *chan_priv_tx; 117 void *chan_priv_rx; 118 int slave_id_tx; 119 int slave_id_rx; 120 int alignment_shift; 121 dma_addr_t dma_rx_offset; 122 bool (*filter)(struct dma_chan *chan, void *arg); 123 }; 124 125 struct tmio_mmc_host; 126 127 /* 128 * data for the MMC controller 129 */ 130 struct tmio_mmc_data { 131 unsigned int hclk; 132 unsigned long capabilities; 133 unsigned long capabilities2; 134 unsigned long flags; 135 unsigned long bus_shift; 136 u32 ocr_mask; /* available voltages */ 137 struct tmio_mmc_dma *dma; 138 struct device *dev; 139 unsigned int cd_gpio; 140 void (*set_pwr)(struct platform_device *host, int state); 141 void (*set_clk_div)(struct platform_device *host, int state); 142 int (*write16_hook)(struct tmio_mmc_host *host, int addr); 143 /* clock management callbacks */ 144 int (*clk_enable)(struct platform_device *pdev, unsigned int *f); 145 void (*clk_disable)(struct platform_device *pdev); 146 int (*multi_io_quirk)(struct mmc_card *card, 147 unsigned int direction, int blk_size); 148 }; 149 150 /* 151 * data for the NAND controller 152 */ 153 struct tmio_nand_data { 154 struct nand_bbt_descr *badblock_pattern; 155 struct mtd_partition *partition; 156 unsigned int num_partitions; 157 }; 158 159 #define FBIO_TMIO_ACC_WRITE 0x7C639300 160 #define FBIO_TMIO_ACC_SYNC 0x7C639301 161 162 struct tmio_fb_data { 163 int (*lcd_set_power)(struct platform_device *fb_dev, 164 bool on); 165 int (*lcd_mode)(struct platform_device *fb_dev, 166 const struct fb_videomode *mode); 167 int num_modes; 168 struct fb_videomode *modes; 169 170 /* in mm: size of screen */ 171 int height; 172 int width; 173 }; 174 175 176 #endif 177