1 /*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX4_QP_H
34 #define MLX4_QP_H
35
36 #include <linux/types.h>
37 #include <linux/if_ether.h>
38
39 #include <linux/mlx4/device.h>
40
41 #define MLX4_INVALID_LKEY 0x100
42
43 enum mlx4_qp_optpar {
44 MLX4_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
45 MLX4_QP_OPTPAR_RRE = 1 << 1,
46 MLX4_QP_OPTPAR_RAE = 1 << 2,
47 MLX4_QP_OPTPAR_RWE = 1 << 3,
48 MLX4_QP_OPTPAR_PKEY_INDEX = 1 << 4,
49 MLX4_QP_OPTPAR_Q_KEY = 1 << 5,
50 MLX4_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
51 MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
52 MLX4_QP_OPTPAR_SRA_MAX = 1 << 8,
53 MLX4_QP_OPTPAR_RRA_MAX = 1 << 9,
54 MLX4_QP_OPTPAR_PM_STATE = 1 << 10,
55 MLX4_QP_OPTPAR_RETRY_COUNT = 1 << 12,
56 MLX4_QP_OPTPAR_RNR_RETRY = 1 << 13,
57 MLX4_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
58 MLX4_QP_OPTPAR_SCHED_QUEUE = 1 << 16,
59 MLX4_QP_OPTPAR_COUNTER_INDEX = 1 << 20,
60 MLX4_QP_OPTPAR_VLAN_STRIPPING = 1 << 21,
61 };
62
63 enum mlx4_qp_state {
64 MLX4_QP_STATE_RST = 0,
65 MLX4_QP_STATE_INIT = 1,
66 MLX4_QP_STATE_RTR = 2,
67 MLX4_QP_STATE_RTS = 3,
68 MLX4_QP_STATE_SQER = 4,
69 MLX4_QP_STATE_SQD = 5,
70 MLX4_QP_STATE_ERR = 6,
71 MLX4_QP_STATE_SQ_DRAINING = 7,
72 MLX4_QP_NUM_STATE
73 };
74
75 enum {
76 MLX4_QP_ST_RC = 0x0,
77 MLX4_QP_ST_UC = 0x1,
78 MLX4_QP_ST_RD = 0x2,
79 MLX4_QP_ST_UD = 0x3,
80 MLX4_QP_ST_XRC = 0x6,
81 MLX4_QP_ST_MLX = 0x7
82 };
83
84 enum {
85 MLX4_QP_PM_MIGRATED = 0x3,
86 MLX4_QP_PM_ARMED = 0x0,
87 MLX4_QP_PM_REARM = 0x1
88 };
89
90 enum {
91 /* params1 */
92 MLX4_QP_BIT_SRE = 1 << 15,
93 MLX4_QP_BIT_SWE = 1 << 14,
94 MLX4_QP_BIT_SAE = 1 << 13,
95 /* params2 */
96 MLX4_QP_BIT_RRE = 1 << 15,
97 MLX4_QP_BIT_RWE = 1 << 14,
98 MLX4_QP_BIT_RAE = 1 << 13,
99 MLX4_QP_BIT_RIC = 1 << 4,
100 };
101
102 enum {
103 MLX4_RSS_HASH_XOR = 0,
104 MLX4_RSS_HASH_TOP = 1,
105
106 MLX4_RSS_UDP_IPV6 = 1 << 0,
107 MLX4_RSS_UDP_IPV4 = 1 << 1,
108 MLX4_RSS_TCP_IPV6 = 1 << 2,
109 MLX4_RSS_IPV6 = 1 << 3,
110 MLX4_RSS_TCP_IPV4 = 1 << 4,
111 MLX4_RSS_IPV4 = 1 << 5,
112
113 MLX4_RSS_BY_OUTER_HEADERS = 0 << 6,
114 MLX4_RSS_BY_INNER_HEADERS = 2 << 6,
115 MLX4_RSS_BY_INNER_HEADERS_IPONLY = 3 << 6,
116
117 /* offset of mlx4_rss_context within mlx4_qp_context.pri_path */
118 MLX4_RSS_OFFSET_IN_QPC_PRI_PATH = 0x24,
119 /* offset of being RSS indirection QP within mlx4_qp_context.flags */
120 MLX4_RSS_QPC_FLAG_OFFSET = 13,
121 };
122
123 struct mlx4_rss_context {
124 __be32 base_qpn;
125 __be32 default_qpn;
126 u16 reserved;
127 u8 hash_fn;
128 u8 flags;
129 __be32 rss_key[10];
130 __be32 base_qpn_udp;
131 };
132
133 struct mlx4_qp_path {
134 u8 fl;
135 u8 vlan_control;
136 u8 disable_pkey_check;
137 u8 pkey_index;
138 u8 counter_index;
139 u8 grh_mylmc;
140 __be16 rlid;
141 u8 ackto;
142 u8 mgid_index;
143 u8 static_rate;
144 u8 hop_limit;
145 __be32 tclass_flowlabel;
146 u8 rgid[16];
147 u8 sched_queue;
148 u8 vlan_index;
149 u8 feup;
150 u8 fvl_rx;
151 u8 reserved4[2];
152 u8 dmac[ETH_ALEN];
153 };
154
155 enum { /* fl */
156 MLX4_FL_CV = 1 << 6,
157 MLX4_FL_ETH_HIDE_CQE_VLAN = 1 << 2
158 };
159 enum { /* vlan_control */
160 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED = 1 << 6,
161 MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED = 1 << 5, /* 802.1p priority tag */
162 MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED = 1 << 4,
163 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED = 1 << 2,
164 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED = 1 << 1, /* 802.1p priority tag */
165 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED = 1 << 0
166 };
167
168 enum { /* feup */
169 MLX4_FEUP_FORCE_ETH_UP = 1 << 6, /* force Eth UP */
170 MLX4_FSM_FORCE_ETH_SRC_MAC = 1 << 5, /* force Source MAC */
171 MLX4_FVL_FORCE_ETH_VLAN = 1 << 3 /* force Eth vlan */
172 };
173
174 enum { /* fvl_rx */
175 MLX4_FVL_RX_FORCE_ETH_VLAN = 1 << 0 /* enforce Eth rx vlan */
176 };
177
178 struct mlx4_qp_context {
179 __be32 flags;
180 __be32 pd;
181 u8 mtu_msgmax;
182 u8 rq_size_stride;
183 u8 sq_size_stride;
184 u8 rlkey;
185 __be32 usr_page;
186 __be32 local_qpn;
187 __be32 remote_qpn;
188 struct mlx4_qp_path pri_path;
189 struct mlx4_qp_path alt_path;
190 __be32 params1;
191 u32 reserved1;
192 __be32 next_send_psn;
193 __be32 cqn_send;
194 u32 reserved2[2];
195 __be32 last_acked_psn;
196 __be32 ssn;
197 __be32 params2;
198 __be32 rnr_nextrecvpsn;
199 __be32 xrcd;
200 __be32 cqn_recv;
201 __be64 db_rec_addr;
202 __be32 qkey;
203 __be32 srqn;
204 __be32 msn;
205 __be16 rq_wqe_counter;
206 __be16 sq_wqe_counter;
207 u32 reserved3[2];
208 __be32 param3;
209 __be32 nummmcpeers_basemkey;
210 u8 log_page_size;
211 u8 reserved4[2];
212 u8 mtt_base_addr_h;
213 __be32 mtt_base_addr_l;
214 u32 reserved5[10];
215 };
216
217 struct mlx4_update_qp_context {
218 __be64 qp_mask;
219 __be64 primary_addr_path_mask;
220 __be64 secondary_addr_path_mask;
221 u64 reserved1;
222 struct mlx4_qp_context qp_context;
223 u64 reserved2[58];
224 };
225
226 enum {
227 MLX4_UPD_QP_MASK_PM_STATE = 32,
228 MLX4_UPD_QP_MASK_VSD = 33,
229 };
230
231 enum {
232 MLX4_UPD_QP_PATH_MASK_PKEY_INDEX = 0 + 32,
233 MLX4_UPD_QP_PATH_MASK_FSM = 1 + 32,
234 MLX4_UPD_QP_PATH_MASK_MAC_INDEX = 2 + 32,
235 MLX4_UPD_QP_PATH_MASK_FVL = 3 + 32,
236 MLX4_UPD_QP_PATH_MASK_CV = 4 + 32,
237 MLX4_UPD_QP_PATH_MASK_VLAN_INDEX = 5 + 32,
238 MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN = 6 + 32,
239 MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED = 7 + 32,
240 MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P = 8 + 32,
241 MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED = 9 + 32,
242 MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED = 10 + 32,
243 MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P = 11 + 32,
244 MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED = 12 + 32,
245 MLX4_UPD_QP_PATH_MASK_FEUP = 13 + 32,
246 MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE = 14 + 32,
247 MLX4_UPD_QP_PATH_MASK_IF_COUNTER_INDEX = 15 + 32,
248 MLX4_UPD_QP_PATH_MASK_FVL_RX = 16 + 32,
249 };
250
251 enum { /* param3 */
252 MLX4_STRIP_VLAN = 1 << 30
253 };
254
255 /* Which firmware version adds support for NEC (NoErrorCompletion) bit */
256 #define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232)
257
258 enum {
259 MLX4_WQE_CTRL_NEC = 1 << 29,
260 MLX4_WQE_CTRL_IIP = 1 << 28,
261 MLX4_WQE_CTRL_ILP = 1 << 27,
262 MLX4_WQE_CTRL_FENCE = 1 << 6,
263 MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2,
264 MLX4_WQE_CTRL_SOLICITED = 1 << 1,
265 MLX4_WQE_CTRL_IP_CSUM = 1 << 4,
266 MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5,
267 MLX4_WQE_CTRL_INS_VLAN = 1 << 6,
268 MLX4_WQE_CTRL_STRONG_ORDER = 1 << 7,
269 MLX4_WQE_CTRL_FORCE_LOOPBACK = 1 << 0,
270 };
271
272 struct mlx4_wqe_ctrl_seg {
273 __be32 owner_opcode;
274 union {
275 struct {
276 __be16 vlan_tag;
277 u8 ins_vlan;
278 u8 fence_size;
279 };
280 __be32 bf_qpn;
281 };
282 /*
283 * High 24 bits are SRC remote buffer; low 8 bits are flags:
284 * [7] SO (strong ordering)
285 * [5] TCP/UDP checksum
286 * [4] IP checksum
287 * [3:2] C (generate completion queue entry)
288 * [1] SE (solicited event)
289 * [0] FL (force loopback)
290 */
291 union {
292 __be32 srcrb_flags;
293 __be16 srcrb_flags16[2];
294 };
295 /*
296 * imm is immediate data for send/RDMA write w/ immediate;
297 * also invalidation key for send with invalidate; input
298 * modifier for WQEs on CCQs.
299 */
300 __be32 imm;
301 };
302
303 enum {
304 MLX4_WQE_MLX_VL15 = 1 << 17,
305 MLX4_WQE_MLX_SLR = 1 << 16
306 };
307
308 struct mlx4_wqe_mlx_seg {
309 u8 owner;
310 u8 reserved1[2];
311 u8 opcode;
312 __be16 sched_prio;
313 u8 reserved2;
314 u8 size;
315 /*
316 * [17] VL15
317 * [16] SLR
318 * [15:12] static rate
319 * [11:8] SL
320 * [4] ICRC
321 * [3:2] C
322 * [0] FL (force loopback)
323 */
324 __be32 flags;
325 __be16 rlid;
326 u16 reserved3;
327 };
328
329 struct mlx4_wqe_datagram_seg {
330 __be32 av[8];
331 __be32 dqpn;
332 __be32 qkey;
333 __be16 vlan;
334 u8 mac[ETH_ALEN];
335 };
336
337 struct mlx4_wqe_lso_seg {
338 __be32 mss_hdr_size;
339 __be32 header[0];
340 };
341
342 enum mlx4_wqe_bind_seg_flags2 {
343 MLX4_WQE_BIND_ZERO_BASED = (1 << 30),
344 MLX4_WQE_BIND_TYPE_2 = (1 << 31),
345 };
346
347 struct mlx4_wqe_bind_seg {
348 __be32 flags1;
349 __be32 flags2;
350 __be32 new_rkey;
351 __be32 lkey;
352 __be64 addr;
353 __be64 length;
354 };
355
356 enum {
357 MLX4_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
358 MLX4_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
359 MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ = 1 << 29,
360 MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE = 1 << 30,
361 MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC = 1 << 31
362 };
363
364 struct mlx4_wqe_fmr_seg {
365 __be32 flags;
366 __be32 mem_key;
367 __be64 buf_list;
368 __be64 start_addr;
369 __be64 reg_len;
370 __be32 offset;
371 __be32 page_size;
372 u32 reserved[2];
373 };
374
375 struct mlx4_wqe_fmr_ext_seg {
376 u8 flags;
377 u8 reserved;
378 __be16 app_mask;
379 __be16 wire_app_tag;
380 __be16 mem_app_tag;
381 __be32 wire_ref_tag_base;
382 __be32 mem_ref_tag_base;
383 };
384
385 struct mlx4_wqe_local_inval_seg {
386 u64 reserved1;
387 __be32 mem_key;
388 u32 reserved2;
389 u64 reserved3[2];
390 };
391
392 struct mlx4_wqe_raddr_seg {
393 __be64 raddr;
394 __be32 rkey;
395 u32 reserved;
396 };
397
398 struct mlx4_wqe_atomic_seg {
399 __be64 swap_add;
400 __be64 compare;
401 };
402
403 struct mlx4_wqe_masked_atomic_seg {
404 __be64 swap_add;
405 __be64 compare;
406 __be64 swap_add_mask;
407 __be64 compare_mask;
408 };
409
410 struct mlx4_wqe_data_seg {
411 __be32 byte_count;
412 __be32 lkey;
413 __be64 addr;
414 };
415
416 enum {
417 MLX4_INLINE_ALIGN = 64,
418 MLX4_INLINE_SEG = 1 << 31,
419 };
420
421 struct mlx4_wqe_inline_seg {
422 __be32 byte_count;
423 };
424
425 enum mlx4_update_qp_attr {
426 MLX4_UPDATE_QP_SMAC = 1 << 0,
427 MLX4_UPDATE_QP_VSD = 1 << 2,
428 MLX4_UPDATE_QP_SUPPORTED_ATTRS = (1 << 2) - 1
429 };
430
431 enum mlx4_update_qp_params_flags {
432 MLX4_UPDATE_QP_PARAMS_FLAGS_VSD_ENABLE = 1 << 0,
433 };
434
435 struct mlx4_update_qp_params {
436 u8 smac_index;
437 u32 flags;
438 };
439
440 int mlx4_update_qp(struct mlx4_dev *dev, u32 qpn,
441 enum mlx4_update_qp_attr attr,
442 struct mlx4_update_qp_params *params);
443 int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
444 enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
445 struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar,
446 int sqd_event, struct mlx4_qp *qp);
447
448 int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp,
449 struct mlx4_qp_context *context);
450
451 int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
452 struct mlx4_qp_context *context,
453 struct mlx4_qp *qp, enum mlx4_qp_state *qp_state);
454
__mlx4_qp_lookup(struct mlx4_dev * dev,u32 qpn)455 static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn)
456 {
457 return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1));
458 }
459
460 void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp);
461
462 #endif /* MLX4_QP_H */
463