1 /*
2 * pxa2xx_ssp.h
3 *
4 * Copyright (C) 2003 Russell King, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This driver supports the following PXA CPU/SSP ports:-
11 *
12 * PXA250 SSP
13 * PXA255 SSP, NSSP
14 * PXA26x SSP, NSSP, ASSP
15 * PXA27x SSP1, SSP2, SSP3
16 * PXA3xx SSP1, SSP2, SSP3, SSP4
17 */
18
19 #ifndef __LINUX_SSP_H
20 #define __LINUX_SSP_H
21
22 #include <linux/list.h>
23 #include <linux/io.h>
24 #include <linux/of.h>
25
26
27 /*
28 * SSP Serial Port Registers
29 * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
30 * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
31 */
32
33 #define SSCR0 (0x00) /* SSP Control Register 0 */
34 #define SSCR1 (0x04) /* SSP Control Register 1 */
35 #define SSSR (0x08) /* SSP Status Register */
36 #define SSITR (0x0C) /* SSP Interrupt Test Register */
37 #define SSDR (0x10) /* SSP Data Write/Data Read Register */
38
39 #define SSTO (0x28) /* SSP Time Out Register */
40 #define SSPSP (0x2C) /* SSP Programmable Serial Protocol */
41 #define SSTSA (0x30) /* SSP Tx Timeslot Active */
42 #define SSRSA (0x34) /* SSP Rx Timeslot Active */
43 #define SSTSS (0x38) /* SSP Timeslot Status */
44 #define SSACD (0x3C) /* SSP Audio Clock Divider */
45 #define SSACDD (0x40) /* SSP Audio Clock Dither Divider */
46
47 /* Common PXA2xx bits first */
48 #define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
49 #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
50 #define SSCR0_FRF (0x00000030) /* FRame Format (mask) */
51 #define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */
52 #define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */
53 #define SSCR0_National (0x2 << 4) /* National Microwire */
54 #define SSCR0_ECS (1 << 6) /* External clock select */
55 #define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
56 #define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */
57
58 /* PXA27x, PXA3xx */
59 #define SSCR0_EDSS (1 << 20) /* Extended data size select */
60 #define SSCR0_NCS (1 << 21) /* Network clock select */
61 #define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */
62 #define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */
63 #define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */
64 #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
65 #define SSCR0_FPCKE (1 << 29) /* FIFO packing enable */
66 #define SSCR0_ACS (1 << 30) /* Audio clock select */
67 #define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
68
69
70 #define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
71 #define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
72 #define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
73 #define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */
74 #define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
75 #define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
76
77 #define SSSR_ALT_FRM_MASK 3 /* Masks the SFRM signal number */
78 #define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
79 #define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
80 #define SSSR_BSY (1 << 4) /* SSP Busy */
81 #define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
82 #define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
83 #define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
84
85 #ifdef CONFIG_ARCH_PXA
86 #define RX_THRESH_DFLT 8
87 #define TX_THRESH_DFLT 8
88
89 #define SSSR_TFL_MASK (0xf << 8) /* Transmit FIFO Level mask */
90 #define SSSR_RFL_MASK (0xf << 12) /* Receive FIFO Level mask */
91
92 #define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */
93 #define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
94 #define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */
95 #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
96
97 #else
98
99 #define RX_THRESH_DFLT 2
100 #define TX_THRESH_DFLT 2
101
102 #define SSSR_TFL_MASK (0x3 << 8) /* Transmit FIFO Level mask */
103 #define SSSR_RFL_MASK (0x3 << 12) /* Receive FIFO Level mask */
104
105 #define SSCR1_TFT (0x000000c0) /* Transmit FIFO Threshold (mask) */
106 #define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..4] */
107 #define SSCR1_RFT (0x00000c00) /* Receive FIFO Threshold (mask) */
108 #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */
109 #endif
110
111 /* extra bits in PXA255, PXA26x and PXA27x SSP ports */
112 #define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */
113 #define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
114 #define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */
115 #define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */
116 #define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */
117 #define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */
118 #define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */
119 #define SSCR1_ECRB (1 << 26) /* Enable Clock request B */
120 #define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */
121 #define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */
122 #define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */
123 #define SSCR1_TRAIL (1 << 22) /* Trailing Byte */
124 #define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */
125 #define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */
126 #define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */
127 #define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interrupt Enable */
128 #define SSCR1_IFS (1 << 16) /* Invert Frame Signal */
129 #define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */
130 #define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */
131
132 #define SSSR_BCE (1 << 23) /* Bit Count Error */
133 #define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */
134 #define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */
135 #define SSSR_EOC (1 << 20) /* End Of Chain */
136 #define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
137 #define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */
138
139
140 #define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */
141 #define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */
142 #define SSPSP_ETDS (1 << 3) /* End of Transfer data State */
143 #define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */
144 #define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */
145 #define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */
146 #define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */
147 #define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */
148 #define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */
149
150 /* PXA3xx */
151 #define SSPSP_EDMYSTRT(x) ((x) << 26) /* Extended Dummy Start */
152 #define SSPSP_EDMYSTOP(x) ((x) << 28) /* Extended Dummy Stop */
153 #define SSPSP_TIMING_MASK (0x7f8001f0)
154
155 #define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */
156 #define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
157 #define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
158 #define SSACD_SCDX8 (1 << 7) /* SYSCLK division ratio select */
159
160 /* LPSS SSP */
161 #define SSITF 0x44 /* TX FIFO trigger level */
162 #define SSITF_TxLoThresh(x) (((x) - 1) << 8)
163 #define SSITF_TxHiThresh(x) ((x) - 1)
164
165 #define SSIRF 0x48 /* RX FIFO trigger level */
166 #define SSIRF_RxThresh(x) ((x) - 1)
167
168 enum pxa_ssp_type {
169 SSP_UNDEFINED = 0,
170 PXA25x_SSP, /* pxa 210, 250, 255, 26x */
171 PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
172 PXA27x_SSP,
173 PXA3xx_SSP,
174 PXA168_SSP,
175 PXA910_SSP,
176 CE4100_SSP,
177 LPSS_SSP,
178 };
179
180 struct ssp_device {
181 struct platform_device *pdev;
182 struct list_head node;
183
184 struct clk *clk;
185 void __iomem *mmio_base;
186 unsigned long phys_base;
187
188 const char *label;
189 int port_id;
190 int type;
191 int use_count;
192 int irq;
193 int drcmr_rx;
194 int drcmr_tx;
195
196 struct device_node *of_node;
197 };
198
199 /**
200 * pxa_ssp_write_reg - Write to a SSP register
201 *
202 * @dev: SSP device to access
203 * @reg: Register to write to
204 * @val: Value to be written.
205 */
pxa_ssp_write_reg(struct ssp_device * dev,u32 reg,u32 val)206 static inline void pxa_ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val)
207 {
208 __raw_writel(val, dev->mmio_base + reg);
209 }
210
211 /**
212 * pxa_ssp_read_reg - Read from a SSP register
213 *
214 * @dev: SSP device to access
215 * @reg: Register to read from
216 */
pxa_ssp_read_reg(struct ssp_device * dev,u32 reg)217 static inline u32 pxa_ssp_read_reg(struct ssp_device *dev, u32 reg)
218 {
219 return __raw_readl(dev->mmio_base + reg);
220 }
221
222 #if IS_ENABLED(CONFIG_PXA_SSP)
223 struct ssp_device *pxa_ssp_request(int port, const char *label);
224 void pxa_ssp_free(struct ssp_device *);
225 struct ssp_device *pxa_ssp_request_of(const struct device_node *of_node,
226 const char *label);
227 #else
pxa_ssp_request(int port,const char * label)228 static inline struct ssp_device *pxa_ssp_request(int port, const char *label)
229 {
230 return NULL;
231 }
pxa_ssp_request_of(const struct device_node * n,const char * name)232 static inline struct ssp_device *pxa_ssp_request_of(const struct device_node *n,
233 const char *name)
234 {
235 return NULL;
236 }
pxa_ssp_free(struct ssp_device * ssp)237 static inline void pxa_ssp_free(struct ssp_device *ssp) {}
238 #endif
239
240 #endif
241