1 /* 2 * Copyright (C) 2007 Google, Inc. 3 * Author: Brian Swetland <swetland@google.com> 4 * 5 * This software is licensed under the terms of the GNU General Public 6 * License version 2, as published by the Free Software Foundation, and 7 * may be copied, distributed, and modified under those terms. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 */ 15 16 #ifndef __LINUX_USB_GADGET_MSM72K_UDC_H__ 17 #define __LINUX_USB_GADGET_MSM72K_UDC_H__ 18 19 /* USB phy selector - in TCSR address range */ 20 #define USB2_PHY_SEL 0xfd4ab000 21 22 #define USB_AHBBURST (MSM_USB_BASE + 0x0090) 23 #define USB_AHBMODE (MSM_USB_BASE + 0x0098) 24 #define USB_CAPLENGTH (MSM_USB_BASE + 0x0100) /* 8 bit */ 25 26 #define USB_USBCMD (MSM_USB_BASE + 0x0140) 27 #define USB_PORTSC (MSM_USB_BASE + 0x0184) 28 #define USB_OTGSC (MSM_USB_BASE + 0x01A4) 29 #define USB_USBMODE (MSM_USB_BASE + 0x01A8) 30 #define USB_PHY_CTRL (MSM_USB_BASE + 0x0240) 31 #define USB_PHY_CTRL2 (MSM_USB_BASE + 0x0278) 32 33 #define USBCMD_RESET 2 34 #define USB_USBINTR (MSM_USB_BASE + 0x0148) 35 36 #define PORTSC_PHCD (1 << 23) /* phy suspend mode */ 37 #define PORTSC_PTS_MASK (3 << 30) 38 #define PORTSC_PTS_ULPI (2 << 30) 39 #define PORTSC_PTS_SERIAL (3 << 30) 40 41 #define USB_ULPI_VIEWPORT (MSM_USB_BASE + 0x0170) 42 #define ULPI_RUN (1 << 30) 43 #define ULPI_WRITE (1 << 29) 44 #define ULPI_READ (0 << 29) 45 #define ULPI_ADDR(n) (((n) & 255) << 16) 46 #define ULPI_DATA(n) ((n) & 255) 47 #define ULPI_DATA_READ(n) (((n) >> 8) & 255) 48 49 /* synopsys 28nm phy registers */ 50 #define ULPI_PWR_CLK_MNG_REG 0x88 51 #define OTG_COMP_DISABLE BIT(0) 52 53 #define ASYNC_INTR_CTRL (1 << 29) /* Enable async interrupt */ 54 #define ULPI_STP_CTRL (1 << 30) /* Block communication with PHY */ 55 #define PHY_RETEN (1 << 1) /* PHY retention enable/disable */ 56 #define PHY_POR_ASSERT (1 << 0) /* USB2 28nm PHY POR ASSERT */ 57 58 /* OTG definitions */ 59 #define OTGSC_INTSTS_MASK (0x7f << 16) 60 #define OTGSC_ID (1 << 8) 61 #define OTGSC_BSV (1 << 11) 62 #define OTGSC_IDIS (1 << 16) 63 #define OTGSC_BSVIS (1 << 19) 64 #define OTGSC_IDIE (1 << 24) 65 #define OTGSC_BSVIE (1 << 27) 66 67 #endif /* __LINUX_USB_GADGET_MSM72K_UDC_H__ */ 68