1 /* 2 * USB 338x super/high/full speed USB device controller. 3 * Unlike many such controllers, this one talks PCI. 4 * 5 * Copyright (C) 2002 NetChip Technology, Inc. (http://www.netchip.com) 6 * Copyright (C) 2003 David Brownell 7 * Copyright (C) 2014 Ricardo Ribalda - Qtechnology/AS 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 */ 20 21 #ifndef __LINUX_USB_USB338X_H 22 #define __LINUX_USB_USB338X_H 23 24 #include <linux/usb/net2280.h> 25 26 /* 27 * Extra defined bits for net2280 registers 28 */ 29 #define SCRATCH 0x0b 30 31 #define DEFECT7374_FSM_FIELD 28 32 #define SUPER_SPEED 8 33 #define DMA_REQUEST_OUTSTANDING 5 34 #define DMA_PAUSE_DONE_INTERRUPT 26 35 #define SET_ISOCHRONOUS_DELAY 24 36 #define SET_SEL 22 37 #define SUPER_SPEED_MODE 8 38 39 /*ep_cfg*/ 40 #define MAX_BURST_SIZE 24 41 #define EP_FIFO_BYTE_COUNT 16 42 #define IN_ENDPOINT_ENABLE 14 43 #define IN_ENDPOINT_TYPE 12 44 #define OUT_ENDPOINT_ENABLE 10 45 #define OUT_ENDPOINT_TYPE 8 46 47 struct usb338x_usb_ext_regs { 48 u32 usbclass; 49 #define DEVICE_PROTOCOL 16 50 #define DEVICE_SUB_CLASS 8 51 #define DEVICE_CLASS 0 52 u32 ss_sel; 53 #define U2_SYSTEM_EXIT_LATENCY 8 54 #define U1_SYSTEM_EXIT_LATENCY 0 55 u32 ss_del; 56 #define U2_DEVICE_EXIT_LATENCY 8 57 #define U1_DEVICE_EXIT_LATENCY 0 58 u32 usb2lpm; 59 #define USB_L1_LPM_HIRD 2 60 #define USB_L1_LPM_REMOTE_WAKE 1 61 #define USB_L1_LPM_SUPPORT 0 62 u32 usb3belt; 63 #define BELT_MULTIPLIER 10 64 #define BEST_EFFORT_LATENCY_TOLERANCE 0 65 u32 usbctl2; 66 #define LTM_ENABLE 7 67 #define U2_ENABLE 6 68 #define U1_ENABLE 5 69 #define FUNCTION_SUSPEND 4 70 #define USB3_CORE_ENABLE 3 71 #define USB2_CORE_ENABLE 2 72 #define SERIAL_NUMBER_STRING_ENABLE 0 73 u32 in_timeout; 74 #define GPEP3_TIMEOUT 19 75 #define GPEP2_TIMEOUT 18 76 #define GPEP1_TIMEOUT 17 77 #define GPEP0_TIMEOUT 16 78 #define GPEP3_TIMEOUT_VALUE 13 79 #define GPEP3_TIMEOUT_ENABLE 12 80 #define GPEP2_TIMEOUT_VALUE 9 81 #define GPEP2_TIMEOUT_ENABLE 8 82 #define GPEP1_TIMEOUT_VALUE 5 83 #define GPEP1_TIMEOUT_ENABLE 4 84 #define GPEP0_TIMEOUT_VALUE 1 85 #define GPEP0_TIMEOUT_ENABLE 0 86 u32 isodelay; 87 #define ISOCHRONOUS_DELAY 0 88 } __packed; 89 90 struct usb338x_fifo_regs { 91 /* offset 0x0500, 0x0520, 0x0540, 0x0560, 0x0580 */ 92 u32 ep_fifo_size_base; 93 #define IN_FIFO_BASE_ADDRESS 22 94 #define IN_FIFO_SIZE 16 95 #define OUT_FIFO_BASE_ADDRESS 6 96 #define OUT_FIFO_SIZE 0 97 u32 ep_fifo_out_wrptr; 98 u32 ep_fifo_out_rdptr; 99 u32 ep_fifo_in_wrptr; 100 u32 ep_fifo_in_rdptr; 101 u32 unused[3]; 102 } __packed; 103 104 105 /* Link layer */ 106 struct usb338x_ll_regs { 107 /* offset 0x700 */ 108 u32 ll_ltssm_ctrl1; 109 u32 ll_ltssm_ctrl2; 110 u32 ll_ltssm_ctrl3; 111 u32 unused[2]; 112 u32 ll_general_ctrl0; 113 u32 ll_general_ctrl1; 114 #define PM_U3_AUTO_EXIT 29 115 #define PM_U2_AUTO_EXIT 28 116 #define PM_U1_AUTO_EXIT 27 117 #define PM_FORCE_U2_ENTRY 26 118 #define PM_FORCE_U1_ENTRY 25 119 #define PM_LGO_COLLISION_SEND_LAU 24 120 #define PM_DIR_LINK_REJECT 23 121 #define PM_FORCE_LINK_ACCEPT 22 122 #define PM_DIR_ENTRY_U3 20 123 #define PM_DIR_ENTRY_U2 19 124 #define PM_DIR_ENTRY_U1 18 125 #define PM_U2_ENABLE 17 126 #define PM_U1_ENABLE 16 127 #define SKP_THRESHOLD_ADJUST_FMW 8 128 #define RESEND_DPP_ON_LRTY_FMW 7 129 #define DL_BIT_VALUE_FMW 6 130 #define FORCE_DL_BIT 5 131 u32 ll_general_ctrl2; 132 #define SELECT_INVERT_LANE_POLARITY 7 133 #define FORCE_INVERT_LANE_POLARITY 6 134 u32 ll_general_ctrl3; 135 u32 ll_general_ctrl4; 136 u32 ll_error_gen; 137 } __packed; 138 139 struct usb338x_ll_lfps_regs { 140 /* offset 0x748 */ 141 u32 ll_lfps_5; 142 #define TIMER_LFPS_6US 16 143 u32 ll_lfps_6; 144 #define TIMER_LFPS_80US 0 145 } __packed; 146 147 struct usb338x_ll_tsn_regs { 148 /* offset 0x77C */ 149 u32 ll_tsn_counters_2; 150 #define HOT_TX_NORESET_TS2 24 151 u32 ll_tsn_counters_3; 152 #define HOT_RX_RESET_TS2 0 153 } __packed; 154 155 struct usb338x_ll_chi_regs { 156 /* offset 0x79C */ 157 u32 ll_tsn_chicken_bit; 158 #define RECOVERY_IDLE_TO_RECOVER_FMW 3 159 } __packed; 160 161 /* protocol layer */ 162 struct usb338x_pl_regs { 163 /* offset 0x800 */ 164 u32 pl_reg_1; 165 u32 pl_reg_2; 166 u32 pl_reg_3; 167 u32 pl_reg_4; 168 u32 pl_ep_ctrl; 169 /* Protocol Layer Endpoint Control*/ 170 #define PL_EP_CTRL 0x810 171 #define ENDPOINT_SELECT 0 172 /* [4:0] */ 173 #define EP_INITIALIZED 16 174 #define SEQUENCE_NUMBER_RESET 17 175 #define CLEAR_ACK_ERROR_CODE 20 176 u32 pl_reg_6; 177 u32 pl_reg_7; 178 u32 pl_reg_8; 179 u32 pl_ep_status_1; 180 /* Protocol Layer Endpoint Status 1*/ 181 #define PL_EP_STATUS_1 0x820 182 #define STATE 16 183 #define ACK_GOOD_NORMAL 0x11 184 #define ACK_GOOD_MORE_ACKS_TO_COME 0x16 185 u32 pl_ep_status_2; 186 u32 pl_ep_status_3; 187 /* Protocol Layer Endpoint Status 3*/ 188 #define PL_EP_STATUS_3 0x828 189 #define SEQUENCE_NUMBER 0 190 u32 pl_ep_status_4; 191 /* Protocol Layer Endpoint Status 4*/ 192 #define PL_EP_STATUS_4 0x82c 193 u32 pl_ep_cfg_4; 194 /* Protocol Layer Endpoint Configuration 4*/ 195 #define PL_EP_CFG_4 0x830 196 #define NON_CTRL_IN_TOLERATE_BAD_DIR 6 197 } __packed; 198 199 #endif /* __LINUX_USB_USB338X_H */ 200