1 /* 2 * V4L2 DV timings header. 3 * 4 * Copyright (C) 2012 Hans Verkuil <hans.verkuil@cisco.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 18 * 02110-1301 USA 19 */ 20 21 #ifndef _V4L2_DV_TIMINGS_H 22 #define _V4L2_DV_TIMINGS_H 23 24 #if __GNUC__ < 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ < 6)) 25 /* Sadly gcc versions older than 4.6 have a bug in how they initialize 26 anonymous unions where they require additional curly brackets. 27 This violates the C1x standard. This workaround adds the curly brackets 28 if needed. */ 29 #define V4L2_INIT_BT_TIMINGS(_width, args...) \ 30 { .bt = { _width , ## args } } 31 #else 32 #define V4L2_INIT_BT_TIMINGS(_width, args...) \ 33 .bt = { _width , ## args } 34 #endif 35 36 /* CEA-861-E timings (i.e. standard HDTV timings) */ 37 38 #define V4L2_DV_BT_CEA_640X480P59_94 { \ 39 .type = V4L2_DV_BT_656_1120, \ 40 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \ 41 25175000, 16, 96, 48, 10, 2, 33, 0, 0, 0, \ 42 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, 0) \ 43 } 44 45 /* Note: these are the nominal timings, for HDMI links this format is typically 46 * double-clocked to meet the minimum pixelclock requirements. */ 47 #define V4L2_DV_BT_CEA_720X480I59_94 { \ 48 .type = V4L2_DV_BT_656_1120, \ 49 V4L2_INIT_BT_TIMINGS(720, 480, 1, 0, \ 50 13500000, 19, 62, 57, 4, 3, 15, 4, 3, 16, \ 51 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \ 52 } 53 54 #define V4L2_DV_BT_CEA_720X480P59_94 { \ 55 .type = V4L2_DV_BT_656_1120, \ 56 V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \ 57 27000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \ 58 V4L2_DV_BT_STD_CEA861, 0) \ 59 } 60 61 /* Note: these are the nominal timings, for HDMI links this format is typically 62 * double-clocked to meet the minimum pixelclock requirements. */ 63 #define V4L2_DV_BT_CEA_720X576I50 { \ 64 .type = V4L2_DV_BT_656_1120, \ 65 V4L2_INIT_BT_TIMINGS(720, 576, 1, 0, \ 66 13500000, 12, 63, 69, 2, 3, 19, 2, 3, 20, \ 67 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \ 68 } 69 70 #define V4L2_DV_BT_CEA_720X576P50 { \ 71 .type = V4L2_DV_BT_656_1120, \ 72 V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \ 73 27000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \ 74 V4L2_DV_BT_STD_CEA861, 0) \ 75 } 76 77 #define V4L2_DV_BT_CEA_1280X720P24 { \ 78 .type = V4L2_DV_BT_656_1120, \ 79 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ 80 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 81 59400000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \ 82 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \ 83 V4L2_DV_FL_CAN_REDUCE_FPS) \ 84 } 85 86 #define V4L2_DV_BT_CEA_1280X720P25 { \ 87 .type = V4L2_DV_BT_656_1120, \ 88 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ 89 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 90 74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, \ 91 V4L2_DV_BT_STD_CEA861, 0) \ 92 } 93 94 #define V4L2_DV_BT_CEA_1280X720P30 { \ 95 .type = V4L2_DV_BT_656_1120, \ 96 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ 97 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 98 74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \ 99 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \ 100 } 101 102 #define V4L2_DV_BT_CEA_1280X720P50 { \ 103 .type = V4L2_DV_BT_656_1120, \ 104 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ 105 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 106 74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \ 107 V4L2_DV_BT_STD_CEA861, 0) \ 108 } 109 110 #define V4L2_DV_BT_CEA_1280X720P60 { \ 111 .type = V4L2_DV_BT_656_1120, \ 112 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ 113 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 114 74250000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \ 115 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \ 116 } 117 118 #define V4L2_DV_BT_CEA_1920X1080P24 { \ 119 .type = V4L2_DV_BT_656_1120, \ 120 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ 121 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 122 74250000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \ 123 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \ 124 } 125 126 #define V4L2_DV_BT_CEA_1920X1080P25 { \ 127 .type = V4L2_DV_BT_656_1120, \ 128 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ 129 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 130 74250000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \ 131 V4L2_DV_BT_STD_CEA861, 0) \ 132 } 133 134 #define V4L2_DV_BT_CEA_1920X1080P30 { \ 135 .type = V4L2_DV_BT_656_1120, \ 136 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ 137 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 138 74250000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \ 139 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \ 140 } 141 142 #define V4L2_DV_BT_CEA_1920X1080I50 { \ 143 .type = V4L2_DV_BT_656_1120, \ 144 V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \ 145 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 146 74250000, 528, 44, 148, 2, 5, 15, 2, 5, 16, \ 147 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \ 148 } 149 150 #define V4L2_DV_BT_CEA_1920X1080P50 { \ 151 .type = V4L2_DV_BT_656_1120, \ 152 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ 153 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 154 148500000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \ 155 V4L2_DV_BT_STD_CEA861, 0) \ 156 } 157 158 #define V4L2_DV_BT_CEA_1920X1080I60 { \ 159 .type = V4L2_DV_BT_656_1120, \ 160 V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \ 161 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 162 74250000, 88, 44, 148, 2, 5, 15, 2, 5, 16, \ 163 V4L2_DV_BT_STD_CEA861, \ 164 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HALF_LINE) \ 165 } 166 167 #define V4L2_DV_BT_CEA_1920X1080P60 { \ 168 .type = V4L2_DV_BT_656_1120, \ 169 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ 170 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 171 148500000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \ 172 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \ 173 V4L2_DV_FL_CAN_REDUCE_FPS) \ 174 } 175 176 #define V4L2_DV_BT_CEA_3840X2160P24 { \ 177 .type = V4L2_DV_BT_656_1120, \ 178 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ 179 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 180 297000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \ 181 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \ 182 } 183 184 #define V4L2_DV_BT_CEA_3840X2160P25 { \ 185 .type = V4L2_DV_BT_656_1120, \ 186 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ 187 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 188 297000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \ 189 V4L2_DV_BT_STD_CEA861, 0) \ 190 } 191 192 #define V4L2_DV_BT_CEA_3840X2160P30 { \ 193 .type = V4L2_DV_BT_656_1120, \ 194 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ 195 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 196 297000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \ 197 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \ 198 } 199 200 #define V4L2_DV_BT_CEA_3840X2160P50 { \ 201 .type = V4L2_DV_BT_656_1120, \ 202 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ 203 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 204 594000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \ 205 V4L2_DV_BT_STD_CEA861, 0) \ 206 } 207 208 #define V4L2_DV_BT_CEA_3840X2160P60 { \ 209 .type = V4L2_DV_BT_656_1120, \ 210 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ 211 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 212 594000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \ 213 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \ 214 } 215 216 #define V4L2_DV_BT_CEA_4096X2160P24 { \ 217 .type = V4L2_DV_BT_656_1120, \ 218 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \ 219 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 220 297000000, 1020, 88, 296, 8, 10, 72, 0, 0, 0, \ 221 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \ 222 } 223 224 #define V4L2_DV_BT_CEA_4096X2160P25 { \ 225 .type = V4L2_DV_BT_656_1120, \ 226 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \ 227 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 228 297000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \ 229 V4L2_DV_BT_STD_CEA861, 0) \ 230 } 231 232 #define V4L2_DV_BT_CEA_4096X2160P30 { \ 233 .type = V4L2_DV_BT_656_1120, \ 234 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \ 235 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 236 297000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \ 237 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \ 238 } 239 240 #define V4L2_DV_BT_CEA_4096X2160P50 { \ 241 .type = V4L2_DV_BT_656_1120, \ 242 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \ 243 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 244 594000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \ 245 V4L2_DV_BT_STD_CEA861, 0) \ 246 } 247 248 #define V4L2_DV_BT_CEA_4096X2160P60 { \ 249 .type = V4L2_DV_BT_656_1120, \ 250 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \ 251 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 252 594000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \ 253 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \ 254 } 255 256 257 /* VESA Discrete Monitor Timings as per version 1.0, revision 12 */ 258 259 #define V4L2_DV_BT_DMT_640X350P85 { \ 260 .type = V4L2_DV_BT_656_1120, \ 261 V4L2_INIT_BT_TIMINGS(640, 350, 0, V4L2_DV_HSYNC_POS_POL, \ 262 31500000, 32, 64, 96, 32, 3, 60, 0, 0, 0, \ 263 V4L2_DV_BT_STD_DMT, 0) \ 264 } 265 266 #define V4L2_DV_BT_DMT_640X400P85 { \ 267 .type = V4L2_DV_BT_656_1120, \ 268 V4L2_INIT_BT_TIMINGS(640, 400, 0, V4L2_DV_VSYNC_POS_POL, \ 269 31500000, 32, 64, 96, 1, 3, 41, 0, 0, 0, \ 270 V4L2_DV_BT_STD_DMT, 0) \ 271 } 272 273 #define V4L2_DV_BT_DMT_720X400P85 { \ 274 .type = V4L2_DV_BT_656_1120, \ 275 V4L2_INIT_BT_TIMINGS(720, 400, 0, V4L2_DV_VSYNC_POS_POL, \ 276 35500000, 36, 72, 108, 1, 3, 42, 0, 0, 0, \ 277 V4L2_DV_BT_STD_DMT, 0) \ 278 } 279 280 /* VGA resolutions */ 281 #define V4L2_DV_BT_DMT_640X480P60 V4L2_DV_BT_CEA_640X480P59_94 282 283 #define V4L2_DV_BT_DMT_640X480P72 { \ 284 .type = V4L2_DV_BT_656_1120, \ 285 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \ 286 31500000, 24, 40, 128, 9, 3, 28, 0, 0, 0, \ 287 V4L2_DV_BT_STD_DMT, 0) \ 288 } 289 290 #define V4L2_DV_BT_DMT_640X480P75 { \ 291 .type = V4L2_DV_BT_656_1120, \ 292 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \ 293 31500000, 16, 64, 120, 1, 3, 16, 0, 0, 0, \ 294 V4L2_DV_BT_STD_DMT, 0) \ 295 } 296 297 #define V4L2_DV_BT_DMT_640X480P85 { \ 298 .type = V4L2_DV_BT_656_1120, \ 299 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \ 300 36000000, 56, 56, 80, 1, 3, 25, 0, 0, 0, \ 301 V4L2_DV_BT_STD_DMT, 0) \ 302 } 303 304 /* SVGA resolutions */ 305 #define V4L2_DV_BT_DMT_800X600P56 { \ 306 .type = V4L2_DV_BT_656_1120, \ 307 V4L2_INIT_BT_TIMINGS(800, 600, 0, \ 308 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 309 36000000, 24, 72, 128, 1, 2, 22, 0, 0, 0, \ 310 V4L2_DV_BT_STD_DMT, 0) \ 311 } 312 313 #define V4L2_DV_BT_DMT_800X600P60 { \ 314 .type = V4L2_DV_BT_656_1120, \ 315 V4L2_INIT_BT_TIMINGS(800, 600, 0, \ 316 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 317 40000000, 40, 128, 88, 1, 4, 23, 0, 0, 0, \ 318 V4L2_DV_BT_STD_DMT, 0) \ 319 } 320 321 #define V4L2_DV_BT_DMT_800X600P72 { \ 322 .type = V4L2_DV_BT_656_1120, \ 323 V4L2_INIT_BT_TIMINGS(800, 600, 0, \ 324 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 325 50000000, 56, 120, 64, 37, 6, 23, 0, 0, 0, \ 326 V4L2_DV_BT_STD_DMT, 0) \ 327 } 328 329 #define V4L2_DV_BT_DMT_800X600P75 { \ 330 .type = V4L2_DV_BT_656_1120, \ 331 V4L2_INIT_BT_TIMINGS(800, 600, 0, \ 332 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 333 49500000, 16, 80, 160, 1, 3, 21, 0, 0, 0, \ 334 V4L2_DV_BT_STD_DMT, 0) \ 335 } 336 337 #define V4L2_DV_BT_DMT_800X600P85 { \ 338 .type = V4L2_DV_BT_656_1120, \ 339 V4L2_INIT_BT_TIMINGS(800, 600, 0, \ 340 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 341 56250000, 32, 64, 152, 1, 3, 27, 0, 0, 0, \ 342 V4L2_DV_BT_STD_DMT, 0) \ 343 } 344 345 #define V4L2_DV_BT_DMT_800X600P120_RB { \ 346 .type = V4L2_DV_BT_656_1120, \ 347 V4L2_INIT_BT_TIMINGS(800, 600, 0, V4L2_DV_HSYNC_POS_POL, \ 348 73250000, 48, 32, 80, 3, 4, 29, 0, 0, 0, \ 349 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 350 V4L2_DV_FL_REDUCED_BLANKING) \ 351 } 352 353 #define V4L2_DV_BT_DMT_848X480P60 { \ 354 .type = V4L2_DV_BT_656_1120, \ 355 V4L2_INIT_BT_TIMINGS(848, 480, 0, \ 356 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 357 33750000, 16, 112, 112, 6, 8, 23, 0, 0, 0, \ 358 V4L2_DV_BT_STD_DMT, 0) \ 359 } 360 361 #define V4L2_DV_BT_DMT_1024X768I43 { \ 362 .type = V4L2_DV_BT_656_1120, \ 363 V4L2_INIT_BT_TIMINGS(1024, 768, 1, \ 364 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 365 44900000, 8, 176, 56, 0, 4, 20, 0, 4, 21, \ 366 V4L2_DV_BT_STD_DMT, 0) \ 367 } 368 369 /* XGA resolutions */ 370 #define V4L2_DV_BT_DMT_1024X768P60 { \ 371 .type = V4L2_DV_BT_656_1120, \ 372 V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \ 373 65000000, 24, 136, 160, 3, 6, 29, 0, 0, 0, \ 374 V4L2_DV_BT_STD_DMT, 0) \ 375 } 376 377 #define V4L2_DV_BT_DMT_1024X768P70 { \ 378 .type = V4L2_DV_BT_656_1120, \ 379 V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \ 380 75000000, 24, 136, 144, 3, 6, 29, 0, 0, 0, \ 381 V4L2_DV_BT_STD_DMT, 0) \ 382 } 383 384 #define V4L2_DV_BT_DMT_1024X768P75 { \ 385 .type = V4L2_DV_BT_656_1120, \ 386 V4L2_INIT_BT_TIMINGS(1024, 768, 0, \ 387 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 388 78750000, 16, 96, 176, 1, 3, 28, 0, 0, 0, \ 389 V4L2_DV_BT_STD_DMT, 0) \ 390 } 391 392 #define V4L2_DV_BT_DMT_1024X768P85 { \ 393 .type = V4L2_DV_BT_656_1120, \ 394 V4L2_INIT_BT_TIMINGS(1024, 768, 0, \ 395 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 396 94500000, 48, 96, 208, 1, 3, 36, 0, 0, 0, \ 397 V4L2_DV_BT_STD_DMT, 0) \ 398 } 399 400 #define V4L2_DV_BT_DMT_1024X768P120_RB { \ 401 .type = V4L2_DV_BT_656_1120, \ 402 V4L2_INIT_BT_TIMINGS(1024, 768, 0, V4L2_DV_HSYNC_POS_POL, \ 403 115500000, 48, 32, 80, 3, 4, 38, 0, 0, 0, \ 404 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 405 V4L2_DV_FL_REDUCED_BLANKING) \ 406 } 407 408 /* XGA+ resolution */ 409 #define V4L2_DV_BT_DMT_1152X864P75 { \ 410 .type = V4L2_DV_BT_656_1120, \ 411 V4L2_INIT_BT_TIMINGS(1152, 864, 0, \ 412 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 413 108000000, 64, 128, 256, 1, 3, 32, 0, 0, 0, \ 414 V4L2_DV_BT_STD_DMT, 0) \ 415 } 416 417 #define V4L2_DV_BT_DMT_1280X720P60 V4L2_DV_BT_CEA_1280X720P60 418 419 /* WXGA resolutions */ 420 #define V4L2_DV_BT_DMT_1280X768P60_RB { \ 421 .type = V4L2_DV_BT_656_1120, \ 422 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \ 423 68250000, 48, 32, 80, 3, 7, 12, 0, 0, 0, \ 424 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 425 V4L2_DV_FL_REDUCED_BLANKING) \ 426 } 427 428 #define V4L2_DV_BT_DMT_1280X768P60 { \ 429 .type = V4L2_DV_BT_656_1120, \ 430 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \ 431 79500000, 64, 128, 192, 3, 7, 20, 0, 0, 0, \ 432 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 433 } 434 435 #define V4L2_DV_BT_DMT_1280X768P75 { \ 436 .type = V4L2_DV_BT_656_1120, \ 437 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \ 438 102250000, 80, 128, 208, 3, 7, 27, 0, 0, 0, \ 439 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 440 } 441 442 #define V4L2_DV_BT_DMT_1280X768P85 { \ 443 .type = V4L2_DV_BT_656_1120, \ 444 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \ 445 117500000, 80, 136, 216, 3, 7, 31, 0, 0, 0, \ 446 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 447 } 448 449 #define V4L2_DV_BT_DMT_1280X768P120_RB { \ 450 .type = V4L2_DV_BT_656_1120, \ 451 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \ 452 140250000, 48, 32, 80, 3, 7, 35, 0, 0, 0, \ 453 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 454 V4L2_DV_FL_REDUCED_BLANKING) \ 455 } 456 457 #define V4L2_DV_BT_DMT_1280X800P60_RB { \ 458 .type = V4L2_DV_BT_656_1120, \ 459 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \ 460 71000000, 48, 32, 80, 3, 6, 14, 0, 0, 0, \ 461 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 462 V4L2_DV_FL_REDUCED_BLANKING) \ 463 } 464 465 #define V4L2_DV_BT_DMT_1280X800P60 { \ 466 .type = V4L2_DV_BT_656_1120, \ 467 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \ 468 83500000, 72, 128, 200, 3, 6, 22, 0, 0, 0, \ 469 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 470 } 471 472 #define V4L2_DV_BT_DMT_1280X800P75 { \ 473 .type = V4L2_DV_BT_656_1120, \ 474 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \ 475 106500000, 80, 128, 208, 3, 6, 29, 0, 0, 0, \ 476 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 477 } 478 479 #define V4L2_DV_BT_DMT_1280X800P85 { \ 480 .type = V4L2_DV_BT_656_1120, \ 481 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \ 482 122500000, 80, 136, 216, 3, 6, 34, 0, 0, 0, \ 483 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 484 } 485 486 #define V4L2_DV_BT_DMT_1280X800P120_RB { \ 487 .type = V4L2_DV_BT_656_1120, \ 488 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \ 489 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, \ 490 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 491 V4L2_DV_FL_REDUCED_BLANKING) \ 492 } 493 494 #define V4L2_DV_BT_DMT_1280X960P60 { \ 495 .type = V4L2_DV_BT_656_1120, \ 496 V4L2_INIT_BT_TIMINGS(1280, 960, 0, \ 497 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 498 108000000, 96, 112, 312, 1, 3, 36, 0, 0, 0, \ 499 V4L2_DV_BT_STD_DMT, 0) \ 500 } 501 502 #define V4L2_DV_BT_DMT_1280X960P85 { \ 503 .type = V4L2_DV_BT_656_1120, \ 504 V4L2_INIT_BT_TIMINGS(1280, 960, 0, \ 505 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 506 148500000, 64, 160, 224, 1, 3, 47, 0, 0, 0, \ 507 V4L2_DV_BT_STD_DMT, 0) \ 508 } 509 510 #define V4L2_DV_BT_DMT_1280X960P120_RB { \ 511 .type = V4L2_DV_BT_656_1120, \ 512 V4L2_INIT_BT_TIMINGS(1280, 960, 0, V4L2_DV_HSYNC_POS_POL, \ 513 175500000, 48, 32, 80, 3, 4, 50, 0, 0, 0, \ 514 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 515 V4L2_DV_FL_REDUCED_BLANKING) \ 516 } 517 518 /* SXGA resolutions */ 519 #define V4L2_DV_BT_DMT_1280X1024P60 { \ 520 .type = V4L2_DV_BT_656_1120, \ 521 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \ 522 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 523 108000000, 48, 112, 248, 1, 3, 38, 0, 0, 0, \ 524 V4L2_DV_BT_STD_DMT, 0) \ 525 } 526 527 #define V4L2_DV_BT_DMT_1280X1024P75 { \ 528 .type = V4L2_DV_BT_656_1120, \ 529 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \ 530 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 531 135000000, 16, 144, 248, 1, 3, 38, 0, 0, 0, \ 532 V4L2_DV_BT_STD_DMT, 0) \ 533 } 534 535 #define V4L2_DV_BT_DMT_1280X1024P85 { \ 536 .type = V4L2_DV_BT_656_1120, \ 537 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \ 538 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 539 157500000, 64, 160, 224, 1, 3, 44, 0, 0, 0, \ 540 V4L2_DV_BT_STD_DMT, 0) \ 541 } 542 543 #define V4L2_DV_BT_DMT_1280X1024P120_RB { \ 544 .type = V4L2_DV_BT_656_1120, \ 545 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, V4L2_DV_HSYNC_POS_POL, \ 546 187250000, 48, 32, 80, 3, 7, 50, 0, 0, 0, \ 547 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 548 V4L2_DV_FL_REDUCED_BLANKING) \ 549 } 550 551 #define V4L2_DV_BT_DMT_1360X768P60 { \ 552 .type = V4L2_DV_BT_656_1120, \ 553 V4L2_INIT_BT_TIMINGS(1360, 768, 0, \ 554 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 555 85500000, 64, 112, 256, 3, 6, 18, 0, 0, 0, \ 556 V4L2_DV_BT_STD_DMT, 0) \ 557 } 558 559 #define V4L2_DV_BT_DMT_1360X768P120_RB { \ 560 .type = V4L2_DV_BT_656_1120, \ 561 V4L2_INIT_BT_TIMINGS(1360, 768, 0, V4L2_DV_HSYNC_POS_POL, \ 562 148250000, 48, 32, 80, 3, 5, 37, 0, 0, 0, \ 563 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 564 V4L2_DV_FL_REDUCED_BLANKING) \ 565 } 566 567 #define V4L2_DV_BT_DMT_1366X768P60 { \ 568 .type = V4L2_DV_BT_656_1120, \ 569 V4L2_INIT_BT_TIMINGS(1366, 768, 0, \ 570 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 571 85500000, 70, 143, 213, 3, 3, 24, 0, 0, 0, \ 572 V4L2_DV_BT_STD_DMT, 0) \ 573 } 574 575 #define V4L2_DV_BT_DMT_1366X768P60_RB { \ 576 .type = V4L2_DV_BT_656_1120, \ 577 V4L2_INIT_BT_TIMINGS(1366, 768, 0, \ 578 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 579 72000000, 14, 56, 64, 1, 3, 28, 0, 0, 0, \ 580 V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \ 581 } 582 583 /* SXGA+ resolutions */ 584 #define V4L2_DV_BT_DMT_1400X1050P60_RB { \ 585 .type = V4L2_DV_BT_656_1120, \ 586 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \ 587 101000000, 48, 32, 80, 3, 4, 23, 0, 0, 0, \ 588 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 589 V4L2_DV_FL_REDUCED_BLANKING) \ 590 } 591 592 #define V4L2_DV_BT_DMT_1400X1050P60 { \ 593 .type = V4L2_DV_BT_656_1120, \ 594 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 595 121750000, 88, 144, 232, 3, 4, 32, 0, 0, 0, \ 596 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 597 } 598 599 #define V4L2_DV_BT_DMT_1400X1050P75 { \ 600 .type = V4L2_DV_BT_656_1120, \ 601 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 602 156000000, 104, 144, 248, 3, 4, 42, 0, 0, 0, \ 603 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 604 } 605 606 #define V4L2_DV_BT_DMT_1400X1050P85 { \ 607 .type = V4L2_DV_BT_656_1120, \ 608 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 609 179500000, 104, 152, 256, 3, 4, 48, 0, 0, 0, \ 610 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 611 } 612 613 #define V4L2_DV_BT_DMT_1400X1050P120_RB { \ 614 .type = V4L2_DV_BT_656_1120, \ 615 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \ 616 208000000, 48, 32, 80, 3, 4, 55, 0, 0, 0, \ 617 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 618 V4L2_DV_FL_REDUCED_BLANKING) \ 619 } 620 621 /* WXGA+ resolutions */ 622 #define V4L2_DV_BT_DMT_1440X900P60_RB { \ 623 .type = V4L2_DV_BT_656_1120, \ 624 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \ 625 88750000, 48, 32, 80, 3, 6, 17, 0, 0, 0, \ 626 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 627 V4L2_DV_FL_REDUCED_BLANKING) \ 628 } 629 630 #define V4L2_DV_BT_DMT_1440X900P60 { \ 631 .type = V4L2_DV_BT_656_1120, \ 632 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \ 633 106500000, 80, 152, 232, 3, 6, 25, 0, 0, 0, \ 634 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 635 } 636 637 #define V4L2_DV_BT_DMT_1440X900P75 { \ 638 .type = V4L2_DV_BT_656_1120, \ 639 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \ 640 136750000, 96, 152, 248, 3, 6, 33, 0, 0, 0, \ 641 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 642 } 643 644 #define V4L2_DV_BT_DMT_1440X900P85 { \ 645 .type = V4L2_DV_BT_656_1120, \ 646 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \ 647 157000000, 104, 152, 256, 3, 6, 39, 0, 0, 0, \ 648 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 649 } 650 651 #define V4L2_DV_BT_DMT_1440X900P120_RB { \ 652 .type = V4L2_DV_BT_656_1120, \ 653 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \ 654 182750000, 48, 32, 80, 3, 6, 44, 0, 0, 0, \ 655 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 656 V4L2_DV_FL_REDUCED_BLANKING) \ 657 } 658 659 #define V4L2_DV_BT_DMT_1600X900P60_RB { \ 660 .type = V4L2_DV_BT_656_1120, \ 661 V4L2_INIT_BT_TIMINGS(1600, 900, 0, \ 662 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 663 108000000, 24, 80, 96, 1, 3, 96, 0, 0, 0, \ 664 V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \ 665 } 666 667 /* UXGA resolutions */ 668 #define V4L2_DV_BT_DMT_1600X1200P60 { \ 669 .type = V4L2_DV_BT_656_1120, \ 670 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ 671 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 672 162000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ 673 V4L2_DV_BT_STD_DMT, 0) \ 674 } 675 676 #define V4L2_DV_BT_DMT_1600X1200P65 { \ 677 .type = V4L2_DV_BT_656_1120, \ 678 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ 679 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 680 175500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ 681 V4L2_DV_BT_STD_DMT, 0) \ 682 } 683 684 #define V4L2_DV_BT_DMT_1600X1200P70 { \ 685 .type = V4L2_DV_BT_656_1120, \ 686 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ 687 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 688 189000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ 689 V4L2_DV_BT_STD_DMT, 0) \ 690 } 691 692 #define V4L2_DV_BT_DMT_1600X1200P75 { \ 693 .type = V4L2_DV_BT_656_1120, \ 694 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ 695 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 696 202500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ 697 V4L2_DV_BT_STD_DMT, 0) \ 698 } 699 700 #define V4L2_DV_BT_DMT_1600X1200P85 { \ 701 .type = V4L2_DV_BT_656_1120, \ 702 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ 703 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 704 229500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ 705 V4L2_DV_BT_STD_DMT, 0) \ 706 } 707 708 #define V4L2_DV_BT_DMT_1600X1200P120_RB { \ 709 .type = V4L2_DV_BT_656_1120, \ 710 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, V4L2_DV_HSYNC_POS_POL, \ 711 268250000, 48, 32, 80, 3, 4, 64, 0, 0, 0, \ 712 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 713 V4L2_DV_FL_REDUCED_BLANKING) \ 714 } 715 716 /* WSXGA+ resolutions */ 717 #define V4L2_DV_BT_DMT_1680X1050P60_RB { \ 718 .type = V4L2_DV_BT_656_1120, \ 719 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \ 720 119000000, 48, 32, 80, 3, 6, 21, 0, 0, 0, \ 721 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 722 V4L2_DV_FL_REDUCED_BLANKING) \ 723 } 724 725 #define V4L2_DV_BT_DMT_1680X1050P60 { \ 726 .type = V4L2_DV_BT_656_1120, \ 727 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 728 146250000, 104, 176, 280, 3, 6, 30, 0, 0, 0, \ 729 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 730 } 731 732 #define V4L2_DV_BT_DMT_1680X1050P75 { \ 733 .type = V4L2_DV_BT_656_1120, \ 734 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 735 187000000, 120, 176, 296, 3, 6, 40, 0, 0, 0, \ 736 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 737 } 738 739 #define V4L2_DV_BT_DMT_1680X1050P85 { \ 740 .type = V4L2_DV_BT_656_1120, \ 741 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 742 214750000, 128, 176, 304, 3, 6, 46, 0, 0, 0, \ 743 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 744 } 745 746 #define V4L2_DV_BT_DMT_1680X1050P120_RB { \ 747 .type = V4L2_DV_BT_656_1120, \ 748 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \ 749 245500000, 48, 32, 80, 3, 6, 53, 0, 0, 0, \ 750 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 751 V4L2_DV_FL_REDUCED_BLANKING) \ 752 } 753 754 #define V4L2_DV_BT_DMT_1792X1344P60 { \ 755 .type = V4L2_DV_BT_656_1120, \ 756 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \ 757 204750000, 128, 200, 328, 1, 3, 46, 0, 0, 0, \ 758 V4L2_DV_BT_STD_DMT, 0) \ 759 } 760 761 #define V4L2_DV_BT_DMT_1792X1344P75 { \ 762 .type = V4L2_DV_BT_656_1120, \ 763 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \ 764 261000000, 96, 216, 352, 1, 3, 69, 0, 0, 0, \ 765 V4L2_DV_BT_STD_DMT, 0) \ 766 } 767 768 #define V4L2_DV_BT_DMT_1792X1344P120_RB { \ 769 .type = V4L2_DV_BT_656_1120, \ 770 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_HSYNC_POS_POL, \ 771 333250000, 48, 32, 80, 3, 4, 72, 0, 0, 0, \ 772 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 773 V4L2_DV_FL_REDUCED_BLANKING) \ 774 } 775 776 #define V4L2_DV_BT_DMT_1856X1392P60 { \ 777 .type = V4L2_DV_BT_656_1120, \ 778 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \ 779 218250000, 96, 224, 352, 1, 3, 43, 0, 0, 0, \ 780 V4L2_DV_BT_STD_DMT, 0) \ 781 } 782 783 #define V4L2_DV_BT_DMT_1856X1392P75 { \ 784 .type = V4L2_DV_BT_656_1120, \ 785 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \ 786 288000000, 128, 224, 352, 1, 3, 104, 0, 0, 0, \ 787 V4L2_DV_BT_STD_DMT, 0) \ 788 } 789 790 #define V4L2_DV_BT_DMT_1856X1392P120_RB { \ 791 .type = V4L2_DV_BT_656_1120, \ 792 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_HSYNC_POS_POL, \ 793 356500000, 48, 32, 80, 3, 4, 75, 0, 0, 0, \ 794 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 795 V4L2_DV_FL_REDUCED_BLANKING) \ 796 } 797 798 #define V4L2_DV_BT_DMT_1920X1080P60 V4L2_DV_BT_CEA_1920X1080P60 799 800 /* WUXGA resolutions */ 801 #define V4L2_DV_BT_DMT_1920X1200P60_RB { \ 802 .type = V4L2_DV_BT_656_1120, \ 803 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \ 804 154000000, 48, 32, 80, 3, 6, 26, 0, 0, 0, \ 805 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 806 V4L2_DV_FL_REDUCED_BLANKING) \ 807 } 808 809 #define V4L2_DV_BT_DMT_1920X1200P60 { \ 810 .type = V4L2_DV_BT_656_1120, \ 811 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \ 812 193250000, 136, 200, 336, 3, 6, 36, 0, 0, 0, \ 813 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 814 } 815 816 #define V4L2_DV_BT_DMT_1920X1200P75 { \ 817 .type = V4L2_DV_BT_656_1120, \ 818 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \ 819 245250000, 136, 208, 344, 3, 6, 46, 0, 0, 0, \ 820 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 821 } 822 823 #define V4L2_DV_BT_DMT_1920X1200P85 { \ 824 .type = V4L2_DV_BT_656_1120, \ 825 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \ 826 281250000, 144, 208, 352, 3, 6, 53, 0, 0, 0, \ 827 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 828 } 829 830 #define V4L2_DV_BT_DMT_1920X1200P120_RB { \ 831 .type = V4L2_DV_BT_656_1120, \ 832 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \ 833 317000000, 48, 32, 80, 3, 6, 62, 0, 0, 0, \ 834 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 835 V4L2_DV_FL_REDUCED_BLANKING) \ 836 } 837 838 #define V4L2_DV_BT_DMT_1920X1440P60 { \ 839 .type = V4L2_DV_BT_656_1120, \ 840 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \ 841 234000000, 128, 208, 344, 1, 3, 56, 0, 0, 0, \ 842 V4L2_DV_BT_STD_DMT, 0) \ 843 } 844 845 #define V4L2_DV_BT_DMT_1920X1440P75 { \ 846 .type = V4L2_DV_BT_656_1120, \ 847 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \ 848 297000000, 144, 224, 352, 1, 3, 56, 0, 0, 0, \ 849 V4L2_DV_BT_STD_DMT, 0) \ 850 } 851 852 #define V4L2_DV_BT_DMT_1920X1440P120_RB { \ 853 .type = V4L2_DV_BT_656_1120, \ 854 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_HSYNC_POS_POL, \ 855 380500000, 48, 32, 80, 3, 4, 78, 0, 0, 0, \ 856 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 857 V4L2_DV_FL_REDUCED_BLANKING) \ 858 } 859 860 #define V4L2_DV_BT_DMT_2048X1152P60_RB { \ 861 .type = V4L2_DV_BT_656_1120, \ 862 V4L2_INIT_BT_TIMINGS(2048, 1152, 0, \ 863 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 864 162000000, 26, 80, 96, 1, 3, 44, 0, 0, 0, \ 865 V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \ 866 } 867 868 /* WQXGA resolutions */ 869 #define V4L2_DV_BT_DMT_2560X1600P60_RB { \ 870 .type = V4L2_DV_BT_656_1120, \ 871 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \ 872 268500000, 48, 32, 80, 3, 6, 37, 0, 0, 0, \ 873 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 874 V4L2_DV_FL_REDUCED_BLANKING) \ 875 } 876 877 #define V4L2_DV_BT_DMT_2560X1600P60 { \ 878 .type = V4L2_DV_BT_656_1120, \ 879 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \ 880 348500000, 192, 280, 472, 3, 6, 49, 0, 0, 0, \ 881 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 882 } 883 884 #define V4L2_DV_BT_DMT_2560X1600P75 { \ 885 .type = V4L2_DV_BT_656_1120, \ 886 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \ 887 443250000, 208, 280, 488, 3, 6, 63, 0, 0, 0, \ 888 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 889 } 890 891 #define V4L2_DV_BT_DMT_2560X1600P85 { \ 892 .type = V4L2_DV_BT_656_1120, \ 893 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \ 894 505250000, 208, 280, 488, 3, 6, 73, 0, 0, 0, \ 895 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 896 } 897 898 #define V4L2_DV_BT_DMT_2560X1600P120_RB { \ 899 .type = V4L2_DV_BT_656_1120, \ 900 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \ 901 552750000, 48, 32, 80, 3, 6, 85, 0, 0, 0, \ 902 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 903 V4L2_DV_FL_REDUCED_BLANKING) \ 904 } 905 906 /* 4K resolutions */ 907 #define V4L2_DV_BT_DMT_4096X2160P60_RB { \ 908 .type = V4L2_DV_BT_656_1120, \ 909 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ 910 556744000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \ 911 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 912 V4L2_DV_FL_REDUCED_BLANKING) \ 913 } 914 915 #define V4L2_DV_BT_DMT_4096X2160P59_94_RB { \ 916 .type = V4L2_DV_BT_656_1120, \ 917 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ 918 556188000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \ 919 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 920 V4L2_DV_FL_REDUCED_BLANKING) \ 921 } 922 923 #endif 924