1 /*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
10 *
11 * Authors:
12 * Wu Fengguang <wfg@linux.intel.com>
13 *
14 * Maintained by:
15 * Wu Fengguang <wfg@linux.intel.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 * for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/slab.h>
35 #include <linux/module.h>
36 #include <sound/core.h>
37 #include <sound/jack.h>
38 #include <sound/asoundef.h>
39 #include <sound/tlv.h>
40 #include "hda_codec.h"
41 #include "hda_local.h"
42 #include "hda_jack.h"
43
44 static bool static_hdmi_pcm;
45 module_param(static_hdmi_pcm, bool, 0644);
46 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
47
48 #define is_haswell(codec) ((codec)->vendor_id == 0x80862807)
49 #define is_broadwell(codec) ((codec)->vendor_id == 0x80862808)
50 #define is_skylake(codec) ((codec)->vendor_id == 0x80862809)
51 #define is_broxton(codec) ((codec)->vendor_id == 0x8086280a)
52 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
53 || is_skylake(codec) || is_broxton(codec))
54
55 #define is_valleyview(codec) ((codec)->vendor_id == 0x80862882)
56 #define is_cherryview(codec) ((codec)->vendor_id == 0x80862883)
57 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
58
59 struct hdmi_spec_per_cvt {
60 hda_nid_t cvt_nid;
61 int assigned;
62 unsigned int channels_min;
63 unsigned int channels_max;
64 u32 rates;
65 u64 formats;
66 unsigned int maxbps;
67 };
68
69 /* max. connections to a widget */
70 #define HDA_MAX_CONNECTIONS 32
71
72 struct hdmi_spec_per_pin {
73 hda_nid_t pin_nid;
74 int num_mux_nids;
75 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
76 int mux_idx;
77 hda_nid_t cvt_nid;
78
79 struct hda_codec *codec;
80 struct hdmi_eld sink_eld;
81 struct mutex lock;
82 struct delayed_work work;
83 struct snd_kcontrol *eld_ctl;
84 int repoll_count;
85 bool setup; /* the stream has been set up by prepare callback */
86 int channels; /* current number of channels */
87 bool non_pcm;
88 bool chmap_set; /* channel-map override by ALSA API? */
89 unsigned char chmap[8]; /* ALSA API channel-map */
90 char pcm_name[8]; /* filled in build_pcm callbacks */
91 #ifdef CONFIG_PROC_FS
92 struct snd_info_entry *proc_entry;
93 #endif
94 };
95
96 struct cea_channel_speaker_allocation;
97
98 /* operations used by generic code that can be overridden by patches */
99 struct hdmi_ops {
100 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
101 unsigned char *buf, int *eld_size);
102
103 /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
104 int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
105 int asp_slot);
106 int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
107 int asp_slot, int channel);
108
109 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
110 int ca, int active_channels, int conn_type);
111
112 /* enable/disable HBR (HD passthrough) */
113 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
114
115 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
116 hda_nid_t pin_nid, u32 stream_tag, int format);
117
118 /* Helpers for producing the channel map TLVs. These can be overridden
119 * for devices that have non-standard mapping requirements. */
120 int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap,
121 int channels);
122 void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap,
123 unsigned int *chmap, int channels);
124
125 /* check that the user-given chmap is supported */
126 int (*chmap_validate)(int ca, int channels, unsigned char *chmap);
127 };
128
129 struct hdmi_spec {
130 int num_cvts;
131 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
132 hda_nid_t cvt_nids[4]; /* only for haswell fix */
133
134 int num_pins;
135 struct snd_array pins; /* struct hdmi_spec_per_pin */
136 struct snd_array pcm_rec; /* struct hda_pcm */
137 unsigned int channels_max; /* max over all cvts */
138
139 struct hdmi_eld temp_eld;
140 struct hdmi_ops ops;
141
142 bool dyn_pin_out;
143
144 /*
145 * Non-generic VIA/NVIDIA specific
146 */
147 struct hda_multi_out multiout;
148 struct hda_pcm_stream pcm_playback;
149 };
150
151
152 struct hdmi_audio_infoframe {
153 u8 type; /* 0x84 */
154 u8 ver; /* 0x01 */
155 u8 len; /* 0x0a */
156
157 u8 checksum;
158
159 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
160 u8 SS01_SF24;
161 u8 CXT04;
162 u8 CA;
163 u8 LFEPBL01_LSV36_DM_INH7;
164 };
165
166 struct dp_audio_infoframe {
167 u8 type; /* 0x84 */
168 u8 len; /* 0x1b */
169 u8 ver; /* 0x11 << 2 */
170
171 u8 CC02_CT47; /* match with HDMI infoframe from this on */
172 u8 SS01_SF24;
173 u8 CXT04;
174 u8 CA;
175 u8 LFEPBL01_LSV36_DM_INH7;
176 };
177
178 union audio_infoframe {
179 struct hdmi_audio_infoframe hdmi;
180 struct dp_audio_infoframe dp;
181 u8 bytes[0];
182 };
183
184 /*
185 * CEA speaker placement:
186 *
187 * FLH FCH FRH
188 * FLW FL FLC FC FRC FR FRW
189 *
190 * LFE
191 * TC
192 *
193 * RL RLC RC RRC RR
194 *
195 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
196 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
197 */
198 enum cea_speaker_placement {
199 FL = (1 << 0), /* Front Left */
200 FC = (1 << 1), /* Front Center */
201 FR = (1 << 2), /* Front Right */
202 FLC = (1 << 3), /* Front Left Center */
203 FRC = (1 << 4), /* Front Right Center */
204 RL = (1 << 5), /* Rear Left */
205 RC = (1 << 6), /* Rear Center */
206 RR = (1 << 7), /* Rear Right */
207 RLC = (1 << 8), /* Rear Left Center */
208 RRC = (1 << 9), /* Rear Right Center */
209 LFE = (1 << 10), /* Low Frequency Effect */
210 FLW = (1 << 11), /* Front Left Wide */
211 FRW = (1 << 12), /* Front Right Wide */
212 FLH = (1 << 13), /* Front Left High */
213 FCH = (1 << 14), /* Front Center High */
214 FRH = (1 << 15), /* Front Right High */
215 TC = (1 << 16), /* Top Center */
216 };
217
218 /*
219 * ELD SA bits in the CEA Speaker Allocation data block
220 */
221 static int eld_speaker_allocation_bits[] = {
222 [0] = FL | FR,
223 [1] = LFE,
224 [2] = FC,
225 [3] = RL | RR,
226 [4] = RC,
227 [5] = FLC | FRC,
228 [6] = RLC | RRC,
229 /* the following are not defined in ELD yet */
230 [7] = FLW | FRW,
231 [8] = FLH | FRH,
232 [9] = TC,
233 [10] = FCH,
234 };
235
236 struct cea_channel_speaker_allocation {
237 int ca_index;
238 int speakers[8];
239
240 /* derived values, just for convenience */
241 int channels;
242 int spk_mask;
243 };
244
245 /*
246 * ALSA sequence is:
247 *
248 * surround40 surround41 surround50 surround51 surround71
249 * ch0 front left = = = =
250 * ch1 front right = = = =
251 * ch2 rear left = = = =
252 * ch3 rear right = = = =
253 * ch4 LFE center center center
254 * ch5 LFE LFE
255 * ch6 side left
256 * ch7 side right
257 *
258 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
259 */
260 static int hdmi_channel_mapping[0x32][8] = {
261 /* stereo */
262 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
263 /* 2.1 */
264 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
265 /* Dolby Surround */
266 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
267 /* surround40 */
268 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
269 /* 4ch */
270 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
271 /* surround41 */
272 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
273 /* surround50 */
274 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
275 /* surround51 */
276 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
277 /* 7.1 */
278 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
279 };
280
281 /*
282 * This is an ordered list!
283 *
284 * The preceding ones have better chances to be selected by
285 * hdmi_channel_allocation().
286 */
287 static struct cea_channel_speaker_allocation channel_allocations[] = {
288 /* channel: 7 6 5 4 3 2 1 0 */
289 { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
290 /* 2.1 */
291 { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
292 /* Dolby Surround */
293 { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
294 /* surround40 */
295 { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
296 /* surround41 */
297 { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
298 /* surround50 */
299 { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
300 /* surround51 */
301 { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
302 /* 6.1 */
303 { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
304 /* surround71 */
305 { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
306
307 { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
308 { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
309 { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
310 { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
311 { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
312 { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
313 { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
314 { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
315 { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
316 { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
317 { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
318 { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
319 { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
320 { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
321 { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
322 { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
323 { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
324 { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
325 { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
326 { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
327 { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
328 { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
329 { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
330 { .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
331 { .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
332 { .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
333 { .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
334 { .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
335 { .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
336 { .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
337 { .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
338 { .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
339 { .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
340 { .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
341 { .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
342 { .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
343 { .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
344 { .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
345 { .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
346 { .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
347 { .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
348 };
349
350
351 /*
352 * HDMI routines
353 */
354
355 #define get_pin(spec, idx) \
356 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
357 #define get_cvt(spec, idx) \
358 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
359 #define get_pcm_rec(spec, idx) \
360 ((struct hda_pcm *)snd_array_elem(&spec->pcm_rec, idx))
361
pin_nid_to_pin_index(struct hda_codec * codec,hda_nid_t pin_nid)362 static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
363 {
364 struct hdmi_spec *spec = codec->spec;
365 int pin_idx;
366
367 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
368 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
369 return pin_idx;
370
371 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
372 return -EINVAL;
373 }
374
hinfo_to_pin_index(struct hda_codec * codec,struct hda_pcm_stream * hinfo)375 static int hinfo_to_pin_index(struct hda_codec *codec,
376 struct hda_pcm_stream *hinfo)
377 {
378 struct hdmi_spec *spec = codec->spec;
379 int pin_idx;
380
381 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
382 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
383 return pin_idx;
384
385 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
386 return -EINVAL;
387 }
388
cvt_nid_to_cvt_index(struct hda_codec * codec,hda_nid_t cvt_nid)389 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
390 {
391 struct hdmi_spec *spec = codec->spec;
392 int cvt_idx;
393
394 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
395 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
396 return cvt_idx;
397
398 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
399 return -EINVAL;
400 }
401
hdmi_eld_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)402 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
403 struct snd_ctl_elem_info *uinfo)
404 {
405 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
406 struct hdmi_spec *spec = codec->spec;
407 struct hdmi_spec_per_pin *per_pin;
408 struct hdmi_eld *eld;
409 int pin_idx;
410
411 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
412
413 pin_idx = kcontrol->private_value;
414 per_pin = get_pin(spec, pin_idx);
415 eld = &per_pin->sink_eld;
416
417 mutex_lock(&per_pin->lock);
418 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
419 mutex_unlock(&per_pin->lock);
420
421 return 0;
422 }
423
hdmi_eld_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)424 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
425 struct snd_ctl_elem_value *ucontrol)
426 {
427 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
428 struct hdmi_spec *spec = codec->spec;
429 struct hdmi_spec_per_pin *per_pin;
430 struct hdmi_eld *eld;
431 int pin_idx;
432
433 pin_idx = kcontrol->private_value;
434 per_pin = get_pin(spec, pin_idx);
435 eld = &per_pin->sink_eld;
436
437 mutex_lock(&per_pin->lock);
438 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
439 eld->eld_size > ELD_MAX_SIZE) {
440 mutex_unlock(&per_pin->lock);
441 snd_BUG();
442 return -EINVAL;
443 }
444
445 memset(ucontrol->value.bytes.data, 0,
446 ARRAY_SIZE(ucontrol->value.bytes.data));
447 if (eld->eld_valid)
448 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
449 eld->eld_size);
450 mutex_unlock(&per_pin->lock);
451
452 return 0;
453 }
454
455 static struct snd_kcontrol_new eld_bytes_ctl = {
456 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
457 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
458 .name = "ELD",
459 .info = hdmi_eld_ctl_info,
460 .get = hdmi_eld_ctl_get,
461 };
462
hdmi_create_eld_ctl(struct hda_codec * codec,int pin_idx,int device)463 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
464 int device)
465 {
466 struct snd_kcontrol *kctl;
467 struct hdmi_spec *spec = codec->spec;
468 int err;
469
470 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
471 if (!kctl)
472 return -ENOMEM;
473 kctl->private_value = pin_idx;
474 kctl->id.device = device;
475
476 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
477 if (err < 0)
478 return err;
479
480 get_pin(spec, pin_idx)->eld_ctl = kctl;
481 return 0;
482 }
483
484 #ifdef BE_PARANOID
hdmi_get_dip_index(struct hda_codec * codec,hda_nid_t pin_nid,int * packet_index,int * byte_index)485 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
486 int *packet_index, int *byte_index)
487 {
488 int val;
489
490 val = snd_hda_codec_read(codec, pin_nid, 0,
491 AC_VERB_GET_HDMI_DIP_INDEX, 0);
492
493 *packet_index = val >> 5;
494 *byte_index = val & 0x1f;
495 }
496 #endif
497
hdmi_set_dip_index(struct hda_codec * codec,hda_nid_t pin_nid,int packet_index,int byte_index)498 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
499 int packet_index, int byte_index)
500 {
501 int val;
502
503 val = (packet_index << 5) | (byte_index & 0x1f);
504
505 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
506 }
507
hdmi_write_dip_byte(struct hda_codec * codec,hda_nid_t pin_nid,unsigned char val)508 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
509 unsigned char val)
510 {
511 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
512 }
513
hdmi_init_pin(struct hda_codec * codec,hda_nid_t pin_nid)514 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
515 {
516 struct hdmi_spec *spec = codec->spec;
517 int pin_out;
518
519 /* Unmute */
520 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
521 snd_hda_codec_write(codec, pin_nid, 0,
522 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
523
524 if (spec->dyn_pin_out)
525 /* Disable pin out until stream is active */
526 pin_out = 0;
527 else
528 /* Enable pin out: some machines with GM965 gets broken output
529 * when the pin is disabled or changed while using with HDMI
530 */
531 pin_out = PIN_OUT;
532
533 snd_hda_codec_write(codec, pin_nid, 0,
534 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
535 }
536
hdmi_get_channel_count(struct hda_codec * codec,hda_nid_t cvt_nid)537 static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
538 {
539 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
540 AC_VERB_GET_CVT_CHAN_COUNT, 0);
541 }
542
hdmi_set_channel_count(struct hda_codec * codec,hda_nid_t cvt_nid,int chs)543 static void hdmi_set_channel_count(struct hda_codec *codec,
544 hda_nid_t cvt_nid, int chs)
545 {
546 if (chs != hdmi_get_channel_count(codec, cvt_nid))
547 snd_hda_codec_write(codec, cvt_nid, 0,
548 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
549 }
550
551 /*
552 * ELD proc files
553 */
554
555 #ifdef CONFIG_PROC_FS
print_eld_info(struct snd_info_entry * entry,struct snd_info_buffer * buffer)556 static void print_eld_info(struct snd_info_entry *entry,
557 struct snd_info_buffer *buffer)
558 {
559 struct hdmi_spec_per_pin *per_pin = entry->private_data;
560
561 mutex_lock(&per_pin->lock);
562 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
563 mutex_unlock(&per_pin->lock);
564 }
565
write_eld_info(struct snd_info_entry * entry,struct snd_info_buffer * buffer)566 static void write_eld_info(struct snd_info_entry *entry,
567 struct snd_info_buffer *buffer)
568 {
569 struct hdmi_spec_per_pin *per_pin = entry->private_data;
570
571 mutex_lock(&per_pin->lock);
572 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
573 mutex_unlock(&per_pin->lock);
574 }
575
eld_proc_new(struct hdmi_spec_per_pin * per_pin,int index)576 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
577 {
578 char name[32];
579 struct hda_codec *codec = per_pin->codec;
580 struct snd_info_entry *entry;
581 int err;
582
583 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
584 err = snd_card_proc_new(codec->bus->card, name, &entry);
585 if (err < 0)
586 return err;
587
588 snd_info_set_text_ops(entry, per_pin, print_eld_info);
589 entry->c.text.write = write_eld_info;
590 entry->mode |= S_IWUSR;
591 per_pin->proc_entry = entry;
592
593 return 0;
594 }
595
eld_proc_free(struct hdmi_spec_per_pin * per_pin)596 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
597 {
598 if (!per_pin->codec->bus->shutdown && per_pin->proc_entry) {
599 snd_device_free(per_pin->codec->bus->card, per_pin->proc_entry);
600 per_pin->proc_entry = NULL;
601 }
602 }
603 #else
eld_proc_new(struct hdmi_spec_per_pin * per_pin,int index)604 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
605 int index)
606 {
607 return 0;
608 }
eld_proc_free(struct hdmi_spec_per_pin * per_pin)609 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
610 {
611 }
612 #endif
613
614 /*
615 * Channel mapping routines
616 */
617
618 /*
619 * Compute derived values in channel_allocations[].
620 */
init_channel_allocations(void)621 static void init_channel_allocations(void)
622 {
623 int i, j;
624 struct cea_channel_speaker_allocation *p;
625
626 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
627 p = channel_allocations + i;
628 p->channels = 0;
629 p->spk_mask = 0;
630 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
631 if (p->speakers[j]) {
632 p->channels++;
633 p->spk_mask |= p->speakers[j];
634 }
635 }
636 }
637
get_channel_allocation_order(int ca)638 static int get_channel_allocation_order(int ca)
639 {
640 int i;
641
642 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
643 if (channel_allocations[i].ca_index == ca)
644 break;
645 }
646 return i;
647 }
648
649 /*
650 * The transformation takes two steps:
651 *
652 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
653 * spk_mask => (channel_allocations[]) => ai->CA
654 *
655 * TODO: it could select the wrong CA from multiple candidates.
656 */
hdmi_channel_allocation(struct hda_codec * codec,struct hdmi_eld * eld,int channels)657 static int hdmi_channel_allocation(struct hda_codec *codec,
658 struct hdmi_eld *eld, int channels)
659 {
660 int i;
661 int ca = 0;
662 int spk_mask = 0;
663 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
664
665 /*
666 * CA defaults to 0 for basic stereo audio
667 */
668 if (channels <= 2)
669 return 0;
670
671 /*
672 * expand ELD's speaker allocation mask
673 *
674 * ELD tells the speaker mask in a compact(paired) form,
675 * expand ELD's notions to match the ones used by Audio InfoFrame.
676 */
677 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
678 if (eld->info.spk_alloc & (1 << i))
679 spk_mask |= eld_speaker_allocation_bits[i];
680 }
681
682 /* search for the first working match in the CA table */
683 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
684 if (channels == channel_allocations[i].channels &&
685 (spk_mask & channel_allocations[i].spk_mask) ==
686 channel_allocations[i].spk_mask) {
687 ca = channel_allocations[i].ca_index;
688 break;
689 }
690 }
691
692 if (!ca) {
693 /* if there was no match, select the regular ALSA channel
694 * allocation with the matching number of channels */
695 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
696 if (channels == channel_allocations[i].channels) {
697 ca = channel_allocations[i].ca_index;
698 break;
699 }
700 }
701 }
702
703 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
704 codec_dbg(codec, "HDMI: select CA 0x%x for %d-channel allocation: %s\n",
705 ca, channels, buf);
706
707 return ca;
708 }
709
hdmi_debug_channel_mapping(struct hda_codec * codec,hda_nid_t pin_nid)710 static void hdmi_debug_channel_mapping(struct hda_codec *codec,
711 hda_nid_t pin_nid)
712 {
713 #ifdef CONFIG_SND_DEBUG_VERBOSE
714 struct hdmi_spec *spec = codec->spec;
715 int i;
716 int channel;
717
718 for (i = 0; i < 8; i++) {
719 channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i);
720 codec_dbg(codec, "HDMI: ASP channel %d => slot %d\n",
721 channel, i);
722 }
723 #endif
724 }
725
hdmi_std_setup_channel_mapping(struct hda_codec * codec,hda_nid_t pin_nid,bool non_pcm,int ca)726 static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
727 hda_nid_t pin_nid,
728 bool non_pcm,
729 int ca)
730 {
731 struct hdmi_spec *spec = codec->spec;
732 struct cea_channel_speaker_allocation *ch_alloc;
733 int i;
734 int err;
735 int order;
736 int non_pcm_mapping[8];
737
738 order = get_channel_allocation_order(ca);
739 ch_alloc = &channel_allocations[order];
740
741 if (hdmi_channel_mapping[ca][1] == 0) {
742 int hdmi_slot = 0;
743 /* fill actual channel mappings in ALSA channel (i) order */
744 for (i = 0; i < ch_alloc->channels; i++) {
745 while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
746 hdmi_slot++; /* skip zero slots */
747
748 hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
749 }
750 /* fill the rest of the slots with ALSA channel 0xf */
751 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
752 if (!ch_alloc->speakers[7 - hdmi_slot])
753 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
754 }
755
756 if (non_pcm) {
757 for (i = 0; i < ch_alloc->channels; i++)
758 non_pcm_mapping[i] = (i << 4) | i;
759 for (; i < 8; i++)
760 non_pcm_mapping[i] = (0xf << 4) | i;
761 }
762
763 for (i = 0; i < 8; i++) {
764 int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i];
765 int hdmi_slot = slotsetup & 0x0f;
766 int channel = (slotsetup & 0xf0) >> 4;
767 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel);
768 if (err) {
769 codec_dbg(codec, "HDMI: channel mapping failed\n");
770 break;
771 }
772 }
773 }
774
775 struct channel_map_table {
776 unsigned char map; /* ALSA API channel map position */
777 int spk_mask; /* speaker position bit mask */
778 };
779
780 static struct channel_map_table map_tables[] = {
781 { SNDRV_CHMAP_FL, FL },
782 { SNDRV_CHMAP_FR, FR },
783 { SNDRV_CHMAP_RL, RL },
784 { SNDRV_CHMAP_RR, RR },
785 { SNDRV_CHMAP_LFE, LFE },
786 { SNDRV_CHMAP_FC, FC },
787 { SNDRV_CHMAP_RLC, RLC },
788 { SNDRV_CHMAP_RRC, RRC },
789 { SNDRV_CHMAP_RC, RC },
790 { SNDRV_CHMAP_FLC, FLC },
791 { SNDRV_CHMAP_FRC, FRC },
792 { SNDRV_CHMAP_TFL, FLH },
793 { SNDRV_CHMAP_TFR, FRH },
794 { SNDRV_CHMAP_FLW, FLW },
795 { SNDRV_CHMAP_FRW, FRW },
796 { SNDRV_CHMAP_TC, TC },
797 { SNDRV_CHMAP_TFC, FCH },
798 {} /* terminator */
799 };
800
801 /* from ALSA API channel position to speaker bit mask */
to_spk_mask(unsigned char c)802 static int to_spk_mask(unsigned char c)
803 {
804 struct channel_map_table *t = map_tables;
805 for (; t->map; t++) {
806 if (t->map == c)
807 return t->spk_mask;
808 }
809 return 0;
810 }
811
812 /* from ALSA API channel position to CEA slot */
to_cea_slot(int ordered_ca,unsigned char pos)813 static int to_cea_slot(int ordered_ca, unsigned char pos)
814 {
815 int mask = to_spk_mask(pos);
816 int i;
817
818 if (mask) {
819 for (i = 0; i < 8; i++) {
820 if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
821 return i;
822 }
823 }
824
825 return -1;
826 }
827
828 /* from speaker bit mask to ALSA API channel position */
spk_to_chmap(int spk)829 static int spk_to_chmap(int spk)
830 {
831 struct channel_map_table *t = map_tables;
832 for (; t->map; t++) {
833 if (t->spk_mask == spk)
834 return t->map;
835 }
836 return 0;
837 }
838
839 /* from CEA slot to ALSA API channel position */
from_cea_slot(int ordered_ca,unsigned char slot)840 static int from_cea_slot(int ordered_ca, unsigned char slot)
841 {
842 int mask = channel_allocations[ordered_ca].speakers[7 - slot];
843
844 return spk_to_chmap(mask);
845 }
846
847 /* get the CA index corresponding to the given ALSA API channel map */
hdmi_manual_channel_allocation(int chs,unsigned char * map)848 static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
849 {
850 int i, spks = 0, spk_mask = 0;
851
852 for (i = 0; i < chs; i++) {
853 int mask = to_spk_mask(map[i]);
854 if (mask) {
855 spk_mask |= mask;
856 spks++;
857 }
858 }
859
860 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
861 if ((chs == channel_allocations[i].channels ||
862 spks == channel_allocations[i].channels) &&
863 (spk_mask & channel_allocations[i].spk_mask) ==
864 channel_allocations[i].spk_mask)
865 return channel_allocations[i].ca_index;
866 }
867 return -1;
868 }
869
870 /* set up the channel slots for the given ALSA API channel map */
hdmi_manual_setup_channel_mapping(struct hda_codec * codec,hda_nid_t pin_nid,int chs,unsigned char * map,int ca)871 static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
872 hda_nid_t pin_nid,
873 int chs, unsigned char *map,
874 int ca)
875 {
876 struct hdmi_spec *spec = codec->spec;
877 int ordered_ca = get_channel_allocation_order(ca);
878 int alsa_pos, hdmi_slot;
879 int assignments[8] = {[0 ... 7] = 0xf};
880
881 for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
882
883 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
884
885 if (hdmi_slot < 0)
886 continue; /* unassigned channel */
887
888 assignments[hdmi_slot] = alsa_pos;
889 }
890
891 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
892 int err;
893
894 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot,
895 assignments[hdmi_slot]);
896 if (err)
897 return -EINVAL;
898 }
899 return 0;
900 }
901
902 /* store ALSA API channel map from the current default map */
hdmi_setup_fake_chmap(unsigned char * map,int ca)903 static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
904 {
905 int i;
906 int ordered_ca = get_channel_allocation_order(ca);
907 for (i = 0; i < 8; i++) {
908 if (i < channel_allocations[ordered_ca].channels)
909 map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
910 else
911 map[i] = 0;
912 }
913 }
914
hdmi_setup_channel_mapping(struct hda_codec * codec,hda_nid_t pin_nid,bool non_pcm,int ca,int channels,unsigned char * map,bool chmap_set)915 static void hdmi_setup_channel_mapping(struct hda_codec *codec,
916 hda_nid_t pin_nid, bool non_pcm, int ca,
917 int channels, unsigned char *map,
918 bool chmap_set)
919 {
920 if (!non_pcm && chmap_set) {
921 hdmi_manual_setup_channel_mapping(codec, pin_nid,
922 channels, map, ca);
923 } else {
924 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
925 hdmi_setup_fake_chmap(map, ca);
926 }
927
928 hdmi_debug_channel_mapping(codec, pin_nid);
929 }
930
hdmi_pin_set_slot_channel(struct hda_codec * codec,hda_nid_t pin_nid,int asp_slot,int channel)931 static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
932 int asp_slot, int channel)
933 {
934 return snd_hda_codec_write(codec, pin_nid, 0,
935 AC_VERB_SET_HDMI_CHAN_SLOT,
936 (channel << 4) | asp_slot);
937 }
938
hdmi_pin_get_slot_channel(struct hda_codec * codec,hda_nid_t pin_nid,int asp_slot)939 static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
940 int asp_slot)
941 {
942 return (snd_hda_codec_read(codec, pin_nid, 0,
943 AC_VERB_GET_HDMI_CHAN_SLOT,
944 asp_slot) & 0xf0) >> 4;
945 }
946
947 /*
948 * Audio InfoFrame routines
949 */
950
951 /*
952 * Enable Audio InfoFrame Transmission
953 */
hdmi_start_infoframe_trans(struct hda_codec * codec,hda_nid_t pin_nid)954 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
955 hda_nid_t pin_nid)
956 {
957 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
958 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
959 AC_DIPXMIT_BEST);
960 }
961
962 /*
963 * Disable Audio InfoFrame Transmission
964 */
hdmi_stop_infoframe_trans(struct hda_codec * codec,hda_nid_t pin_nid)965 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
966 hda_nid_t pin_nid)
967 {
968 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
969 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
970 AC_DIPXMIT_DISABLE);
971 }
972
hdmi_debug_dip_size(struct hda_codec * codec,hda_nid_t pin_nid)973 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
974 {
975 #ifdef CONFIG_SND_DEBUG_VERBOSE
976 int i;
977 int size;
978
979 size = snd_hdmi_get_eld_size(codec, pin_nid);
980 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
981
982 for (i = 0; i < 8; i++) {
983 size = snd_hda_codec_read(codec, pin_nid, 0,
984 AC_VERB_GET_HDMI_DIP_SIZE, i);
985 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
986 }
987 #endif
988 }
989
hdmi_clear_dip_buffers(struct hda_codec * codec,hda_nid_t pin_nid)990 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
991 {
992 #ifdef BE_PARANOID
993 int i, j;
994 int size;
995 int pi, bi;
996 for (i = 0; i < 8; i++) {
997 size = snd_hda_codec_read(codec, pin_nid, 0,
998 AC_VERB_GET_HDMI_DIP_SIZE, i);
999 if (size == 0)
1000 continue;
1001
1002 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
1003 for (j = 1; j < 1000; j++) {
1004 hdmi_write_dip_byte(codec, pin_nid, 0x0);
1005 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
1006 if (pi != i)
1007 codec_dbg(codec, "dip index %d: %d != %d\n",
1008 bi, pi, i);
1009 if (bi == 0) /* byte index wrapped around */
1010 break;
1011 }
1012 codec_dbg(codec,
1013 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
1014 i, size, j);
1015 }
1016 #endif
1017 }
1018
hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe * hdmi_ai)1019 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
1020 {
1021 u8 *bytes = (u8 *)hdmi_ai;
1022 u8 sum = 0;
1023 int i;
1024
1025 hdmi_ai->checksum = 0;
1026
1027 for (i = 0; i < sizeof(*hdmi_ai); i++)
1028 sum += bytes[i];
1029
1030 hdmi_ai->checksum = -sum;
1031 }
1032
hdmi_fill_audio_infoframe(struct hda_codec * codec,hda_nid_t pin_nid,u8 * dip,int size)1033 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
1034 hda_nid_t pin_nid,
1035 u8 *dip, int size)
1036 {
1037 int i;
1038
1039 hdmi_debug_dip_size(codec, pin_nid);
1040 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
1041
1042 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1043 for (i = 0; i < size; i++)
1044 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
1045 }
1046
hdmi_infoframe_uptodate(struct hda_codec * codec,hda_nid_t pin_nid,u8 * dip,int size)1047 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
1048 u8 *dip, int size)
1049 {
1050 u8 val;
1051 int i;
1052
1053 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
1054 != AC_DIPXMIT_BEST)
1055 return false;
1056
1057 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1058 for (i = 0; i < size; i++) {
1059 val = snd_hda_codec_read(codec, pin_nid, 0,
1060 AC_VERB_GET_HDMI_DIP_DATA, 0);
1061 if (val != dip[i])
1062 return false;
1063 }
1064
1065 return true;
1066 }
1067
hdmi_pin_setup_infoframe(struct hda_codec * codec,hda_nid_t pin_nid,int ca,int active_channels,int conn_type)1068 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
1069 hda_nid_t pin_nid,
1070 int ca, int active_channels,
1071 int conn_type)
1072 {
1073 union audio_infoframe ai;
1074
1075 memset(&ai, 0, sizeof(ai));
1076 if (conn_type == 0) { /* HDMI */
1077 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
1078
1079 hdmi_ai->type = 0x84;
1080 hdmi_ai->ver = 0x01;
1081 hdmi_ai->len = 0x0a;
1082 hdmi_ai->CC02_CT47 = active_channels - 1;
1083 hdmi_ai->CA = ca;
1084 hdmi_checksum_audio_infoframe(hdmi_ai);
1085 } else if (conn_type == 1) { /* DisplayPort */
1086 struct dp_audio_infoframe *dp_ai = &ai.dp;
1087
1088 dp_ai->type = 0x84;
1089 dp_ai->len = 0x1b;
1090 dp_ai->ver = 0x11 << 2;
1091 dp_ai->CC02_CT47 = active_channels - 1;
1092 dp_ai->CA = ca;
1093 } else {
1094 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
1095 pin_nid);
1096 return;
1097 }
1098
1099 /*
1100 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
1101 * sizeof(*dp_ai) to avoid partial match/update problems when
1102 * the user switches between HDMI/DP monitors.
1103 */
1104 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
1105 sizeof(ai))) {
1106 codec_dbg(codec,
1107 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
1108 pin_nid,
1109 active_channels, ca);
1110 hdmi_stop_infoframe_trans(codec, pin_nid);
1111 hdmi_fill_audio_infoframe(codec, pin_nid,
1112 ai.bytes, sizeof(ai));
1113 hdmi_start_infoframe_trans(codec, pin_nid);
1114 }
1115 }
1116
hdmi_setup_audio_infoframe(struct hda_codec * codec,struct hdmi_spec_per_pin * per_pin,bool non_pcm)1117 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
1118 struct hdmi_spec_per_pin *per_pin,
1119 bool non_pcm)
1120 {
1121 struct hdmi_spec *spec = codec->spec;
1122 hda_nid_t pin_nid = per_pin->pin_nid;
1123 int channels = per_pin->channels;
1124 int active_channels;
1125 struct hdmi_eld *eld;
1126 int ca, ordered_ca;
1127
1128 if (!channels)
1129 return;
1130
1131 if (is_haswell_plus(codec))
1132 snd_hda_codec_write(codec, pin_nid, 0,
1133 AC_VERB_SET_AMP_GAIN_MUTE,
1134 AMP_OUT_UNMUTE);
1135
1136 eld = &per_pin->sink_eld;
1137
1138 if (!non_pcm && per_pin->chmap_set)
1139 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
1140 else
1141 ca = hdmi_channel_allocation(codec, eld, channels);
1142 if (ca < 0)
1143 ca = 0;
1144
1145 ordered_ca = get_channel_allocation_order(ca);
1146 active_channels = channel_allocations[ordered_ca].channels;
1147
1148 hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
1149
1150 /*
1151 * always configure channel mapping, it may have been changed by the
1152 * user in the meantime
1153 */
1154 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
1155 channels, per_pin->chmap,
1156 per_pin->chmap_set);
1157
1158 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
1159 eld->info.conn_type);
1160
1161 per_pin->non_pcm = non_pcm;
1162 }
1163
1164 /*
1165 * Unsolicited events
1166 */
1167
1168 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
1169
check_presence_and_report(struct hda_codec * codec,hda_nid_t nid)1170 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid)
1171 {
1172 struct hdmi_spec *spec = codec->spec;
1173 int pin_idx = pin_nid_to_pin_index(codec, nid);
1174
1175 if (pin_idx < 0)
1176 return;
1177 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
1178 snd_hda_jack_report_sync(codec);
1179 }
1180
jack_callback(struct hda_codec * codec,struct hda_jack_callback * jack)1181 static void jack_callback(struct hda_codec *codec,
1182 struct hda_jack_callback *jack)
1183 {
1184 check_presence_and_report(codec, jack->tbl->nid);
1185 }
1186
hdmi_intrinsic_event(struct hda_codec * codec,unsigned int res)1187 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1188 {
1189 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1190 struct hda_jack_tbl *jack;
1191 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
1192
1193 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1194 if (!jack)
1195 return;
1196 jack->jack_dirty = 1;
1197
1198 codec_dbg(codec,
1199 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
1200 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
1201 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
1202
1203 check_presence_and_report(codec, jack->nid);
1204 }
1205
hdmi_non_intrinsic_event(struct hda_codec * codec,unsigned int res)1206 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1207 {
1208 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1209 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1210 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1211 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1212
1213 codec_info(codec,
1214 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
1215 codec->addr,
1216 tag,
1217 subtag,
1218 cp_state,
1219 cp_ready);
1220
1221 /* TODO */
1222 if (cp_state)
1223 ;
1224 if (cp_ready)
1225 ;
1226 }
1227
1228
hdmi_unsol_event(struct hda_codec * codec,unsigned int res)1229 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1230 {
1231 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1232 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1233
1234 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
1235 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
1236 return;
1237 }
1238
1239 if (subtag == 0)
1240 hdmi_intrinsic_event(codec, res);
1241 else
1242 hdmi_non_intrinsic_event(codec, res);
1243 }
1244
haswell_verify_D0(struct hda_codec * codec,hda_nid_t cvt_nid,hda_nid_t nid)1245 static void haswell_verify_D0(struct hda_codec *codec,
1246 hda_nid_t cvt_nid, hda_nid_t nid)
1247 {
1248 int pwr;
1249
1250 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1251 * thus pins could only choose converter 0 for use. Make sure the
1252 * converters are in correct power state */
1253 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
1254 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1255
1256 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
1257 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1258 AC_PWRST_D0);
1259 msleep(40);
1260 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1261 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
1262 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
1263 }
1264 }
1265
1266 /*
1267 * Callbacks
1268 */
1269
1270 /* HBR should be Non-PCM, 8 channels */
1271 #define is_hbr_format(format) \
1272 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1273
hdmi_pin_hbr_setup(struct hda_codec * codec,hda_nid_t pin_nid,bool hbr)1274 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
1275 bool hbr)
1276 {
1277 int pinctl, new_pinctl;
1278
1279 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1280 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1281 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1282
1283 if (pinctl < 0)
1284 return hbr ? -EINVAL : 0;
1285
1286 new_pinctl = pinctl & ~AC_PINCTL_EPT;
1287 if (hbr)
1288 new_pinctl |= AC_PINCTL_EPT_HBR;
1289 else
1290 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1291
1292 codec_dbg(codec,
1293 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
1294 pin_nid,
1295 pinctl == new_pinctl ? "" : "new-",
1296 new_pinctl);
1297
1298 if (pinctl != new_pinctl)
1299 snd_hda_codec_write(codec, pin_nid, 0,
1300 AC_VERB_SET_PIN_WIDGET_CONTROL,
1301 new_pinctl);
1302 } else if (hbr)
1303 return -EINVAL;
1304
1305 return 0;
1306 }
1307
hdmi_setup_stream(struct hda_codec * codec,hda_nid_t cvt_nid,hda_nid_t pin_nid,u32 stream_tag,int format)1308 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1309 hda_nid_t pin_nid, u32 stream_tag, int format)
1310 {
1311 struct hdmi_spec *spec = codec->spec;
1312 int err;
1313
1314 if (is_haswell_plus(codec))
1315 haswell_verify_D0(codec, cvt_nid, pin_nid);
1316
1317 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
1318
1319 if (err) {
1320 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
1321 return err;
1322 }
1323
1324 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
1325 return 0;
1326 }
1327
hdmi_choose_cvt(struct hda_codec * codec,int pin_idx,int * cvt_id,int * mux_id)1328 static int hdmi_choose_cvt(struct hda_codec *codec,
1329 int pin_idx, int *cvt_id, int *mux_id)
1330 {
1331 struct hdmi_spec *spec = codec->spec;
1332 struct hdmi_spec_per_pin *per_pin;
1333 struct hdmi_spec_per_cvt *per_cvt = NULL;
1334 int cvt_idx, mux_idx = 0;
1335
1336 per_pin = get_pin(spec, pin_idx);
1337
1338 /* Dynamically assign converter to stream */
1339 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1340 per_cvt = get_cvt(spec, cvt_idx);
1341
1342 /* Must not already be assigned */
1343 if (per_cvt->assigned)
1344 continue;
1345 /* Must be in pin's mux's list of converters */
1346 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1347 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1348 break;
1349 /* Not in mux list */
1350 if (mux_idx == per_pin->num_mux_nids)
1351 continue;
1352 break;
1353 }
1354
1355 /* No free converters */
1356 if (cvt_idx == spec->num_cvts)
1357 return -ENODEV;
1358
1359 per_pin->mux_idx = mux_idx;
1360
1361 if (cvt_id)
1362 *cvt_id = cvt_idx;
1363 if (mux_id)
1364 *mux_id = mux_idx;
1365
1366 return 0;
1367 }
1368
1369 /* Assure the pin select the right convetor */
intel_verify_pin_cvt_connect(struct hda_codec * codec,struct hdmi_spec_per_pin * per_pin)1370 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1371 struct hdmi_spec_per_pin *per_pin)
1372 {
1373 hda_nid_t pin_nid = per_pin->pin_nid;
1374 int mux_idx, curr;
1375
1376 mux_idx = per_pin->mux_idx;
1377 curr = snd_hda_codec_read(codec, pin_nid, 0,
1378 AC_VERB_GET_CONNECT_SEL, 0);
1379 if (curr != mux_idx)
1380 snd_hda_codec_write_cache(codec, pin_nid, 0,
1381 AC_VERB_SET_CONNECT_SEL,
1382 mux_idx);
1383 }
1384
1385 /* Intel HDMI workaround to fix audio routing issue:
1386 * For some Intel display codecs, pins share the same connection list.
1387 * So a conveter can be selected by multiple pins and playback on any of these
1388 * pins will generate sound on the external display, because audio flows from
1389 * the same converter to the display pipeline. Also muting one pin may make
1390 * other pins have no sound output.
1391 * So this function assures that an assigned converter for a pin is not selected
1392 * by any other pins.
1393 */
intel_not_share_assigned_cvt(struct hda_codec * codec,hda_nid_t pin_nid,int mux_idx)1394 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1395 hda_nid_t pin_nid, int mux_idx)
1396 {
1397 struct hdmi_spec *spec = codec->spec;
1398 hda_nid_t nid, end_nid;
1399 int cvt_idx, curr;
1400 struct hdmi_spec_per_cvt *per_cvt;
1401
1402 /* configure all pins, including "no physical connection" ones */
1403 end_nid = codec->start_nid + codec->num_nodes;
1404 for (nid = codec->start_nid; nid < end_nid; nid++) {
1405 unsigned int wid_caps = get_wcaps(codec, nid);
1406 unsigned int wid_type = get_wcaps_type(wid_caps);
1407
1408 if (wid_type != AC_WID_PIN)
1409 continue;
1410
1411 if (nid == pin_nid)
1412 continue;
1413
1414 curr = snd_hda_codec_read(codec, nid, 0,
1415 AC_VERB_GET_CONNECT_SEL, 0);
1416 if (curr != mux_idx)
1417 continue;
1418
1419 /* choose an unassigned converter. The conveters in the
1420 * connection list are in the same order as in the codec.
1421 */
1422 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1423 per_cvt = get_cvt(spec, cvt_idx);
1424 if (!per_cvt->assigned) {
1425 codec_dbg(codec,
1426 "choose cvt %d for pin nid %d\n",
1427 cvt_idx, nid);
1428 snd_hda_codec_write_cache(codec, nid, 0,
1429 AC_VERB_SET_CONNECT_SEL,
1430 cvt_idx);
1431 break;
1432 }
1433 }
1434 }
1435 }
1436
1437 /*
1438 * HDA PCM callbacks
1439 */
hdmi_pcm_open(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)1440 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1441 struct hda_codec *codec,
1442 struct snd_pcm_substream *substream)
1443 {
1444 struct hdmi_spec *spec = codec->spec;
1445 struct snd_pcm_runtime *runtime = substream->runtime;
1446 int pin_idx, cvt_idx, mux_idx = 0;
1447 struct hdmi_spec_per_pin *per_pin;
1448 struct hdmi_eld *eld;
1449 struct hdmi_spec_per_cvt *per_cvt = NULL;
1450 int err;
1451
1452 /* Validate hinfo */
1453 pin_idx = hinfo_to_pin_index(codec, hinfo);
1454 if (snd_BUG_ON(pin_idx < 0))
1455 return -EINVAL;
1456 per_pin = get_pin(spec, pin_idx);
1457 eld = &per_pin->sink_eld;
1458
1459 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1460 if (err < 0)
1461 return err;
1462
1463 per_cvt = get_cvt(spec, cvt_idx);
1464 /* Claim converter */
1465 per_cvt->assigned = 1;
1466 per_pin->cvt_nid = per_cvt->cvt_nid;
1467 hinfo->nid = per_cvt->cvt_nid;
1468
1469 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1470 AC_VERB_SET_CONNECT_SEL,
1471 mux_idx);
1472
1473 /* configure unused pins to choose other converters */
1474 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
1475 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
1476
1477 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
1478
1479 /* Initially set the converter's capabilities */
1480 hinfo->channels_min = per_cvt->channels_min;
1481 hinfo->channels_max = per_cvt->channels_max;
1482 hinfo->rates = per_cvt->rates;
1483 hinfo->formats = per_cvt->formats;
1484 hinfo->maxbps = per_cvt->maxbps;
1485
1486 /* Restrict capabilities by ELD if this isn't disabled */
1487 if (!static_hdmi_pcm && eld->eld_valid) {
1488 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1489 if (hinfo->channels_min > hinfo->channels_max ||
1490 !hinfo->rates || !hinfo->formats) {
1491 per_cvt->assigned = 0;
1492 hinfo->nid = 0;
1493 snd_hda_spdif_ctls_unassign(codec, pin_idx);
1494 return -ENODEV;
1495 }
1496 }
1497
1498 /* Store the updated parameters */
1499 runtime->hw.channels_min = hinfo->channels_min;
1500 runtime->hw.channels_max = hinfo->channels_max;
1501 runtime->hw.formats = hinfo->formats;
1502 runtime->hw.rates = hinfo->rates;
1503
1504 snd_pcm_hw_constraint_step(substream->runtime, 0,
1505 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1506 return 0;
1507 }
1508
1509 /*
1510 * HDA/HDMI auto parsing
1511 */
hdmi_read_pin_conn(struct hda_codec * codec,int pin_idx)1512 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1513 {
1514 struct hdmi_spec *spec = codec->spec;
1515 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1516 hda_nid_t pin_nid = per_pin->pin_nid;
1517
1518 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1519 codec_warn(codec,
1520 "HDMI: pin %d wcaps %#x does not support connection list\n",
1521 pin_nid, get_wcaps(codec, pin_nid));
1522 return -EINVAL;
1523 }
1524
1525 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1526 per_pin->mux_nids,
1527 HDA_MAX_CONNECTIONS);
1528
1529 return 0;
1530 }
1531
hdmi_present_sense(struct hdmi_spec_per_pin * per_pin,int repoll)1532 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1533 {
1534 struct hda_jack_tbl *jack;
1535 struct hda_codec *codec = per_pin->codec;
1536 struct hdmi_spec *spec = codec->spec;
1537 struct hdmi_eld *eld = &spec->temp_eld;
1538 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1539 hda_nid_t pin_nid = per_pin->pin_nid;
1540 /*
1541 * Always execute a GetPinSense verb here, even when called from
1542 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1543 * response's PD bit is not the real PD value, but indicates that
1544 * the real PD value changed. An older version of the HD-audio
1545 * specification worked this way. Hence, we just ignore the data in
1546 * the unsolicited response to avoid custom WARs.
1547 */
1548 int present;
1549 bool update_eld = false;
1550 bool eld_changed = false;
1551 bool ret;
1552
1553 snd_hda_power_up(codec);
1554 present = snd_hda_pin_sense(codec, pin_nid);
1555
1556 mutex_lock(&per_pin->lock);
1557 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1558 eld->monitor_present = pin_eld->monitor_present;
1559
1560 if (pin_eld->monitor_present)
1561 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1562 else
1563 eld->eld_valid = false;
1564
1565 codec_dbg(codec,
1566 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1567 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
1568
1569 if (eld->eld_valid) {
1570 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1571 &eld->eld_size) < 0)
1572 eld->eld_valid = false;
1573 else {
1574 memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
1575 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1576 eld->eld_size) < 0)
1577 eld->eld_valid = false;
1578 }
1579
1580 if (eld->eld_valid) {
1581 snd_hdmi_show_eld(codec, &eld->info);
1582 update_eld = true;
1583 }
1584 else if (repoll) {
1585 queue_delayed_work(codec->bus->workq,
1586 &per_pin->work,
1587 msecs_to_jiffies(300));
1588 goto unlock;
1589 }
1590 }
1591
1592 if (pin_eld->eld_valid != eld->eld_valid)
1593 eld_changed = true;
1594
1595 if (pin_eld->eld_valid && !eld->eld_valid)
1596 update_eld = true;
1597
1598 if (update_eld) {
1599 bool old_eld_valid = pin_eld->eld_valid;
1600 pin_eld->eld_valid = eld->eld_valid;
1601 if (pin_eld->eld_size != eld->eld_size ||
1602 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1603 eld->eld_size) != 0) {
1604 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1605 eld->eld_size);
1606 eld_changed = true;
1607 }
1608 pin_eld->eld_size = eld->eld_size;
1609 pin_eld->info = eld->info;
1610
1611 /*
1612 * Re-setup pin and infoframe. This is needed e.g. when
1613 * - sink is first plugged-in (infoframe is not set up if !monitor_present)
1614 * - transcoder can change during stream playback on Haswell
1615 * and this can make HW reset converter selection on a pin.
1616 */
1617 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1618 if (is_haswell_plus(codec) ||
1619 is_valleyview_plus(codec)) {
1620 intel_verify_pin_cvt_connect(codec, per_pin);
1621 intel_not_share_assigned_cvt(codec, pin_nid,
1622 per_pin->mux_idx);
1623 }
1624
1625 hdmi_setup_audio_infoframe(codec, per_pin,
1626 per_pin->non_pcm);
1627 }
1628 }
1629
1630 if (eld_changed)
1631 snd_ctl_notify(codec->bus->card,
1632 SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
1633 &per_pin->eld_ctl->id);
1634 unlock:
1635 ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid;
1636
1637 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1638 if (jack)
1639 jack->block_report = !ret;
1640
1641 mutex_unlock(&per_pin->lock);
1642 snd_hda_power_down(codec);
1643 return ret;
1644 }
1645
hdmi_repoll_eld(struct work_struct * work)1646 static void hdmi_repoll_eld(struct work_struct *work)
1647 {
1648 struct hdmi_spec_per_pin *per_pin =
1649 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1650
1651 if (per_pin->repoll_count++ > 6)
1652 per_pin->repoll_count = 0;
1653
1654 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1655 snd_hda_jack_report_sync(per_pin->codec);
1656 }
1657
1658 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1659 hda_nid_t nid);
1660
hdmi_add_pin(struct hda_codec * codec,hda_nid_t pin_nid)1661 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1662 {
1663 struct hdmi_spec *spec = codec->spec;
1664 unsigned int caps, config;
1665 int pin_idx;
1666 struct hdmi_spec_per_pin *per_pin;
1667 int err;
1668
1669 caps = snd_hda_query_pin_caps(codec, pin_nid);
1670 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1671 return 0;
1672
1673 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1674 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1675 return 0;
1676
1677 if (is_haswell_plus(codec))
1678 intel_haswell_fixup_connect_list(codec, pin_nid);
1679
1680 pin_idx = spec->num_pins;
1681 per_pin = snd_array_new(&spec->pins);
1682 if (!per_pin)
1683 return -ENOMEM;
1684
1685 per_pin->pin_nid = pin_nid;
1686 per_pin->non_pcm = false;
1687
1688 err = hdmi_read_pin_conn(codec, pin_idx);
1689 if (err < 0)
1690 return err;
1691
1692 spec->num_pins++;
1693
1694 return 0;
1695 }
1696
hdmi_add_cvt(struct hda_codec * codec,hda_nid_t cvt_nid)1697 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1698 {
1699 struct hdmi_spec *spec = codec->spec;
1700 struct hdmi_spec_per_cvt *per_cvt;
1701 unsigned int chans;
1702 int err;
1703
1704 chans = get_wcaps(codec, cvt_nid);
1705 chans = get_wcaps_channels(chans);
1706
1707 per_cvt = snd_array_new(&spec->cvts);
1708 if (!per_cvt)
1709 return -ENOMEM;
1710
1711 per_cvt->cvt_nid = cvt_nid;
1712 per_cvt->channels_min = 2;
1713 if (chans <= 16) {
1714 per_cvt->channels_max = chans;
1715 if (chans > spec->channels_max)
1716 spec->channels_max = chans;
1717 }
1718
1719 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1720 &per_cvt->rates,
1721 &per_cvt->formats,
1722 &per_cvt->maxbps);
1723 if (err < 0)
1724 return err;
1725
1726 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1727 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1728 spec->num_cvts++;
1729
1730 return 0;
1731 }
1732
hdmi_parse_codec(struct hda_codec * codec)1733 static int hdmi_parse_codec(struct hda_codec *codec)
1734 {
1735 hda_nid_t nid;
1736 int i, nodes;
1737
1738 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
1739 if (!nid || nodes < 0) {
1740 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1741 return -EINVAL;
1742 }
1743
1744 for (i = 0; i < nodes; i++, nid++) {
1745 unsigned int caps;
1746 unsigned int type;
1747
1748 caps = get_wcaps(codec, nid);
1749 type = get_wcaps_type(caps);
1750
1751 if (!(caps & AC_WCAP_DIGITAL))
1752 continue;
1753
1754 switch (type) {
1755 case AC_WID_AUD_OUT:
1756 hdmi_add_cvt(codec, nid);
1757 break;
1758 case AC_WID_PIN:
1759 hdmi_add_pin(codec, nid);
1760 break;
1761 }
1762 }
1763
1764 return 0;
1765 }
1766
1767 /*
1768 */
check_non_pcm_per_cvt(struct hda_codec * codec,hda_nid_t cvt_nid)1769 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1770 {
1771 struct hda_spdif_out *spdif;
1772 bool non_pcm;
1773
1774 mutex_lock(&codec->spdif_mutex);
1775 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1776 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1777 mutex_unlock(&codec->spdif_mutex);
1778 return non_pcm;
1779 }
1780
1781
1782 /*
1783 * HDMI callbacks
1784 */
1785
generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream * hinfo,struct hda_codec * codec,unsigned int stream_tag,unsigned int format,struct snd_pcm_substream * substream)1786 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1787 struct hda_codec *codec,
1788 unsigned int stream_tag,
1789 unsigned int format,
1790 struct snd_pcm_substream *substream)
1791 {
1792 hda_nid_t cvt_nid = hinfo->nid;
1793 struct hdmi_spec *spec = codec->spec;
1794 int pin_idx = hinfo_to_pin_index(codec, hinfo);
1795 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1796 hda_nid_t pin_nid = per_pin->pin_nid;
1797 bool non_pcm;
1798 int pinctl;
1799
1800 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
1801 /* Verify pin:cvt selections to avoid silent audio after S3.
1802 * After S3, the audio driver restores pin:cvt selections
1803 * but this can happen before gfx is ready and such selection
1804 * is overlooked by HW. Thus multiple pins can share a same
1805 * default convertor and mute control will affect each other,
1806 * which can cause a resumed audio playback become silent
1807 * after S3.
1808 */
1809 intel_verify_pin_cvt_connect(codec, per_pin);
1810 intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx);
1811 }
1812
1813 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1814 mutex_lock(&per_pin->lock);
1815 per_pin->channels = substream->runtime->channels;
1816 per_pin->setup = true;
1817
1818 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1819 mutex_unlock(&per_pin->lock);
1820
1821 if (spec->dyn_pin_out) {
1822 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1823 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1824 snd_hda_codec_write(codec, pin_nid, 0,
1825 AC_VERB_SET_PIN_WIDGET_CONTROL,
1826 pinctl | PIN_OUT);
1827 }
1828
1829 return spec->ops.setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
1830 }
1831
generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)1832 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1833 struct hda_codec *codec,
1834 struct snd_pcm_substream *substream)
1835 {
1836 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1837 return 0;
1838 }
1839
hdmi_pcm_close(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)1840 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1841 struct hda_codec *codec,
1842 struct snd_pcm_substream *substream)
1843 {
1844 struct hdmi_spec *spec = codec->spec;
1845 int cvt_idx, pin_idx;
1846 struct hdmi_spec_per_cvt *per_cvt;
1847 struct hdmi_spec_per_pin *per_pin;
1848 int pinctl;
1849
1850 if (hinfo->nid) {
1851 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1852 if (snd_BUG_ON(cvt_idx < 0))
1853 return -EINVAL;
1854 per_cvt = get_cvt(spec, cvt_idx);
1855
1856 snd_BUG_ON(!per_cvt->assigned);
1857 per_cvt->assigned = 0;
1858 hinfo->nid = 0;
1859
1860 pin_idx = hinfo_to_pin_index(codec, hinfo);
1861 if (snd_BUG_ON(pin_idx < 0))
1862 return -EINVAL;
1863 per_pin = get_pin(spec, pin_idx);
1864
1865 if (spec->dyn_pin_out) {
1866 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1867 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1868 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1869 AC_VERB_SET_PIN_WIDGET_CONTROL,
1870 pinctl & ~PIN_OUT);
1871 }
1872
1873 snd_hda_spdif_ctls_unassign(codec, pin_idx);
1874
1875 mutex_lock(&per_pin->lock);
1876 per_pin->chmap_set = false;
1877 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1878
1879 per_pin->setup = false;
1880 per_pin->channels = 0;
1881 mutex_unlock(&per_pin->lock);
1882 }
1883
1884 return 0;
1885 }
1886
1887 static const struct hda_pcm_ops generic_ops = {
1888 .open = hdmi_pcm_open,
1889 .close = hdmi_pcm_close,
1890 .prepare = generic_hdmi_playback_pcm_prepare,
1891 .cleanup = generic_hdmi_playback_pcm_cleanup,
1892 };
1893
1894 /*
1895 * ALSA API channel-map control callbacks
1896 */
hdmi_chmap_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1897 static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1898 struct snd_ctl_elem_info *uinfo)
1899 {
1900 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1901 struct hda_codec *codec = info->private_data;
1902 struct hdmi_spec *spec = codec->spec;
1903 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1904 uinfo->count = spec->channels_max;
1905 uinfo->value.integer.min = 0;
1906 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1907 return 0;
1908 }
1909
hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation * cap,int channels)1910 static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
1911 int channels)
1912 {
1913 /* If the speaker allocation matches the channel count, it is OK.*/
1914 if (cap->channels != channels)
1915 return -1;
1916
1917 /* all channels are remappable freely */
1918 return SNDRV_CTL_TLVT_CHMAP_VAR;
1919 }
1920
hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation * cap,unsigned int * chmap,int channels)1921 static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
1922 unsigned int *chmap, int channels)
1923 {
1924 int count = 0;
1925 int c;
1926
1927 for (c = 7; c >= 0; c--) {
1928 int spk = cap->speakers[c];
1929 if (!spk)
1930 continue;
1931
1932 chmap[count++] = spk_to_chmap(spk);
1933 }
1934
1935 WARN_ON(count != channels);
1936 }
1937
hdmi_chmap_ctl_tlv(struct snd_kcontrol * kcontrol,int op_flag,unsigned int size,unsigned int __user * tlv)1938 static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1939 unsigned int size, unsigned int __user *tlv)
1940 {
1941 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1942 struct hda_codec *codec = info->private_data;
1943 struct hdmi_spec *spec = codec->spec;
1944 unsigned int __user *dst;
1945 int chs, count = 0;
1946
1947 if (size < 8)
1948 return -ENOMEM;
1949 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1950 return -EFAULT;
1951 size -= 8;
1952 dst = tlv + 2;
1953 for (chs = 2; chs <= spec->channels_max; chs++) {
1954 int i;
1955 struct cea_channel_speaker_allocation *cap;
1956 cap = channel_allocations;
1957 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1958 int chs_bytes = chs * 4;
1959 int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs);
1960 unsigned int tlv_chmap[8];
1961
1962 if (type < 0)
1963 continue;
1964 if (size < 8)
1965 return -ENOMEM;
1966 if (put_user(type, dst) ||
1967 put_user(chs_bytes, dst + 1))
1968 return -EFAULT;
1969 dst += 2;
1970 size -= 8;
1971 count += 8;
1972 if (size < chs_bytes)
1973 return -ENOMEM;
1974 size -= chs_bytes;
1975 count += chs_bytes;
1976 spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs);
1977 if (copy_to_user(dst, tlv_chmap, chs_bytes))
1978 return -EFAULT;
1979 dst += chs;
1980 }
1981 }
1982 if (put_user(count, tlv + 1))
1983 return -EFAULT;
1984 return 0;
1985 }
1986
hdmi_chmap_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1987 static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
1988 struct snd_ctl_elem_value *ucontrol)
1989 {
1990 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1991 struct hda_codec *codec = info->private_data;
1992 struct hdmi_spec *spec = codec->spec;
1993 int pin_idx = kcontrol->private_value;
1994 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1995 int i;
1996
1997 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
1998 ucontrol->value.integer.value[i] = per_pin->chmap[i];
1999 return 0;
2000 }
2001
hdmi_chmap_ctl_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2002 static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
2003 struct snd_ctl_elem_value *ucontrol)
2004 {
2005 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2006 struct hda_codec *codec = info->private_data;
2007 struct hdmi_spec *spec = codec->spec;
2008 int pin_idx = kcontrol->private_value;
2009 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2010 unsigned int ctl_idx;
2011 struct snd_pcm_substream *substream;
2012 unsigned char chmap[8];
2013 int i, err, ca, prepared = 0;
2014
2015 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2016 substream = snd_pcm_chmap_substream(info, ctl_idx);
2017 if (!substream || !substream->runtime)
2018 return 0; /* just for avoiding error from alsactl restore */
2019 switch (substream->runtime->status->state) {
2020 case SNDRV_PCM_STATE_OPEN:
2021 case SNDRV_PCM_STATE_SETUP:
2022 break;
2023 case SNDRV_PCM_STATE_PREPARED:
2024 prepared = 1;
2025 break;
2026 default:
2027 return -EBUSY;
2028 }
2029 memset(chmap, 0, sizeof(chmap));
2030 for (i = 0; i < ARRAY_SIZE(chmap); i++)
2031 chmap[i] = ucontrol->value.integer.value[i];
2032 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
2033 return 0;
2034 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
2035 if (ca < 0)
2036 return -EINVAL;
2037 if (spec->ops.chmap_validate) {
2038 err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap);
2039 if (err)
2040 return err;
2041 }
2042 mutex_lock(&per_pin->lock);
2043 per_pin->chmap_set = true;
2044 memcpy(per_pin->chmap, chmap, sizeof(chmap));
2045 if (prepared)
2046 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2047 mutex_unlock(&per_pin->lock);
2048
2049 return 0;
2050 }
2051
generic_hdmi_build_pcms(struct hda_codec * codec)2052 static int generic_hdmi_build_pcms(struct hda_codec *codec)
2053 {
2054 struct hdmi_spec *spec = codec->spec;
2055 int pin_idx;
2056
2057 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2058 struct hda_pcm *info;
2059 struct hda_pcm_stream *pstr;
2060 struct hdmi_spec_per_pin *per_pin;
2061
2062 per_pin = get_pin(spec, pin_idx);
2063 sprintf(per_pin->pcm_name, "HDMI %d", pin_idx);
2064 info = snd_array_new(&spec->pcm_rec);
2065 if (!info)
2066 return -ENOMEM;
2067 info->name = per_pin->pcm_name;
2068 info->pcm_type = HDA_PCM_TYPE_HDMI;
2069 info->own_chmap = true;
2070
2071 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2072 pstr->substreams = 1;
2073 pstr->ops = generic_ops;
2074 /* other pstr fields are set in open */
2075 }
2076
2077 codec->num_pcms = spec->num_pins;
2078 codec->pcm_info = spec->pcm_rec.list;
2079
2080 return 0;
2081 }
2082
generic_hdmi_build_jack(struct hda_codec * codec,int pin_idx)2083 static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
2084 {
2085 char hdmi_str[32] = "HDMI/DP";
2086 struct hdmi_spec *spec = codec->spec;
2087 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2088 int pcmdev = get_pcm_rec(spec, pin_idx)->device;
2089
2090 if (pcmdev > 0)
2091 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2092 if (!is_jack_detectable(codec, per_pin->pin_nid))
2093 strncat(hdmi_str, " Phantom",
2094 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2095
2096 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0);
2097 }
2098
generic_hdmi_build_controls(struct hda_codec * codec)2099 static int generic_hdmi_build_controls(struct hda_codec *codec)
2100 {
2101 struct hdmi_spec *spec = codec->spec;
2102 int err;
2103 int pin_idx;
2104
2105 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2106 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2107
2108 err = generic_hdmi_build_jack(codec, pin_idx);
2109 if (err < 0)
2110 return err;
2111
2112 err = snd_hda_create_dig_out_ctls(codec,
2113 per_pin->pin_nid,
2114 per_pin->mux_nids[0],
2115 HDA_PCM_TYPE_HDMI);
2116 if (err < 0)
2117 return err;
2118 snd_hda_spdif_ctls_unassign(codec, pin_idx);
2119
2120 /* add control for ELD Bytes */
2121 err = hdmi_create_eld_ctl(codec, pin_idx,
2122 get_pcm_rec(spec, pin_idx)->device);
2123
2124 if (err < 0)
2125 return err;
2126
2127 hdmi_present_sense(per_pin, 0);
2128 }
2129
2130 /* add channel maps */
2131 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2132 struct snd_pcm_chmap *chmap;
2133 struct snd_kcontrol *kctl;
2134 int i;
2135
2136 if (!codec->pcm_info[pin_idx].pcm)
2137 break;
2138 err = snd_pcm_add_chmap_ctls(codec->pcm_info[pin_idx].pcm,
2139 SNDRV_PCM_STREAM_PLAYBACK,
2140 NULL, 0, pin_idx, &chmap);
2141 if (err < 0)
2142 return err;
2143 /* override handlers */
2144 chmap->private_data = codec;
2145 kctl = chmap->kctl;
2146 for (i = 0; i < kctl->count; i++)
2147 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
2148 kctl->info = hdmi_chmap_ctl_info;
2149 kctl->get = hdmi_chmap_ctl_get;
2150 kctl->put = hdmi_chmap_ctl_put;
2151 kctl->tlv.c = hdmi_chmap_ctl_tlv;
2152 }
2153
2154 return 0;
2155 }
2156
generic_hdmi_init_per_pins(struct hda_codec * codec)2157 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2158 {
2159 struct hdmi_spec *spec = codec->spec;
2160 int pin_idx;
2161
2162 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2163 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2164
2165 per_pin->codec = codec;
2166 mutex_init(&per_pin->lock);
2167 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2168 eld_proc_new(per_pin, pin_idx);
2169 }
2170 return 0;
2171 }
2172
generic_hdmi_init(struct hda_codec * codec)2173 static int generic_hdmi_init(struct hda_codec *codec)
2174 {
2175 struct hdmi_spec *spec = codec->spec;
2176 int pin_idx;
2177
2178 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2179 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2180 hda_nid_t pin_nid = per_pin->pin_nid;
2181
2182 hdmi_init_pin(codec, pin_nid);
2183 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2184 codec->jackpoll_interval > 0 ? jack_callback : NULL);
2185 }
2186 return 0;
2187 }
2188
hdmi_array_init(struct hdmi_spec * spec,int nums)2189 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2190 {
2191 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2192 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2193 snd_array_init(&spec->pcm_rec, sizeof(struct hda_pcm), nums);
2194 }
2195
hdmi_array_free(struct hdmi_spec * spec)2196 static void hdmi_array_free(struct hdmi_spec *spec)
2197 {
2198 snd_array_free(&spec->pins);
2199 snd_array_free(&spec->cvts);
2200 snd_array_free(&spec->pcm_rec);
2201 }
2202
generic_hdmi_free(struct hda_codec * codec)2203 static void generic_hdmi_free(struct hda_codec *codec)
2204 {
2205 struct hdmi_spec *spec = codec->spec;
2206 int pin_idx;
2207
2208 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2209 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2210
2211 cancel_delayed_work(&per_pin->work);
2212 eld_proc_free(per_pin);
2213 }
2214
2215 flush_workqueue(codec->bus->workq);
2216 hdmi_array_free(spec);
2217 kfree(spec);
2218 }
2219
2220 #ifdef CONFIG_PM
generic_hdmi_resume(struct hda_codec * codec)2221 static int generic_hdmi_resume(struct hda_codec *codec)
2222 {
2223 struct hdmi_spec *spec = codec->spec;
2224 int pin_idx;
2225
2226 codec->patch_ops.init(codec);
2227 snd_hda_codec_resume_amp(codec);
2228 snd_hda_codec_resume_cache(codec);
2229
2230 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2231 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2232 hdmi_present_sense(per_pin, 1);
2233 }
2234 return 0;
2235 }
2236 #endif
2237
2238 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2239 .init = generic_hdmi_init,
2240 .free = generic_hdmi_free,
2241 .build_pcms = generic_hdmi_build_pcms,
2242 .build_controls = generic_hdmi_build_controls,
2243 .unsol_event = hdmi_unsol_event,
2244 #ifdef CONFIG_PM
2245 .resume = generic_hdmi_resume,
2246 #endif
2247 };
2248
2249 static const struct hdmi_ops generic_standard_hdmi_ops = {
2250 .pin_get_eld = snd_hdmi_get_eld,
2251 .pin_get_slot_channel = hdmi_pin_get_slot_channel,
2252 .pin_set_slot_channel = hdmi_pin_set_slot_channel,
2253 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2254 .pin_hbr_setup = hdmi_pin_hbr_setup,
2255 .setup_stream = hdmi_setup_stream,
2256 .chmap_cea_alloc_validate_get_type = hdmi_chmap_cea_alloc_validate_get_type,
2257 .cea_alloc_to_tlv_chmap = hdmi_cea_alloc_to_tlv_chmap,
2258 };
2259
2260
intel_haswell_fixup_connect_list(struct hda_codec * codec,hda_nid_t nid)2261 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2262 hda_nid_t nid)
2263 {
2264 struct hdmi_spec *spec = codec->spec;
2265 hda_nid_t conns[4];
2266 int nconns;
2267
2268 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2269 if (nconns == spec->num_cvts &&
2270 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2271 return;
2272
2273 /* override pins connection list */
2274 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2275 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2276 }
2277
2278 #define INTEL_VENDOR_NID 0x08
2279 #define INTEL_GET_VENDOR_VERB 0xf81
2280 #define INTEL_SET_VENDOR_VERB 0x781
2281 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2282 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2283
intel_haswell_enable_all_pins(struct hda_codec * codec,bool update_tree)2284 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2285 bool update_tree)
2286 {
2287 unsigned int vendor_param;
2288
2289 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2290 INTEL_GET_VENDOR_VERB, 0);
2291 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2292 return;
2293
2294 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2295 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2296 INTEL_SET_VENDOR_VERB, vendor_param);
2297 if (vendor_param == -1)
2298 return;
2299
2300 if (update_tree)
2301 snd_hda_codec_update_widgets(codec);
2302 }
2303
intel_haswell_fixup_enable_dp12(struct hda_codec * codec)2304 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2305 {
2306 unsigned int vendor_param;
2307
2308 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2309 INTEL_GET_VENDOR_VERB, 0);
2310 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2311 return;
2312
2313 /* enable DP1.2 mode */
2314 vendor_param |= INTEL_EN_DP12;
2315 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2316 INTEL_SET_VENDOR_VERB, vendor_param);
2317 }
2318
2319 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2320 * Otherwise you may get severe h/w communication errors.
2321 */
haswell_set_power_state(struct hda_codec * codec,hda_nid_t fg,unsigned int power_state)2322 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2323 unsigned int power_state)
2324 {
2325 if (power_state == AC_PWRST_D0) {
2326 intel_haswell_enable_all_pins(codec, false);
2327 intel_haswell_fixup_enable_dp12(codec);
2328 }
2329
2330 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2331 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2332 }
2333
patch_generic_hdmi(struct hda_codec * codec)2334 static int patch_generic_hdmi(struct hda_codec *codec)
2335 {
2336 struct hdmi_spec *spec;
2337
2338 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2339 if (spec == NULL)
2340 return -ENOMEM;
2341
2342 spec->ops = generic_standard_hdmi_ops;
2343 codec->spec = spec;
2344 hdmi_array_init(spec, 4);
2345
2346 if (is_haswell_plus(codec)) {
2347 intel_haswell_enable_all_pins(codec, true);
2348 intel_haswell_fixup_enable_dp12(codec);
2349 }
2350
2351 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2352 codec->depop_delay = 0;
2353
2354 if (hdmi_parse_codec(codec) < 0) {
2355 codec->spec = NULL;
2356 kfree(spec);
2357 return -EINVAL;
2358 }
2359 codec->patch_ops = generic_hdmi_patch_ops;
2360 if (is_haswell_plus(codec)) {
2361 codec->patch_ops.set_power_state = haswell_set_power_state;
2362 codec->dp_mst = true;
2363 }
2364
2365 generic_hdmi_init_per_pins(codec);
2366
2367 init_channel_allocations();
2368
2369 return 0;
2370 }
2371
2372 /*
2373 * Shared non-generic implementations
2374 */
2375
simple_playback_build_pcms(struct hda_codec * codec)2376 static int simple_playback_build_pcms(struct hda_codec *codec)
2377 {
2378 struct hdmi_spec *spec = codec->spec;
2379 struct hda_pcm *info;
2380 unsigned int chans;
2381 struct hda_pcm_stream *pstr;
2382 struct hdmi_spec_per_cvt *per_cvt;
2383
2384 per_cvt = get_cvt(spec, 0);
2385 chans = get_wcaps(codec, per_cvt->cvt_nid);
2386 chans = get_wcaps_channels(chans);
2387
2388 info = snd_array_new(&spec->pcm_rec);
2389 if (!info)
2390 return -ENOMEM;
2391 info->name = get_pin(spec, 0)->pcm_name;
2392 sprintf(info->name, "HDMI 0");
2393 info->pcm_type = HDA_PCM_TYPE_HDMI;
2394 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2395 *pstr = spec->pcm_playback;
2396 pstr->nid = per_cvt->cvt_nid;
2397 if (pstr->channels_max <= 2 && chans && chans <= 16)
2398 pstr->channels_max = chans;
2399
2400 codec->num_pcms = 1;
2401 codec->pcm_info = info;
2402
2403 return 0;
2404 }
2405
2406 /* unsolicited event for jack sensing */
simple_hdmi_unsol_event(struct hda_codec * codec,unsigned int res)2407 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2408 unsigned int res)
2409 {
2410 snd_hda_jack_set_dirty_all(codec);
2411 snd_hda_jack_report_sync(codec);
2412 }
2413
2414 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2415 * as long as spec->pins[] is set correctly
2416 */
2417 #define simple_hdmi_build_jack generic_hdmi_build_jack
2418
simple_playback_build_controls(struct hda_codec * codec)2419 static int simple_playback_build_controls(struct hda_codec *codec)
2420 {
2421 struct hdmi_spec *spec = codec->spec;
2422 struct hdmi_spec_per_cvt *per_cvt;
2423 int err;
2424
2425 per_cvt = get_cvt(spec, 0);
2426 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2427 per_cvt->cvt_nid,
2428 HDA_PCM_TYPE_HDMI);
2429 if (err < 0)
2430 return err;
2431 return simple_hdmi_build_jack(codec, 0);
2432 }
2433
simple_playback_init(struct hda_codec * codec)2434 static int simple_playback_init(struct hda_codec *codec)
2435 {
2436 struct hdmi_spec *spec = codec->spec;
2437 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2438 hda_nid_t pin = per_pin->pin_nid;
2439
2440 snd_hda_codec_write(codec, pin, 0,
2441 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2442 /* some codecs require to unmute the pin */
2443 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2444 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2445 AMP_OUT_UNMUTE);
2446 snd_hda_jack_detect_enable(codec, pin);
2447 return 0;
2448 }
2449
simple_playback_free(struct hda_codec * codec)2450 static void simple_playback_free(struct hda_codec *codec)
2451 {
2452 struct hdmi_spec *spec = codec->spec;
2453
2454 hdmi_array_free(spec);
2455 kfree(spec);
2456 }
2457
2458 /*
2459 * Nvidia specific implementations
2460 */
2461
2462 #define Nv_VERB_SET_Channel_Allocation 0xF79
2463 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2464 #define Nv_VERB_SET_Audio_Protection_On 0xF98
2465 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
2466
2467 #define nvhdmi_master_con_nid_7x 0x04
2468 #define nvhdmi_master_pin_nid_7x 0x05
2469
2470 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2471 /*front, rear, clfe, rear_surr */
2472 0x6, 0x8, 0xa, 0xc,
2473 };
2474
2475 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2476 /* set audio protect on */
2477 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2478 /* enable digital output on pin widget */
2479 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2480 {} /* terminator */
2481 };
2482
2483 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2484 /* set audio protect on */
2485 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2486 /* enable digital output on pin widget */
2487 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2488 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2489 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2490 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2491 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2492 {} /* terminator */
2493 };
2494
2495 #ifdef LIMITED_RATE_FMT_SUPPORT
2496 /* support only the safe format and rate */
2497 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2498 #define SUPPORTED_MAXBPS 16
2499 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2500 #else
2501 /* support all rates and formats */
2502 #define SUPPORTED_RATES \
2503 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2504 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2505 SNDRV_PCM_RATE_192000)
2506 #define SUPPORTED_MAXBPS 24
2507 #define SUPPORTED_FORMATS \
2508 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2509 #endif
2510
nvhdmi_7x_init_2ch(struct hda_codec * codec)2511 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2512 {
2513 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2514 return 0;
2515 }
2516
nvhdmi_7x_init_8ch(struct hda_codec * codec)2517 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2518 {
2519 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2520 return 0;
2521 }
2522
2523 static unsigned int channels_2_6_8[] = {
2524 2, 6, 8
2525 };
2526
2527 static unsigned int channels_2_8[] = {
2528 2, 8
2529 };
2530
2531 static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2532 .count = ARRAY_SIZE(channels_2_6_8),
2533 .list = channels_2_6_8,
2534 .mask = 0,
2535 };
2536
2537 static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2538 .count = ARRAY_SIZE(channels_2_8),
2539 .list = channels_2_8,
2540 .mask = 0,
2541 };
2542
simple_playback_pcm_open(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)2543 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2544 struct hda_codec *codec,
2545 struct snd_pcm_substream *substream)
2546 {
2547 struct hdmi_spec *spec = codec->spec;
2548 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2549
2550 switch (codec->preset->id) {
2551 case 0x10de0002:
2552 case 0x10de0003:
2553 case 0x10de0005:
2554 case 0x10de0006:
2555 hw_constraints_channels = &hw_constraints_2_8_channels;
2556 break;
2557 case 0x10de0007:
2558 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2559 break;
2560 default:
2561 break;
2562 }
2563
2564 if (hw_constraints_channels != NULL) {
2565 snd_pcm_hw_constraint_list(substream->runtime, 0,
2566 SNDRV_PCM_HW_PARAM_CHANNELS,
2567 hw_constraints_channels);
2568 } else {
2569 snd_pcm_hw_constraint_step(substream->runtime, 0,
2570 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2571 }
2572
2573 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2574 }
2575
simple_playback_pcm_close(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)2576 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2577 struct hda_codec *codec,
2578 struct snd_pcm_substream *substream)
2579 {
2580 struct hdmi_spec *spec = codec->spec;
2581 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2582 }
2583
simple_playback_pcm_prepare(struct hda_pcm_stream * hinfo,struct hda_codec * codec,unsigned int stream_tag,unsigned int format,struct snd_pcm_substream * substream)2584 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2585 struct hda_codec *codec,
2586 unsigned int stream_tag,
2587 unsigned int format,
2588 struct snd_pcm_substream *substream)
2589 {
2590 struct hdmi_spec *spec = codec->spec;
2591 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2592 stream_tag, format, substream);
2593 }
2594
2595 static const struct hda_pcm_stream simple_pcm_playback = {
2596 .substreams = 1,
2597 .channels_min = 2,
2598 .channels_max = 2,
2599 .ops = {
2600 .open = simple_playback_pcm_open,
2601 .close = simple_playback_pcm_close,
2602 .prepare = simple_playback_pcm_prepare
2603 },
2604 };
2605
2606 static const struct hda_codec_ops simple_hdmi_patch_ops = {
2607 .build_controls = simple_playback_build_controls,
2608 .build_pcms = simple_playback_build_pcms,
2609 .init = simple_playback_init,
2610 .free = simple_playback_free,
2611 .unsol_event = simple_hdmi_unsol_event,
2612 };
2613
patch_simple_hdmi(struct hda_codec * codec,hda_nid_t cvt_nid,hda_nid_t pin_nid)2614 static int patch_simple_hdmi(struct hda_codec *codec,
2615 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2616 {
2617 struct hdmi_spec *spec;
2618 struct hdmi_spec_per_cvt *per_cvt;
2619 struct hdmi_spec_per_pin *per_pin;
2620
2621 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2622 if (!spec)
2623 return -ENOMEM;
2624
2625 codec->spec = spec;
2626 hdmi_array_init(spec, 1);
2627
2628 spec->multiout.num_dacs = 0; /* no analog */
2629 spec->multiout.max_channels = 2;
2630 spec->multiout.dig_out_nid = cvt_nid;
2631 spec->num_cvts = 1;
2632 spec->num_pins = 1;
2633 per_pin = snd_array_new(&spec->pins);
2634 per_cvt = snd_array_new(&spec->cvts);
2635 if (!per_pin || !per_cvt) {
2636 simple_playback_free(codec);
2637 return -ENOMEM;
2638 }
2639 per_cvt->cvt_nid = cvt_nid;
2640 per_pin->pin_nid = pin_nid;
2641 spec->pcm_playback = simple_pcm_playback;
2642
2643 codec->patch_ops = simple_hdmi_patch_ops;
2644
2645 return 0;
2646 }
2647
nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec * codec,int channels)2648 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2649 int channels)
2650 {
2651 unsigned int chanmask;
2652 int chan = channels ? (channels - 1) : 1;
2653
2654 switch (channels) {
2655 default:
2656 case 0:
2657 case 2:
2658 chanmask = 0x00;
2659 break;
2660 case 4:
2661 chanmask = 0x08;
2662 break;
2663 case 6:
2664 chanmask = 0x0b;
2665 break;
2666 case 8:
2667 chanmask = 0x13;
2668 break;
2669 }
2670
2671 /* Set the audio infoframe channel allocation and checksum fields. The
2672 * channel count is computed implicitly by the hardware. */
2673 snd_hda_codec_write(codec, 0x1, 0,
2674 Nv_VERB_SET_Channel_Allocation, chanmask);
2675
2676 snd_hda_codec_write(codec, 0x1, 0,
2677 Nv_VERB_SET_Info_Frame_Checksum,
2678 (0x71 - chan - chanmask));
2679 }
2680
nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)2681 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2682 struct hda_codec *codec,
2683 struct snd_pcm_substream *substream)
2684 {
2685 struct hdmi_spec *spec = codec->spec;
2686 int i;
2687
2688 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2689 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2690 for (i = 0; i < 4; i++) {
2691 /* set the stream id */
2692 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2693 AC_VERB_SET_CHANNEL_STREAMID, 0);
2694 /* set the stream format */
2695 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2696 AC_VERB_SET_STREAM_FORMAT, 0);
2697 }
2698
2699 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2700 * streams are disabled. */
2701 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2702
2703 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2704 }
2705
nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream * hinfo,struct hda_codec * codec,unsigned int stream_tag,unsigned int format,struct snd_pcm_substream * substream)2706 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2707 struct hda_codec *codec,
2708 unsigned int stream_tag,
2709 unsigned int format,
2710 struct snd_pcm_substream *substream)
2711 {
2712 int chs;
2713 unsigned int dataDCC2, channel_id;
2714 int i;
2715 struct hdmi_spec *spec = codec->spec;
2716 struct hda_spdif_out *spdif;
2717 struct hdmi_spec_per_cvt *per_cvt;
2718
2719 mutex_lock(&codec->spdif_mutex);
2720 per_cvt = get_cvt(spec, 0);
2721 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
2722
2723 chs = substream->runtime->channels;
2724
2725 dataDCC2 = 0x2;
2726
2727 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
2728 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
2729 snd_hda_codec_write(codec,
2730 nvhdmi_master_con_nid_7x,
2731 0,
2732 AC_VERB_SET_DIGI_CONVERT_1,
2733 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2734
2735 /* set the stream id */
2736 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2737 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2738
2739 /* set the stream format */
2740 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2741 AC_VERB_SET_STREAM_FORMAT, format);
2742
2743 /* turn on again (if needed) */
2744 /* enable and set the channel status audio/data flag */
2745 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
2746 snd_hda_codec_write(codec,
2747 nvhdmi_master_con_nid_7x,
2748 0,
2749 AC_VERB_SET_DIGI_CONVERT_1,
2750 spdif->ctls & 0xff);
2751 snd_hda_codec_write(codec,
2752 nvhdmi_master_con_nid_7x,
2753 0,
2754 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2755 }
2756
2757 for (i = 0; i < 4; i++) {
2758 if (chs == 2)
2759 channel_id = 0;
2760 else
2761 channel_id = i * 2;
2762
2763 /* turn off SPDIF once;
2764 *otherwise the IEC958 bits won't be updated
2765 */
2766 if (codec->spdif_status_reset &&
2767 (spdif->ctls & AC_DIG1_ENABLE))
2768 snd_hda_codec_write(codec,
2769 nvhdmi_con_nids_7x[i],
2770 0,
2771 AC_VERB_SET_DIGI_CONVERT_1,
2772 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2773 /* set the stream id */
2774 snd_hda_codec_write(codec,
2775 nvhdmi_con_nids_7x[i],
2776 0,
2777 AC_VERB_SET_CHANNEL_STREAMID,
2778 (stream_tag << 4) | channel_id);
2779 /* set the stream format */
2780 snd_hda_codec_write(codec,
2781 nvhdmi_con_nids_7x[i],
2782 0,
2783 AC_VERB_SET_STREAM_FORMAT,
2784 format);
2785 /* turn on again (if needed) */
2786 /* enable and set the channel status audio/data flag */
2787 if (codec->spdif_status_reset &&
2788 (spdif->ctls & AC_DIG1_ENABLE)) {
2789 snd_hda_codec_write(codec,
2790 nvhdmi_con_nids_7x[i],
2791 0,
2792 AC_VERB_SET_DIGI_CONVERT_1,
2793 spdif->ctls & 0xff);
2794 snd_hda_codec_write(codec,
2795 nvhdmi_con_nids_7x[i],
2796 0,
2797 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2798 }
2799 }
2800
2801 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
2802
2803 mutex_unlock(&codec->spdif_mutex);
2804 return 0;
2805 }
2806
2807 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
2808 .substreams = 1,
2809 .channels_min = 2,
2810 .channels_max = 8,
2811 .nid = nvhdmi_master_con_nid_7x,
2812 .rates = SUPPORTED_RATES,
2813 .maxbps = SUPPORTED_MAXBPS,
2814 .formats = SUPPORTED_FORMATS,
2815 .ops = {
2816 .open = simple_playback_pcm_open,
2817 .close = nvhdmi_8ch_7x_pcm_close,
2818 .prepare = nvhdmi_8ch_7x_pcm_prepare
2819 },
2820 };
2821
patch_nvhdmi_2ch(struct hda_codec * codec)2822 static int patch_nvhdmi_2ch(struct hda_codec *codec)
2823 {
2824 struct hdmi_spec *spec;
2825 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2826 nvhdmi_master_pin_nid_7x);
2827 if (err < 0)
2828 return err;
2829
2830 codec->patch_ops.init = nvhdmi_7x_init_2ch;
2831 /* override the PCM rates, etc, as the codec doesn't give full list */
2832 spec = codec->spec;
2833 spec->pcm_playback.rates = SUPPORTED_RATES;
2834 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2835 spec->pcm_playback.formats = SUPPORTED_FORMATS;
2836 return 0;
2837 }
2838
nvhdmi_7x_8ch_build_pcms(struct hda_codec * codec)2839 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2840 {
2841 struct hdmi_spec *spec = codec->spec;
2842 int err = simple_playback_build_pcms(codec);
2843 if (!err) {
2844 struct hda_pcm *info = get_pcm_rec(spec, 0);
2845 info->own_chmap = true;
2846 }
2847 return err;
2848 }
2849
nvhdmi_7x_8ch_build_controls(struct hda_codec * codec)2850 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2851 {
2852 struct hdmi_spec *spec = codec->spec;
2853 struct hda_pcm *info;
2854 struct snd_pcm_chmap *chmap;
2855 int err;
2856
2857 err = simple_playback_build_controls(codec);
2858 if (err < 0)
2859 return err;
2860
2861 /* add channel maps */
2862 info = get_pcm_rec(spec, 0);
2863 err = snd_pcm_add_chmap_ctls(info->pcm,
2864 SNDRV_PCM_STREAM_PLAYBACK,
2865 snd_pcm_alt_chmaps, 8, 0, &chmap);
2866 if (err < 0)
2867 return err;
2868 switch (codec->preset->id) {
2869 case 0x10de0002:
2870 case 0x10de0003:
2871 case 0x10de0005:
2872 case 0x10de0006:
2873 chmap->channel_mask = (1U << 2) | (1U << 8);
2874 break;
2875 case 0x10de0007:
2876 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2877 }
2878 return 0;
2879 }
2880
patch_nvhdmi_8ch_7x(struct hda_codec * codec)2881 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2882 {
2883 struct hdmi_spec *spec;
2884 int err = patch_nvhdmi_2ch(codec);
2885 if (err < 0)
2886 return err;
2887 spec = codec->spec;
2888 spec->multiout.max_channels = 8;
2889 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
2890 codec->patch_ops.init = nvhdmi_7x_init_8ch;
2891 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2892 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
2893
2894 /* Initialize the audio infoframe channel mask and checksum to something
2895 * valid */
2896 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2897
2898 return 0;
2899 }
2900
2901 /*
2902 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
2903 * - 0x10de0015
2904 * - 0x10de0040
2905 */
nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation * cap,int channels)2906 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
2907 int channels)
2908 {
2909 if (cap->ca_index == 0x00 && channels == 2)
2910 return SNDRV_CTL_TLVT_CHMAP_FIXED;
2911
2912 return hdmi_chmap_cea_alloc_validate_get_type(cap, channels);
2913 }
2914
nvhdmi_chmap_validate(int ca,int chs,unsigned char * map)2915 static int nvhdmi_chmap_validate(int ca, int chs, unsigned char *map)
2916 {
2917 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
2918 return -EINVAL;
2919
2920 return 0;
2921 }
2922
patch_nvhdmi(struct hda_codec * codec)2923 static int patch_nvhdmi(struct hda_codec *codec)
2924 {
2925 struct hdmi_spec *spec;
2926 int err;
2927
2928 err = patch_generic_hdmi(codec);
2929 if (err)
2930 return err;
2931
2932 spec = codec->spec;
2933 spec->dyn_pin_out = true;
2934
2935 spec->ops.chmap_cea_alloc_validate_get_type =
2936 nvhdmi_chmap_cea_alloc_validate_get_type;
2937 spec->ops.chmap_validate = nvhdmi_chmap_validate;
2938
2939 return 0;
2940 }
2941
2942 /*
2943 * ATI/AMD-specific implementations
2944 */
2945
2946 #define is_amdhdmi_rev3_or_later(codec) \
2947 ((codec)->vendor_id == 0x1002aa01 && ((codec)->revision_id & 0xff00) >= 0x0300)
2948 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
2949
2950 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
2951 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
2952 #define ATI_VERB_SET_DOWNMIX_INFO 0x772
2953 #define ATI_VERB_SET_MULTICHANNEL_01 0x777
2954 #define ATI_VERB_SET_MULTICHANNEL_23 0x778
2955 #define ATI_VERB_SET_MULTICHANNEL_45 0x779
2956 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
2957 #define ATI_VERB_SET_HBR_CONTROL 0x77c
2958 #define ATI_VERB_SET_MULTICHANNEL_1 0x785
2959 #define ATI_VERB_SET_MULTICHANNEL_3 0x786
2960 #define ATI_VERB_SET_MULTICHANNEL_5 0x787
2961 #define ATI_VERB_SET_MULTICHANNEL_7 0x788
2962 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
2963 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
2964 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
2965 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
2966 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
2967 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
2968 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
2969 #define ATI_VERB_GET_HBR_CONTROL 0xf7c
2970 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
2971 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
2972 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
2973 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
2974 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
2975
2976 /* AMD specific HDA cvt verbs */
2977 #define ATI_VERB_SET_RAMP_RATE 0x770
2978 #define ATI_VERB_GET_RAMP_RATE 0xf70
2979
2980 #define ATI_OUT_ENABLE 0x1
2981
2982 #define ATI_MULTICHANNEL_MODE_PAIRED 0
2983 #define ATI_MULTICHANNEL_MODE_SINGLE 1
2984
2985 #define ATI_HBR_CAPABLE 0x01
2986 #define ATI_HBR_ENABLE 0x10
2987
atihdmi_pin_get_eld(struct hda_codec * codec,hda_nid_t nid,unsigned char * buf,int * eld_size)2988 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
2989 unsigned char *buf, int *eld_size)
2990 {
2991 /* call hda_eld.c ATI/AMD-specific function */
2992 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
2993 is_amdhdmi_rev3_or_later(codec));
2994 }
2995
atihdmi_pin_setup_infoframe(struct hda_codec * codec,hda_nid_t pin_nid,int ca,int active_channels,int conn_type)2996 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
2997 int active_channels, int conn_type)
2998 {
2999 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3000 }
3001
atihdmi_paired_swap_fc_lfe(int pos)3002 static int atihdmi_paired_swap_fc_lfe(int pos)
3003 {
3004 /*
3005 * ATI/AMD have automatic FC/LFE swap built-in
3006 * when in pairwise mapping mode.
3007 */
3008
3009 switch (pos) {
3010 /* see channel_allocations[].speakers[] */
3011 case 2: return 3;
3012 case 3: return 2;
3013 default: break;
3014 }
3015
3016 return pos;
3017 }
3018
atihdmi_paired_chmap_validate(int ca,int chs,unsigned char * map)3019 static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map)
3020 {
3021 struct cea_channel_speaker_allocation *cap;
3022 int i, j;
3023
3024 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3025
3026 cap = &channel_allocations[get_channel_allocation_order(ca)];
3027 for (i = 0; i < chs; ++i) {
3028 int mask = to_spk_mask(map[i]);
3029 bool ok = false;
3030 bool companion_ok = false;
3031
3032 if (!mask)
3033 continue;
3034
3035 for (j = 0 + i % 2; j < 8; j += 2) {
3036 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3037 if (cap->speakers[chan_idx] == mask) {
3038 /* channel is in a supported position */
3039 ok = true;
3040
3041 if (i % 2 == 0 && i + 1 < chs) {
3042 /* even channel, check the odd companion */
3043 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3044 int comp_mask_req = to_spk_mask(map[i+1]);
3045 int comp_mask_act = cap->speakers[comp_chan_idx];
3046
3047 if (comp_mask_req == comp_mask_act)
3048 companion_ok = true;
3049 else
3050 return -EINVAL;
3051 }
3052 break;
3053 }
3054 }
3055
3056 if (!ok)
3057 return -EINVAL;
3058
3059 if (companion_ok)
3060 i++; /* companion channel already checked */
3061 }
3062
3063 return 0;
3064 }
3065
atihdmi_pin_set_slot_channel(struct hda_codec * codec,hda_nid_t pin_nid,int hdmi_slot,int stream_channel)3066 static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3067 int hdmi_slot, int stream_channel)
3068 {
3069 int verb;
3070 int ati_channel_setup = 0;
3071
3072 if (hdmi_slot > 7)
3073 return -EINVAL;
3074
3075 if (!has_amd_full_remap_support(codec)) {
3076 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3077
3078 /* In case this is an odd slot but without stream channel, do not
3079 * disable the slot since the corresponding even slot could have a
3080 * channel. In case neither have a channel, the slot pair will be
3081 * disabled when this function is called for the even slot. */
3082 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3083 return 0;
3084
3085 hdmi_slot -= hdmi_slot % 2;
3086
3087 if (stream_channel != 0xf)
3088 stream_channel -= stream_channel % 2;
3089 }
3090
3091 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3092
3093 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3094
3095 if (stream_channel != 0xf)
3096 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3097
3098 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3099 }
3100
atihdmi_pin_get_slot_channel(struct hda_codec * codec,hda_nid_t pin_nid,int asp_slot)3101 static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3102 int asp_slot)
3103 {
3104 bool was_odd = false;
3105 int ati_asp_slot = asp_slot;
3106 int verb;
3107 int ati_channel_setup;
3108
3109 if (asp_slot > 7)
3110 return -EINVAL;
3111
3112 if (!has_amd_full_remap_support(codec)) {
3113 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3114 if (ati_asp_slot % 2 != 0) {
3115 ati_asp_slot -= 1;
3116 was_odd = true;
3117 }
3118 }
3119
3120 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3121
3122 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3123
3124 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3125 return 0xf;
3126
3127 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3128 }
3129
atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation * cap,int channels)3130 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
3131 int channels)
3132 {
3133 int c;
3134
3135 /*
3136 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3137 * we need to take that into account (a single channel may take 2
3138 * channel slots if we need to carry a silent channel next to it).
3139 * On Rev3+ AMD codecs this function is not used.
3140 */
3141 int chanpairs = 0;
3142
3143 /* We only produce even-numbered channel count TLVs */
3144 if ((channels % 2) != 0)
3145 return -1;
3146
3147 for (c = 0; c < 7; c += 2) {
3148 if (cap->speakers[c] || cap->speakers[c+1])
3149 chanpairs++;
3150 }
3151
3152 if (chanpairs * 2 != channels)
3153 return -1;
3154
3155 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3156 }
3157
atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation * cap,unsigned int * chmap,int channels)3158 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
3159 unsigned int *chmap, int channels)
3160 {
3161 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3162 int count = 0;
3163 int c;
3164
3165 for (c = 7; c >= 0; c--) {
3166 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3167 int spk = cap->speakers[chan];
3168 if (!spk) {
3169 /* add N/A channel if the companion channel is occupied */
3170 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3171 chmap[count++] = SNDRV_CHMAP_NA;
3172
3173 continue;
3174 }
3175
3176 chmap[count++] = spk_to_chmap(spk);
3177 }
3178
3179 WARN_ON(count != channels);
3180 }
3181
atihdmi_pin_hbr_setup(struct hda_codec * codec,hda_nid_t pin_nid,bool hbr)3182 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3183 bool hbr)
3184 {
3185 int hbr_ctl, hbr_ctl_new;
3186
3187 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3188 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3189 if (hbr)
3190 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3191 else
3192 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3193
3194 codec_dbg(codec,
3195 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3196 pin_nid,
3197 hbr_ctl == hbr_ctl_new ? "" : "new-",
3198 hbr_ctl_new);
3199
3200 if (hbr_ctl != hbr_ctl_new)
3201 snd_hda_codec_write(codec, pin_nid, 0,
3202 ATI_VERB_SET_HBR_CONTROL,
3203 hbr_ctl_new);
3204
3205 } else if (hbr)
3206 return -EINVAL;
3207
3208 return 0;
3209 }
3210
atihdmi_setup_stream(struct hda_codec * codec,hda_nid_t cvt_nid,hda_nid_t pin_nid,u32 stream_tag,int format)3211 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3212 hda_nid_t pin_nid, u32 stream_tag, int format)
3213 {
3214
3215 if (is_amdhdmi_rev3_or_later(codec)) {
3216 int ramp_rate = 180; /* default as per AMD spec */
3217 /* disable ramp-up/down for non-pcm as per AMD spec */
3218 if (format & AC_FMT_TYPE_NON_PCM)
3219 ramp_rate = 0;
3220
3221 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3222 }
3223
3224 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3225 }
3226
3227
atihdmi_init(struct hda_codec * codec)3228 static int atihdmi_init(struct hda_codec *codec)
3229 {
3230 struct hdmi_spec *spec = codec->spec;
3231 int pin_idx, err;
3232
3233 err = generic_hdmi_init(codec);
3234
3235 if (err)
3236 return err;
3237
3238 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3239 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3240
3241 /* make sure downmix information in infoframe is zero */
3242 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3243
3244 /* enable channel-wise remap mode if supported */
3245 if (has_amd_full_remap_support(codec))
3246 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3247 ATI_VERB_SET_MULTICHANNEL_MODE,
3248 ATI_MULTICHANNEL_MODE_SINGLE);
3249 }
3250
3251 return 0;
3252 }
3253
patch_atihdmi(struct hda_codec * codec)3254 static int patch_atihdmi(struct hda_codec *codec)
3255 {
3256 struct hdmi_spec *spec;
3257 struct hdmi_spec_per_cvt *per_cvt;
3258 int err, cvt_idx;
3259
3260 err = patch_generic_hdmi(codec);
3261
3262 if (err)
3263 return err;
3264
3265 codec->patch_ops.init = atihdmi_init;
3266
3267 spec = codec->spec;
3268
3269 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3270 spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3271 spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3272 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3273 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3274 spec->ops.setup_stream = atihdmi_setup_stream;
3275
3276 if (!has_amd_full_remap_support(codec)) {
3277 /* override to ATI/AMD-specific versions with pairwise mapping */
3278 spec->ops.chmap_cea_alloc_validate_get_type =
3279 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3280 spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap;
3281 spec->ops.chmap_validate = atihdmi_paired_chmap_validate;
3282 }
3283
3284 /* ATI/AMD converters do not advertise all of their capabilities */
3285 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3286 per_cvt = get_cvt(spec, cvt_idx);
3287 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3288 per_cvt->rates |= SUPPORTED_RATES;
3289 per_cvt->formats |= SUPPORTED_FORMATS;
3290 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3291 }
3292
3293 spec->channels_max = max(spec->channels_max, 8u);
3294
3295 return 0;
3296 }
3297
3298 /* VIA HDMI Implementation */
3299 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3300 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3301
patch_via_hdmi(struct hda_codec * codec)3302 static int patch_via_hdmi(struct hda_codec *codec)
3303 {
3304 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3305 }
3306
3307 /*
3308 * called from hda_codec.c for generic HDMI support
3309 */
snd_hda_parse_hdmi_codec(struct hda_codec * codec)3310 int snd_hda_parse_hdmi_codec(struct hda_codec *codec)
3311 {
3312 return patch_generic_hdmi(codec);
3313 }
3314 EXPORT_SYMBOL_GPL(snd_hda_parse_hdmi_codec);
3315
3316 /*
3317 * patch entries
3318 */
3319 static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
3320 { .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
3321 { .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
3322 { .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
3323 { .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_atihdmi },
3324 { .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
3325 { .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
3326 { .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
3327 { .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3328 { .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3329 { .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3330 { .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3331 { .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
3332 { .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_nvhdmi },
3333 { .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_nvhdmi },
3334 { .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_nvhdmi },
3335 { .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_nvhdmi },
3336 { .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_nvhdmi },
3337 { .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_nvhdmi },
3338 { .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_nvhdmi },
3339 { .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_nvhdmi },
3340 { .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_nvhdmi },
3341 { .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_nvhdmi },
3342 { .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_nvhdmi },
3343 /* 17 is known to be absent */
3344 { .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_nvhdmi },
3345 { .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_nvhdmi },
3346 { .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_nvhdmi },
3347 { .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_nvhdmi },
3348 { .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_nvhdmi },
3349 { .id = 0x10de0028, .name = "Tegra12x HDMI", .patch = patch_nvhdmi },
3350 { .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_nvhdmi },
3351 { .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_nvhdmi },
3352 { .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_nvhdmi },
3353 { .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_nvhdmi },
3354 { .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_nvhdmi },
3355 { .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_nvhdmi },
3356 { .id = 0x10de0060, .name = "GPU 60 HDMI/DP", .patch = patch_nvhdmi },
3357 { .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
3358 { .id = 0x10de0070, .name = "GPU 70 HDMI/DP", .patch = patch_nvhdmi },
3359 { .id = 0x10de0071, .name = "GPU 71 HDMI/DP", .patch = patch_nvhdmi },
3360 { .id = 0x10de0072, .name = "GPU 72 HDMI/DP", .patch = patch_nvhdmi },
3361 { .id = 0x10de007d, .name = "GPU 7d HDMI/DP", .patch = patch_nvhdmi },
3362 { .id = 0x10de0082, .name = "GPU 82 HDMI/DP", .patch = patch_nvhdmi },
3363 { .id = 0x10de0083, .name = "GPU 83 HDMI/DP", .patch = patch_nvhdmi },
3364 { .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
3365 { .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
3366 { .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
3367 { .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
3368 { .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
3369 { .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
3370 { .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
3371 { .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
3372 { .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
3373 { .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
3374 { .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
3375 { .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
3376 { .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi },
3377 { .id = 0x80862808, .name = "Broadwell HDMI", .patch = patch_generic_hdmi },
3378 { .id = 0x80862809, .name = "Skylake HDMI", .patch = patch_generic_hdmi },
3379 { .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
3380 { .id = 0x80862882, .name = "Valleyview2 HDMI", .patch = patch_generic_hdmi },
3381 { .id = 0x80862883, .name = "Braswell HDMI", .patch = patch_generic_hdmi },
3382 { .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
3383 {} /* terminator */
3384 };
3385
3386 MODULE_ALIAS("snd-hda-codec-id:1002793c");
3387 MODULE_ALIAS("snd-hda-codec-id:10027919");
3388 MODULE_ALIAS("snd-hda-codec-id:1002791a");
3389 MODULE_ALIAS("snd-hda-codec-id:1002aa01");
3390 MODULE_ALIAS("snd-hda-codec-id:10951390");
3391 MODULE_ALIAS("snd-hda-codec-id:10951392");
3392 MODULE_ALIAS("snd-hda-codec-id:10de0002");
3393 MODULE_ALIAS("snd-hda-codec-id:10de0003");
3394 MODULE_ALIAS("snd-hda-codec-id:10de0005");
3395 MODULE_ALIAS("snd-hda-codec-id:10de0006");
3396 MODULE_ALIAS("snd-hda-codec-id:10de0007");
3397 MODULE_ALIAS("snd-hda-codec-id:10de000a");
3398 MODULE_ALIAS("snd-hda-codec-id:10de000b");
3399 MODULE_ALIAS("snd-hda-codec-id:10de000c");
3400 MODULE_ALIAS("snd-hda-codec-id:10de000d");
3401 MODULE_ALIAS("snd-hda-codec-id:10de0010");
3402 MODULE_ALIAS("snd-hda-codec-id:10de0011");
3403 MODULE_ALIAS("snd-hda-codec-id:10de0012");
3404 MODULE_ALIAS("snd-hda-codec-id:10de0013");
3405 MODULE_ALIAS("snd-hda-codec-id:10de0014");
3406 MODULE_ALIAS("snd-hda-codec-id:10de0015");
3407 MODULE_ALIAS("snd-hda-codec-id:10de0016");
3408 MODULE_ALIAS("snd-hda-codec-id:10de0018");
3409 MODULE_ALIAS("snd-hda-codec-id:10de0019");
3410 MODULE_ALIAS("snd-hda-codec-id:10de001a");
3411 MODULE_ALIAS("snd-hda-codec-id:10de001b");
3412 MODULE_ALIAS("snd-hda-codec-id:10de001c");
3413 MODULE_ALIAS("snd-hda-codec-id:10de0028");
3414 MODULE_ALIAS("snd-hda-codec-id:10de0040");
3415 MODULE_ALIAS("snd-hda-codec-id:10de0041");
3416 MODULE_ALIAS("snd-hda-codec-id:10de0042");
3417 MODULE_ALIAS("snd-hda-codec-id:10de0043");
3418 MODULE_ALIAS("snd-hda-codec-id:10de0044");
3419 MODULE_ALIAS("snd-hda-codec-id:10de0051");
3420 MODULE_ALIAS("snd-hda-codec-id:10de0060");
3421 MODULE_ALIAS("snd-hda-codec-id:10de0067");
3422 MODULE_ALIAS("snd-hda-codec-id:10de0070");
3423 MODULE_ALIAS("snd-hda-codec-id:10de0071");
3424 MODULE_ALIAS("snd-hda-codec-id:10de0072");
3425 MODULE_ALIAS("snd-hda-codec-id:10de007d");
3426 MODULE_ALIAS("snd-hda-codec-id:10de8001");
3427 MODULE_ALIAS("snd-hda-codec-id:11069f80");
3428 MODULE_ALIAS("snd-hda-codec-id:11069f81");
3429 MODULE_ALIAS("snd-hda-codec-id:11069f84");
3430 MODULE_ALIAS("snd-hda-codec-id:11069f85");
3431 MODULE_ALIAS("snd-hda-codec-id:17e80047");
3432 MODULE_ALIAS("snd-hda-codec-id:80860054");
3433 MODULE_ALIAS("snd-hda-codec-id:80862801");
3434 MODULE_ALIAS("snd-hda-codec-id:80862802");
3435 MODULE_ALIAS("snd-hda-codec-id:80862803");
3436 MODULE_ALIAS("snd-hda-codec-id:80862804");
3437 MODULE_ALIAS("snd-hda-codec-id:80862805");
3438 MODULE_ALIAS("snd-hda-codec-id:80862806");
3439 MODULE_ALIAS("snd-hda-codec-id:80862807");
3440 MODULE_ALIAS("snd-hda-codec-id:80862808");
3441 MODULE_ALIAS("snd-hda-codec-id:80862809");
3442 MODULE_ALIAS("snd-hda-codec-id:80862880");
3443 MODULE_ALIAS("snd-hda-codec-id:80862882");
3444 MODULE_ALIAS("snd-hda-codec-id:80862883");
3445 MODULE_ALIAS("snd-hda-codec-id:808629fb");
3446
3447 MODULE_LICENSE("GPL");
3448 MODULE_DESCRIPTION("HDMI HD-audio codec");
3449 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3450 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3451 MODULE_ALIAS("snd-hda-codec-atihdmi");
3452
3453 static struct hda_codec_preset_list intel_list = {
3454 .preset = snd_hda_preset_hdmi,
3455 .owner = THIS_MODULE,
3456 };
3457
patch_hdmi_init(void)3458 static int __init patch_hdmi_init(void)
3459 {
3460 return snd_hda_add_codec_preset(&intel_list);
3461 }
3462
patch_hdmi_exit(void)3463 static void __exit patch_hdmi_exit(void)
3464 {
3465 snd_hda_delete_codec_preset(&intel_list);
3466 }
3467
3468 module_init(patch_hdmi_init)
3469 module_exit(patch_hdmi_exit)
3470