1 /*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/of.h>
27 #include <linux/of_platform.h>
28 #include <linux/of_device.h>
29
30 #include <sound/asoundef.h>
31 #include <sound/core.h>
32 #include <sound/pcm.h>
33 #include <sound/pcm_params.h>
34 #include <sound/initval.h>
35 #include <sound/soc.h>
36 #include <sound/dmaengine_pcm.h>
37 #include <sound/omap-pcm.h>
38
39 #include "davinci-pcm.h"
40 #include "edma-pcm.h"
41 #include "davinci-mcasp.h"
42
43 #define MCASP_MAX_AFIFO_DEPTH 64
44
45 static u32 context_regs[] = {
46 DAVINCI_MCASP_TXFMCTL_REG,
47 DAVINCI_MCASP_RXFMCTL_REG,
48 DAVINCI_MCASP_TXFMT_REG,
49 DAVINCI_MCASP_RXFMT_REG,
50 DAVINCI_MCASP_ACLKXCTL_REG,
51 DAVINCI_MCASP_ACLKRCTL_REG,
52 DAVINCI_MCASP_AHCLKXCTL_REG,
53 DAVINCI_MCASP_AHCLKRCTL_REG,
54 DAVINCI_MCASP_PDIR_REG,
55 DAVINCI_MCASP_RXMASK_REG,
56 DAVINCI_MCASP_TXMASK_REG,
57 DAVINCI_MCASP_RXTDM_REG,
58 DAVINCI_MCASP_TXTDM_REG,
59 };
60
61 struct davinci_mcasp_context {
62 u32 config_regs[ARRAY_SIZE(context_regs)];
63 u32 afifo_regs[2]; /* for read/write fifo control registers */
64 u32 *xrsr_regs; /* for serializer configuration */
65 };
66
67 struct davinci_mcasp {
68 struct davinci_pcm_dma_params dma_params[2];
69 struct snd_dmaengine_dai_dma_data dma_data[2];
70 void __iomem *base;
71 u32 fifo_base;
72 struct device *dev;
73
74 /* McASP specific data */
75 int tdm_slots;
76 u8 op_mode;
77 u8 num_serializer;
78 u8 *serial_dir;
79 u8 version;
80 u8 bclk_div;
81 u16 bclk_lrclk_ratio;
82 int streams;
83
84 int sysclk_freq;
85 bool bclk_master;
86
87 /* McASP FIFO related */
88 u8 txnumevt;
89 u8 rxnumevt;
90
91 bool dat_port;
92
93 #ifdef CONFIG_PM_SLEEP
94 struct davinci_mcasp_context context;
95 #endif
96 };
97
mcasp_set_bits(struct davinci_mcasp * mcasp,u32 offset,u32 val)98 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
99 u32 val)
100 {
101 void __iomem *reg = mcasp->base + offset;
102 __raw_writel(__raw_readl(reg) | val, reg);
103 }
104
mcasp_clr_bits(struct davinci_mcasp * mcasp,u32 offset,u32 val)105 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
106 u32 val)
107 {
108 void __iomem *reg = mcasp->base + offset;
109 __raw_writel((__raw_readl(reg) & ~(val)), reg);
110 }
111
mcasp_mod_bits(struct davinci_mcasp * mcasp,u32 offset,u32 val,u32 mask)112 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
113 u32 val, u32 mask)
114 {
115 void __iomem *reg = mcasp->base + offset;
116 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
117 }
118
mcasp_set_reg(struct davinci_mcasp * mcasp,u32 offset,u32 val)119 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
120 u32 val)
121 {
122 __raw_writel(val, mcasp->base + offset);
123 }
124
mcasp_get_reg(struct davinci_mcasp * mcasp,u32 offset)125 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
126 {
127 return (u32)__raw_readl(mcasp->base + offset);
128 }
129
mcasp_set_ctl_reg(struct davinci_mcasp * mcasp,u32 ctl_reg,u32 val)130 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
131 {
132 int i = 0;
133
134 mcasp_set_bits(mcasp, ctl_reg, val);
135
136 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
137 /* loop count is to avoid the lock-up */
138 for (i = 0; i < 1000; i++) {
139 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
140 break;
141 }
142
143 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
144 printk(KERN_ERR "GBLCTL write error\n");
145 }
146
mcasp_is_synchronous(struct davinci_mcasp * mcasp)147 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
148 {
149 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
150 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
151
152 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
153 }
154
mcasp_start_rx(struct davinci_mcasp * mcasp)155 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
156 {
157 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
158 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
159
160 /*
161 * When ASYNC == 0 the transmit and receive sections operate
162 * synchronously from the transmit clock and frame sync. We need to make
163 * sure that the TX signlas are enabled when starting reception.
164 */
165 if (mcasp_is_synchronous(mcasp)) {
166 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
167 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
168 }
169
170 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
171 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
172
173 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
174 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
175 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
176
177 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
178 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
179
180 if (mcasp_is_synchronous(mcasp))
181 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
182 }
183
mcasp_start_tx(struct davinci_mcasp * mcasp)184 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
185 {
186 u8 offset = 0, i;
187 u32 cnt;
188
189 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
190 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
191 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
192 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
193
194 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
195 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
196 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
197 for (i = 0; i < mcasp->num_serializer; i++) {
198 if (mcasp->serial_dir[i] == TX_MODE) {
199 offset = i;
200 break;
201 }
202 }
203
204 /* wait for TX ready */
205 cnt = 0;
206 while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(offset)) &
207 TXSTATE) && (cnt < 100000))
208 cnt++;
209
210 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
211 }
212
davinci_mcasp_start(struct davinci_mcasp * mcasp,int stream)213 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
214 {
215 u32 reg;
216
217 mcasp->streams++;
218
219 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
220 if (mcasp->txnumevt) { /* enable FIFO */
221 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
222 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
223 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
224 }
225 mcasp_start_tx(mcasp);
226 } else {
227 if (mcasp->rxnumevt) { /* enable FIFO */
228 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
229 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
230 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
231 }
232 mcasp_start_rx(mcasp);
233 }
234 }
235
mcasp_stop_rx(struct davinci_mcasp * mcasp)236 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
237 {
238 /*
239 * In synchronous mode stop the TX clocks if no other stream is
240 * running
241 */
242 if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
243 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
244
245 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
246 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
247 }
248
mcasp_stop_tx(struct davinci_mcasp * mcasp)249 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
250 {
251 u32 val = 0;
252
253 /*
254 * In synchronous mode keep TX clocks running if the capture stream is
255 * still running.
256 */
257 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
258 val = TXHCLKRST | TXCLKRST | TXFSRST;
259
260 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
261 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
262 }
263
davinci_mcasp_stop(struct davinci_mcasp * mcasp,int stream)264 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
265 {
266 u32 reg;
267
268 mcasp->streams--;
269
270 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
271 if (mcasp->txnumevt) { /* disable FIFO */
272 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
273 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
274 }
275 mcasp_stop_tx(mcasp);
276 } else {
277 if (mcasp->rxnumevt) { /* disable FIFO */
278 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
279 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
280 }
281 mcasp_stop_rx(mcasp);
282 }
283 }
284
davinci_mcasp_set_dai_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)285 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
286 unsigned int fmt)
287 {
288 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
289 int ret = 0;
290 u32 data_delay;
291 bool fs_pol_rising;
292 bool inv_fs = false;
293
294 pm_runtime_get_sync(mcasp->dev);
295 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
296 case SND_SOC_DAIFMT_DSP_A:
297 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
298 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
299 /* 1st data bit occur one ACLK cycle after the frame sync */
300 data_delay = 1;
301 break;
302 case SND_SOC_DAIFMT_DSP_B:
303 case SND_SOC_DAIFMT_AC97:
304 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
305 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
306 /* No delay after FS */
307 data_delay = 0;
308 break;
309 case SND_SOC_DAIFMT_I2S:
310 /* configure a full-word SYNC pulse (LRCLK) */
311 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
312 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
313 /* 1st data bit occur one ACLK cycle after the frame sync */
314 data_delay = 1;
315 /* FS need to be inverted */
316 inv_fs = true;
317 break;
318 case SND_SOC_DAIFMT_LEFT_J:
319 /* configure a full-word SYNC pulse (LRCLK) */
320 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
321 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
322 /* No delay after FS */
323 data_delay = 0;
324 break;
325 default:
326 ret = -EINVAL;
327 goto out;
328 }
329
330 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
331 FSXDLY(3));
332 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
333 FSRDLY(3));
334
335 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
336 case SND_SOC_DAIFMT_CBS_CFS:
337 /* codec is clock and frame slave */
338 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
339 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
340
341 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
342 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
343
344 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
345 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
346 mcasp->bclk_master = 1;
347 break;
348 case SND_SOC_DAIFMT_CBM_CFS:
349 /* codec is clock master and frame slave */
350 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
351 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
352
353 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
354 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
355
356 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
357 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
358 mcasp->bclk_master = 0;
359 break;
360 case SND_SOC_DAIFMT_CBM_CFM:
361 /* codec is clock and frame master */
362 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
363 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
364
365 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
366 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
367
368 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
369 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
370 mcasp->bclk_master = 0;
371 break;
372 default:
373 ret = -EINVAL;
374 goto out;
375 }
376
377 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
378 case SND_SOC_DAIFMT_IB_NF:
379 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
380 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
381 fs_pol_rising = true;
382 break;
383 case SND_SOC_DAIFMT_NB_IF:
384 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
385 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
386 fs_pol_rising = false;
387 break;
388 case SND_SOC_DAIFMT_IB_IF:
389 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
390 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
391 fs_pol_rising = false;
392 break;
393 case SND_SOC_DAIFMT_NB_NF:
394 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
395 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
396 fs_pol_rising = true;
397 break;
398 default:
399 ret = -EINVAL;
400 goto out;
401 }
402
403 if (inv_fs)
404 fs_pol_rising = !fs_pol_rising;
405
406 if (fs_pol_rising) {
407 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
408 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
409 } else {
410 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
411 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
412 }
413 out:
414 pm_runtime_put_sync(mcasp->dev);
415 return ret;
416 }
417
__davinci_mcasp_set_clkdiv(struct snd_soc_dai * dai,int div_id,int div,bool explicit)418 static int __davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
419 int div, bool explicit)
420 {
421 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
422
423 switch (div_id) {
424 case 0: /* MCLK divider */
425 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
426 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
427 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
428 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
429 break;
430
431 case 1: /* BCLK divider */
432 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
433 ACLKXDIV(div - 1), ACLKXDIV_MASK);
434 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
435 ACLKRDIV(div - 1), ACLKRDIV_MASK);
436 if (explicit)
437 mcasp->bclk_div = div;
438 break;
439
440 case 2: /* BCLK/LRCLK ratio */
441 mcasp->bclk_lrclk_ratio = div;
442 break;
443
444 default:
445 return -EINVAL;
446 }
447
448 return 0;
449 }
450
davinci_mcasp_set_clkdiv(struct snd_soc_dai * dai,int div_id,int div)451 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
452 int div)
453 {
454 return __davinci_mcasp_set_clkdiv(dai, div_id, div, 1);
455 }
456
davinci_mcasp_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)457 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
458 unsigned int freq, int dir)
459 {
460 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
461
462 if (dir == SND_SOC_CLOCK_OUT) {
463 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
464 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
465 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
466 } else {
467 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
468 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
469 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
470 }
471
472 mcasp->sysclk_freq = freq;
473
474 return 0;
475 }
476
davinci_config_channel_size(struct davinci_mcasp * mcasp,int word_length)477 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
478 int word_length)
479 {
480 u32 fmt;
481 u32 tx_rotate = (word_length / 4) & 0x7;
482 u32 mask = (1ULL << word_length) - 1;
483 /*
484 * For captured data we should not rotate, inversion and masking is
485 * enoguh to get the data to the right position:
486 * Format data from bus after reverse (XRBUF)
487 * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB|
488 * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
489 * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
490 * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB|
491 */
492 u32 rx_rotate = 0;
493
494 /*
495 * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
496 * callback, take it into account here. That allows us to for example
497 * send 32 bits per channel to the codec, while only 16 of them carry
498 * audio payload.
499 * The clock ratio is given for a full period of data (for I2S format
500 * both left and right channels), so it has to be divided by number of
501 * tdm-slots (for I2S - divided by 2).
502 */
503 if (mcasp->bclk_lrclk_ratio)
504 word_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots;
505
506 /* mapping of the XSSZ bit-field as described in the datasheet */
507 fmt = (word_length >> 1) - 1;
508
509 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
510 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
511 RXSSZ(0x0F));
512 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
513 TXSSZ(0x0F));
514 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
515 TXROT(7));
516 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
517 RXROT(7));
518 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
519 }
520
521 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
522
523 return 0;
524 }
525
mcasp_common_hw_param(struct davinci_mcasp * mcasp,int stream,int period_words,int channels)526 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
527 int period_words, int channels)
528 {
529 struct davinci_pcm_dma_params *dma_params = &mcasp->dma_params[stream];
530 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
531 int i;
532 u8 tx_ser = 0;
533 u8 rx_ser = 0;
534 u8 slots = mcasp->tdm_slots;
535 u8 max_active_serializers = (channels + slots - 1) / slots;
536 int active_serializers, numevt, n;
537 u32 reg;
538 /* Default configuration */
539 if (mcasp->version < MCASP_VERSION_3)
540 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
541
542 /* All PINS as McASP */
543 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
544
545 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
546 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
547 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
548 } else {
549 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
550 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
551 }
552
553 for (i = 0; i < mcasp->num_serializer; i++) {
554 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
555 mcasp->serial_dir[i]);
556 if (mcasp->serial_dir[i] == TX_MODE &&
557 tx_ser < max_active_serializers) {
558 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
559 tx_ser++;
560 } else if (mcasp->serial_dir[i] == RX_MODE &&
561 rx_ser < max_active_serializers) {
562 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
563 rx_ser++;
564 } else {
565 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
566 SRMOD_INACTIVE, SRMOD_MASK);
567 }
568 }
569
570 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
571 active_serializers = tx_ser;
572 numevt = mcasp->txnumevt;
573 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
574 } else {
575 active_serializers = rx_ser;
576 numevt = mcasp->rxnumevt;
577 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
578 }
579
580 if (active_serializers < max_active_serializers) {
581 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
582 "enabled in mcasp (%d)\n", channels,
583 active_serializers * slots);
584 return -EINVAL;
585 }
586
587 /* AFIFO is not in use */
588 if (!numevt) {
589 /* Configure the burst size for platform drivers */
590 if (active_serializers > 1) {
591 /*
592 * If more than one serializers are in use we have one
593 * DMA request to provide data for all serializers.
594 * For example if three serializers are enabled the DMA
595 * need to transfer three words per DMA request.
596 */
597 dma_params->fifo_level = active_serializers;
598 dma_data->maxburst = active_serializers;
599 } else {
600 dma_params->fifo_level = 0;
601 dma_data->maxburst = 0;
602 }
603 return 0;
604 }
605
606 if (period_words % active_serializers) {
607 dev_err(mcasp->dev, "Invalid combination of period words and "
608 "active serializers: %d, %d\n", period_words,
609 active_serializers);
610 return -EINVAL;
611 }
612
613 /*
614 * Calculate the optimal AFIFO depth for platform side:
615 * The number of words for numevt need to be in steps of active
616 * serializers.
617 */
618 n = numevt % active_serializers;
619 if (n)
620 numevt += (active_serializers - n);
621 while (period_words % numevt && numevt > 0)
622 numevt -= active_serializers;
623 if (numevt <= 0)
624 numevt = active_serializers;
625
626 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
627 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
628
629 /* Configure the burst size for platform drivers */
630 if (numevt == 1)
631 numevt = 0;
632 dma_params->fifo_level = numevt;
633 dma_data->maxburst = numevt;
634
635 return 0;
636 }
637
mcasp_i2s_hw_param(struct davinci_mcasp * mcasp,int stream)638 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream)
639 {
640 int i, active_slots;
641 u32 mask = 0;
642 u32 busel = 0;
643
644 if ((mcasp->tdm_slots < 2) || (mcasp->tdm_slots > 32)) {
645 dev_err(mcasp->dev, "tdm slot %d not supported\n",
646 mcasp->tdm_slots);
647 return -EINVAL;
648 }
649
650 active_slots = (mcasp->tdm_slots > 31) ? 32 : mcasp->tdm_slots;
651 for (i = 0; i < active_slots; i++)
652 mask |= (1 << i);
653
654 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
655
656 if (!mcasp->dat_port)
657 busel = TXSEL;
658
659 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
660 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
661 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
662 FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF));
663
664 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
665 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
666 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
667 FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF));
668
669 return 0;
670 }
671
672 /* S/PDIF */
mcasp_dit_hw_param(struct davinci_mcasp * mcasp,unsigned int rate)673 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
674 unsigned int rate)
675 {
676 u32 cs_value = 0;
677 u8 *cs_bytes = (u8*) &cs_value;
678
679 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
680 and LSB first */
681 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
682
683 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
684 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
685
686 /* Set the TX tdm : for all the slots */
687 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
688
689 /* Set the TX clock controls : div = 1 and internal */
690 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
691
692 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
693
694 /* Only 44100 and 48000 are valid, both have the same setting */
695 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
696
697 /* Enable the DIT */
698 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
699
700 /* Set S/PDIF channel status bits */
701 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
702 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
703
704 switch (rate) {
705 case 22050:
706 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
707 break;
708 case 24000:
709 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
710 break;
711 case 32000:
712 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
713 break;
714 case 44100:
715 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
716 break;
717 case 48000:
718 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
719 break;
720 case 88200:
721 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
722 break;
723 case 96000:
724 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
725 break;
726 case 176400:
727 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
728 break;
729 case 192000:
730 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
731 break;
732 default:
733 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
734 return -EINVAL;
735 }
736
737 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
738 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
739
740 return 0;
741 }
742
davinci_mcasp_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * cpu_dai)743 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
744 struct snd_pcm_hw_params *params,
745 struct snd_soc_dai *cpu_dai)
746 {
747 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
748 struct davinci_pcm_dma_params *dma_params =
749 &mcasp->dma_params[substream->stream];
750 int word_length;
751 int channels = params_channels(params);
752 int period_size = params_period_size(params);
753 int ret;
754
755 /*
756 * If mcasp is BCLK master, and a BCLK divider was not provided by
757 * the machine driver, we need to calculate the ratio.
758 */
759 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
760 unsigned int bclk_freq = snd_soc_params_to_bclk(params);
761 unsigned int div = mcasp->sysclk_freq / bclk_freq;
762 if (mcasp->sysclk_freq % bclk_freq != 0) {
763 if (((mcasp->sysclk_freq / div) - bclk_freq) >
764 (bclk_freq - (mcasp->sysclk_freq / (div+1))))
765 div++;
766 dev_warn(mcasp->dev,
767 "Inaccurate BCLK: %u Hz / %u != %u Hz\n",
768 mcasp->sysclk_freq, div, bclk_freq);
769 }
770 __davinci_mcasp_set_clkdiv(cpu_dai, 1, div, 0);
771 }
772
773 ret = mcasp_common_hw_param(mcasp, substream->stream,
774 period_size * channels, channels);
775 if (ret)
776 return ret;
777
778 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
779 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
780 else
781 ret = mcasp_i2s_hw_param(mcasp, substream->stream);
782
783 if (ret)
784 return ret;
785
786 switch (params_format(params)) {
787 case SNDRV_PCM_FORMAT_U8:
788 case SNDRV_PCM_FORMAT_S8:
789 dma_params->data_type = 1;
790 word_length = 8;
791 break;
792
793 case SNDRV_PCM_FORMAT_U16_LE:
794 case SNDRV_PCM_FORMAT_S16_LE:
795 dma_params->data_type = 2;
796 word_length = 16;
797 break;
798
799 case SNDRV_PCM_FORMAT_U24_3LE:
800 case SNDRV_PCM_FORMAT_S24_3LE:
801 dma_params->data_type = 3;
802 word_length = 24;
803 break;
804
805 case SNDRV_PCM_FORMAT_U24_LE:
806 case SNDRV_PCM_FORMAT_S24_LE:
807 dma_params->data_type = 4;
808 word_length = 24;
809 break;
810
811 case SNDRV_PCM_FORMAT_U32_LE:
812 case SNDRV_PCM_FORMAT_S32_LE:
813 dma_params->data_type = 4;
814 word_length = 32;
815 break;
816
817 default:
818 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
819 return -EINVAL;
820 }
821
822 if (mcasp->version == MCASP_VERSION_2 && !dma_params->fifo_level)
823 dma_params->acnt = 4;
824 else
825 dma_params->acnt = dma_params->data_type;
826
827 davinci_config_channel_size(mcasp, word_length);
828
829 return 0;
830 }
831
davinci_mcasp_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * cpu_dai)832 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
833 int cmd, struct snd_soc_dai *cpu_dai)
834 {
835 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
836 int ret = 0;
837
838 switch (cmd) {
839 case SNDRV_PCM_TRIGGER_RESUME:
840 case SNDRV_PCM_TRIGGER_START:
841 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
842 davinci_mcasp_start(mcasp, substream->stream);
843 break;
844 case SNDRV_PCM_TRIGGER_SUSPEND:
845 case SNDRV_PCM_TRIGGER_STOP:
846 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
847 davinci_mcasp_stop(mcasp, substream->stream);
848 break;
849
850 default:
851 ret = -EINVAL;
852 }
853
854 return ret;
855 }
856
857 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
858 .trigger = davinci_mcasp_trigger,
859 .hw_params = davinci_mcasp_hw_params,
860 .set_fmt = davinci_mcasp_set_dai_fmt,
861 .set_clkdiv = davinci_mcasp_set_clkdiv,
862 .set_sysclk = davinci_mcasp_set_sysclk,
863 };
864
davinci_mcasp_dai_probe(struct snd_soc_dai * dai)865 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
866 {
867 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
868
869 if (mcasp->version >= MCASP_VERSION_3) {
870 /* Using dmaengine PCM */
871 dai->playback_dma_data =
872 &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
873 dai->capture_dma_data =
874 &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
875 } else {
876 /* Using davinci-pcm */
877 dai->playback_dma_data = mcasp->dma_params;
878 dai->capture_dma_data = mcasp->dma_params;
879 }
880
881 return 0;
882 }
883
884 #ifdef CONFIG_PM_SLEEP
davinci_mcasp_suspend(struct snd_soc_dai * dai)885 static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
886 {
887 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
888 struct davinci_mcasp_context *context = &mcasp->context;
889 u32 reg;
890 int i;
891
892 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
893 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
894
895 if (mcasp->txnumevt) {
896 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
897 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
898 }
899 if (mcasp->rxnumevt) {
900 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
901 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
902 }
903
904 for (i = 0; i < mcasp->num_serializer; i++)
905 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
906 DAVINCI_MCASP_XRSRCTL_REG(i));
907
908 return 0;
909 }
910
davinci_mcasp_resume(struct snd_soc_dai * dai)911 static int davinci_mcasp_resume(struct snd_soc_dai *dai)
912 {
913 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
914 struct davinci_mcasp_context *context = &mcasp->context;
915 u32 reg;
916 int i;
917
918 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
919 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
920
921 if (mcasp->txnumevt) {
922 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
923 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
924 }
925 if (mcasp->rxnumevt) {
926 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
927 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
928 }
929
930 for (i = 0; i < mcasp->num_serializer; i++)
931 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
932 context->xrsr_regs[i]);
933
934 return 0;
935 }
936 #else
937 #define davinci_mcasp_suspend NULL
938 #define davinci_mcasp_resume NULL
939 #endif
940
941 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
942
943 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
944 SNDRV_PCM_FMTBIT_U8 | \
945 SNDRV_PCM_FMTBIT_S16_LE | \
946 SNDRV_PCM_FMTBIT_U16_LE | \
947 SNDRV_PCM_FMTBIT_S24_LE | \
948 SNDRV_PCM_FMTBIT_U24_LE | \
949 SNDRV_PCM_FMTBIT_S24_3LE | \
950 SNDRV_PCM_FMTBIT_U24_3LE | \
951 SNDRV_PCM_FMTBIT_S32_LE | \
952 SNDRV_PCM_FMTBIT_U32_LE)
953
954 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
955 {
956 .name = "davinci-mcasp.0",
957 .probe = davinci_mcasp_dai_probe,
958 .suspend = davinci_mcasp_suspend,
959 .resume = davinci_mcasp_resume,
960 .playback = {
961 .channels_min = 2,
962 .channels_max = 32 * 16,
963 .rates = DAVINCI_MCASP_RATES,
964 .formats = DAVINCI_MCASP_PCM_FMTS,
965 },
966 .capture = {
967 .channels_min = 2,
968 .channels_max = 32 * 16,
969 .rates = DAVINCI_MCASP_RATES,
970 .formats = DAVINCI_MCASP_PCM_FMTS,
971 },
972 .ops = &davinci_mcasp_dai_ops,
973
974 },
975 {
976 .name = "davinci-mcasp.1",
977 .probe = davinci_mcasp_dai_probe,
978 .playback = {
979 .channels_min = 1,
980 .channels_max = 384,
981 .rates = DAVINCI_MCASP_RATES,
982 .formats = DAVINCI_MCASP_PCM_FMTS,
983 },
984 .ops = &davinci_mcasp_dai_ops,
985 },
986
987 };
988
989 static const struct snd_soc_component_driver davinci_mcasp_component = {
990 .name = "davinci-mcasp",
991 };
992
993 /* Some HW specific values and defaults. The rest is filled in from DT. */
994 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
995 .tx_dma_offset = 0x400,
996 .rx_dma_offset = 0x400,
997 .asp_chan_q = EVENTQ_0,
998 .version = MCASP_VERSION_1,
999 };
1000
1001 static struct davinci_mcasp_pdata da830_mcasp_pdata = {
1002 .tx_dma_offset = 0x2000,
1003 .rx_dma_offset = 0x2000,
1004 .asp_chan_q = EVENTQ_0,
1005 .version = MCASP_VERSION_2,
1006 };
1007
1008 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
1009 .tx_dma_offset = 0,
1010 .rx_dma_offset = 0,
1011 .asp_chan_q = EVENTQ_0,
1012 .version = MCASP_VERSION_3,
1013 };
1014
1015 static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
1016 .tx_dma_offset = 0x200,
1017 .rx_dma_offset = 0x284,
1018 .asp_chan_q = EVENTQ_0,
1019 .version = MCASP_VERSION_4,
1020 };
1021
1022 static const struct of_device_id mcasp_dt_ids[] = {
1023 {
1024 .compatible = "ti,dm646x-mcasp-audio",
1025 .data = &dm646x_mcasp_pdata,
1026 },
1027 {
1028 .compatible = "ti,da830-mcasp-audio",
1029 .data = &da830_mcasp_pdata,
1030 },
1031 {
1032 .compatible = "ti,am33xx-mcasp-audio",
1033 .data = &am33xx_mcasp_pdata,
1034 },
1035 {
1036 .compatible = "ti,dra7-mcasp-audio",
1037 .data = &dra7_mcasp_pdata,
1038 },
1039 { /* sentinel */ }
1040 };
1041 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1042
mcasp_reparent_fck(struct platform_device * pdev)1043 static int mcasp_reparent_fck(struct platform_device *pdev)
1044 {
1045 struct device_node *node = pdev->dev.of_node;
1046 struct clk *gfclk, *parent_clk;
1047 const char *parent_name;
1048 int ret;
1049
1050 if (!node)
1051 return 0;
1052
1053 parent_name = of_get_property(node, "fck_parent", NULL);
1054 if (!parent_name)
1055 return 0;
1056
1057 gfclk = clk_get(&pdev->dev, "fck");
1058 if (IS_ERR(gfclk)) {
1059 dev_err(&pdev->dev, "failed to get fck\n");
1060 return PTR_ERR(gfclk);
1061 }
1062
1063 parent_clk = clk_get(NULL, parent_name);
1064 if (IS_ERR(parent_clk)) {
1065 dev_err(&pdev->dev, "failed to get parent clock\n");
1066 ret = PTR_ERR(parent_clk);
1067 goto err1;
1068 }
1069
1070 ret = clk_set_parent(gfclk, parent_clk);
1071 if (ret) {
1072 dev_err(&pdev->dev, "failed to reparent fck\n");
1073 goto err2;
1074 }
1075
1076 err2:
1077 clk_put(parent_clk);
1078 err1:
1079 clk_put(gfclk);
1080 return ret;
1081 }
1082
davinci_mcasp_set_pdata_from_of(struct platform_device * pdev)1083 static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
1084 struct platform_device *pdev)
1085 {
1086 struct device_node *np = pdev->dev.of_node;
1087 struct davinci_mcasp_pdata *pdata = NULL;
1088 const struct of_device_id *match =
1089 of_match_device(mcasp_dt_ids, &pdev->dev);
1090 struct of_phandle_args dma_spec;
1091
1092 const u32 *of_serial_dir32;
1093 u32 val;
1094 int i, ret = 0;
1095
1096 if (pdev->dev.platform_data) {
1097 pdata = pdev->dev.platform_data;
1098 return pdata;
1099 } else if (match) {
1100 pdata = (struct davinci_mcasp_pdata*) match->data;
1101 } else {
1102 /* control shouldn't reach here. something is wrong */
1103 ret = -EINVAL;
1104 goto nodata;
1105 }
1106
1107 ret = of_property_read_u32(np, "op-mode", &val);
1108 if (ret >= 0)
1109 pdata->op_mode = val;
1110
1111 ret = of_property_read_u32(np, "tdm-slots", &val);
1112 if (ret >= 0) {
1113 if (val < 2 || val > 32) {
1114 dev_err(&pdev->dev,
1115 "tdm-slots must be in rage [2-32]\n");
1116 ret = -EINVAL;
1117 goto nodata;
1118 }
1119
1120 pdata->tdm_slots = val;
1121 }
1122
1123 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1124 val /= sizeof(u32);
1125 if (of_serial_dir32) {
1126 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1127 (sizeof(*of_serial_dir) * val),
1128 GFP_KERNEL);
1129 if (!of_serial_dir) {
1130 ret = -ENOMEM;
1131 goto nodata;
1132 }
1133
1134 for (i = 0; i < val; i++)
1135 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1136
1137 pdata->num_serializer = val;
1138 pdata->serial_dir = of_serial_dir;
1139 }
1140
1141 ret = of_property_match_string(np, "dma-names", "tx");
1142 if (ret < 0)
1143 goto nodata;
1144
1145 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1146 &dma_spec);
1147 if (ret < 0)
1148 goto nodata;
1149
1150 pdata->tx_dma_channel = dma_spec.args[0];
1151
1152 ret = of_property_match_string(np, "dma-names", "rx");
1153 if (ret < 0)
1154 goto nodata;
1155
1156 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1157 &dma_spec);
1158 if (ret < 0)
1159 goto nodata;
1160
1161 pdata->rx_dma_channel = dma_spec.args[0];
1162
1163 ret = of_property_read_u32(np, "tx-num-evt", &val);
1164 if (ret >= 0)
1165 pdata->txnumevt = val;
1166
1167 ret = of_property_read_u32(np, "rx-num-evt", &val);
1168 if (ret >= 0)
1169 pdata->rxnumevt = val;
1170
1171 ret = of_property_read_u32(np, "sram-size-playback", &val);
1172 if (ret >= 0)
1173 pdata->sram_size_playback = val;
1174
1175 ret = of_property_read_u32(np, "sram-size-capture", &val);
1176 if (ret >= 0)
1177 pdata->sram_size_capture = val;
1178
1179 return pdata;
1180
1181 nodata:
1182 if (ret < 0) {
1183 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1184 ret);
1185 pdata = NULL;
1186 }
1187 return pdata;
1188 }
1189
davinci_mcasp_probe(struct platform_device * pdev)1190 static int davinci_mcasp_probe(struct platform_device *pdev)
1191 {
1192 struct davinci_pcm_dma_params *dma_params;
1193 struct snd_dmaengine_dai_dma_data *dma_data;
1194 struct resource *mem, *ioarea, *res, *dat;
1195 struct davinci_mcasp_pdata *pdata;
1196 struct davinci_mcasp *mcasp;
1197 int ret;
1198
1199 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1200 dev_err(&pdev->dev, "No platform data supplied\n");
1201 return -EINVAL;
1202 }
1203
1204 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
1205 GFP_KERNEL);
1206 if (!mcasp)
1207 return -ENOMEM;
1208
1209 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1210 if (!pdata) {
1211 dev_err(&pdev->dev, "no platform data\n");
1212 return -EINVAL;
1213 }
1214
1215 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1216 if (!mem) {
1217 dev_warn(mcasp->dev,
1218 "\"mpu\" mem resource not found, using index 0\n");
1219 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1220 if (!mem) {
1221 dev_err(&pdev->dev, "no mem resource?\n");
1222 return -ENODEV;
1223 }
1224 }
1225
1226 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
1227 resource_size(mem), pdev->name);
1228 if (!ioarea) {
1229 dev_err(&pdev->dev, "Audio region already claimed\n");
1230 return -EBUSY;
1231 }
1232
1233 pm_runtime_enable(&pdev->dev);
1234
1235 ret = pm_runtime_get_sync(&pdev->dev);
1236 if (IS_ERR_VALUE(ret)) {
1237 dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
1238 return ret;
1239 }
1240
1241 mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
1242 if (!mcasp->base) {
1243 dev_err(&pdev->dev, "ioremap failed\n");
1244 ret = -ENOMEM;
1245 goto err;
1246 }
1247
1248 mcasp->op_mode = pdata->op_mode;
1249 mcasp->tdm_slots = pdata->tdm_slots;
1250 mcasp->num_serializer = pdata->num_serializer;
1251 #ifdef CONFIG_PM_SLEEP
1252 mcasp->context.xrsr_regs = devm_kzalloc(&pdev->dev,
1253 sizeof(u32) * mcasp->num_serializer,
1254 GFP_KERNEL);
1255 #endif
1256 mcasp->serial_dir = pdata->serial_dir;
1257 mcasp->version = pdata->version;
1258 mcasp->txnumevt = pdata->txnumevt;
1259 mcasp->rxnumevt = pdata->rxnumevt;
1260
1261 mcasp->dev = &pdev->dev;
1262
1263 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
1264 if (dat)
1265 mcasp->dat_port = true;
1266
1267 dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
1268 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1269 dma_params->asp_chan_q = pdata->asp_chan_q;
1270 dma_params->ram_chan_q = pdata->ram_chan_q;
1271 dma_params->sram_pool = pdata->sram_pool;
1272 dma_params->sram_size = pdata->sram_size_playback;
1273 if (dat)
1274 dma_params->dma_addr = dat->start;
1275 else
1276 dma_params->dma_addr = mem->start + pdata->tx_dma_offset;
1277
1278 /* Unconditional dmaengine stuff */
1279 dma_data->addr = dma_params->dma_addr;
1280
1281 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1282 if (res)
1283 dma_params->channel = res->start;
1284 else
1285 dma_params->channel = pdata->tx_dma_channel;
1286
1287 /* dmaengine filter data for DT and non-DT boot */
1288 if (pdev->dev.of_node)
1289 dma_data->filter_data = "tx";
1290 else
1291 dma_data->filter_data = &dma_params->channel;
1292
1293 dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE];
1294 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1295 dma_params->asp_chan_q = pdata->asp_chan_q;
1296 dma_params->ram_chan_q = pdata->ram_chan_q;
1297 dma_params->sram_pool = pdata->sram_pool;
1298 dma_params->sram_size = pdata->sram_size_capture;
1299 if (dat)
1300 dma_params->dma_addr = dat->start;
1301 else
1302 dma_params->dma_addr = mem->start + pdata->rx_dma_offset;
1303
1304 /* Unconditional dmaengine stuff */
1305 dma_data->addr = dma_params->dma_addr;
1306
1307 if (mcasp->version < MCASP_VERSION_3) {
1308 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
1309 /* dma_params->dma_addr is pointing to the data port address */
1310 mcasp->dat_port = true;
1311 } else {
1312 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
1313 }
1314
1315 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1316 if (res)
1317 dma_params->channel = res->start;
1318 else
1319 dma_params->channel = pdata->rx_dma_channel;
1320
1321 /* dmaengine filter data for DT and non-DT boot */
1322 if (pdev->dev.of_node)
1323 dma_data->filter_data = "rx";
1324 else
1325 dma_data->filter_data = &dma_params->channel;
1326
1327 dev_set_drvdata(&pdev->dev, mcasp);
1328
1329 mcasp_reparent_fck(pdev);
1330
1331 ret = devm_snd_soc_register_component(&pdev->dev,
1332 &davinci_mcasp_component,
1333 &davinci_mcasp_dai[pdata->op_mode], 1);
1334
1335 if (ret != 0)
1336 goto err;
1337
1338 switch (mcasp->version) {
1339 #if IS_BUILTIN(CONFIG_SND_DAVINCI_SOC) || \
1340 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1341 IS_MODULE(CONFIG_SND_DAVINCI_SOC))
1342 case MCASP_VERSION_1:
1343 case MCASP_VERSION_2:
1344 ret = davinci_soc_platform_register(&pdev->dev);
1345 break;
1346 #endif
1347 #if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \
1348 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1349 IS_MODULE(CONFIG_SND_EDMA_SOC))
1350 case MCASP_VERSION_3:
1351 ret = edma_pcm_platform_register(&pdev->dev);
1352 break;
1353 #endif
1354 #if IS_BUILTIN(CONFIG_SND_OMAP_SOC) || \
1355 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1356 IS_MODULE(CONFIG_SND_OMAP_SOC))
1357 case MCASP_VERSION_4:
1358 ret = omap_pcm_platform_register(&pdev->dev);
1359 break;
1360 #endif
1361 default:
1362 dev_err(&pdev->dev, "Invalid McASP version: %d\n",
1363 mcasp->version);
1364 ret = -EINVAL;
1365 break;
1366 }
1367
1368 if (ret) {
1369 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1370 goto err;
1371 }
1372
1373 return 0;
1374
1375 err:
1376 pm_runtime_put_sync(&pdev->dev);
1377 pm_runtime_disable(&pdev->dev);
1378 return ret;
1379 }
1380
davinci_mcasp_remove(struct platform_device * pdev)1381 static int davinci_mcasp_remove(struct platform_device *pdev)
1382 {
1383 pm_runtime_put_sync(&pdev->dev);
1384 pm_runtime_disable(&pdev->dev);
1385
1386 return 0;
1387 }
1388
1389 static struct platform_driver davinci_mcasp_driver = {
1390 .probe = davinci_mcasp_probe,
1391 .remove = davinci_mcasp_remove,
1392 .driver = {
1393 .name = "davinci-mcasp",
1394 .owner = THIS_MODULE,
1395 .of_match_table = mcasp_dt_ids,
1396 },
1397 };
1398
1399 module_platform_driver(davinci_mcasp_driver);
1400
1401 MODULE_AUTHOR("Steve Chen");
1402 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1403 MODULE_LICENSE("GPL");
1404