1 /* 2 * Intel SST Haswell/Broadwell IPC Support 3 * 4 * Copyright (C) 2013, Intel Corporation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License version 8 * 2 as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 */ 16 17 #ifndef __SST_HASWELL_IPC_H 18 #define __SST_HASWELL_IPC_H 19 20 #include <linux/types.h> 21 #include <linux/kernel.h> 22 #include <linux/platform_device.h> 23 24 #define SST_HSW_NO_CHANNELS 2 25 #define SST_HSW_MAX_DX_REGIONS 14 26 27 #define SST_HSW_FW_LOG_CONFIG_DWORDS 12 28 #define SST_HSW_GLOBAL_LOG 15 29 30 /** 31 * Upfront defined maximum message size that is 32 * expected by the in/out communication pipes in FW. 33 */ 34 #define SST_HSW_IPC_MAX_PAYLOAD_SIZE 400 35 #define SST_HSW_MAX_INFO_SIZE 64 36 #define SST_HSW_BUILD_HASH_LENGTH 40 37 38 struct sst_hsw; 39 struct sst_hsw_stream; 40 struct sst_hsw_log_stream; 41 struct sst_pdata; 42 struct sst_module; 43 extern struct sst_ops haswell_ops; 44 45 /* Stream Allocate Path ID */ 46 enum sst_hsw_stream_path_id { 47 SST_HSW_STREAM_PATH_SSP0_OUT = 0, 48 SST_HSW_STREAM_PATH_SSP0_IN = 1, 49 SST_HSW_STREAM_PATH_MAX_PATH_ID = 2, 50 }; 51 52 /* Stream Allocate Stream Type */ 53 enum sst_hsw_stream_type { 54 SST_HSW_STREAM_TYPE_RENDER = 0, 55 SST_HSW_STREAM_TYPE_SYSTEM = 1, 56 SST_HSW_STREAM_TYPE_CAPTURE = 2, 57 SST_HSW_STREAM_TYPE_LOOPBACK = 3, 58 SST_HSW_STREAM_TYPE_MAX_STREAM_TYPE = 4, 59 }; 60 61 /* Stream Allocate Stream Format */ 62 enum sst_hsw_stream_format { 63 SST_HSW_STREAM_FORMAT_PCM_FORMAT = 0, 64 SST_HSW_STREAM_FORMAT_MP3_FORMAT = 1, 65 SST_HSW_STREAM_FORMAT_AAC_FORMAT = 2, 66 SST_HSW_STREAM_FORMAT_MAX_FORMAT_ID = 3, 67 }; 68 69 /* Device ID */ 70 enum sst_hsw_device_id { 71 SST_HSW_DEVICE_SSP_0 = 0, 72 SST_HSW_DEVICE_SSP_1 = 1, 73 }; 74 75 /* Device Master Clock Frequency */ 76 enum sst_hsw_device_mclk { 77 SST_HSW_DEVICE_MCLK_OFF = 0, 78 SST_HSW_DEVICE_MCLK_FREQ_6_MHZ = 1, 79 SST_HSW_DEVICE_MCLK_FREQ_12_MHZ = 2, 80 SST_HSW_DEVICE_MCLK_FREQ_24_MHZ = 3, 81 }; 82 83 /* Device Clock Master */ 84 enum sst_hsw_device_mode { 85 SST_HSW_DEVICE_CLOCK_SLAVE = 0, 86 SST_HSW_DEVICE_CLOCK_MASTER = 1, 87 }; 88 89 /* DX Power State */ 90 enum sst_hsw_dx_state { 91 SST_HSW_DX_STATE_D0 = 0, 92 SST_HSW_DX_STATE_D1 = 1, 93 SST_HSW_DX_STATE_D3 = 3, 94 SST_HSW_DX_STATE_MAX = 3, 95 }; 96 97 /* Audio stream stage IDs */ 98 enum sst_hsw_fx_stage_id { 99 SST_HSW_STAGE_ID_WAVES = 0, 100 SST_HSW_STAGE_ID_DTS = 1, 101 SST_HSW_STAGE_ID_DOLBY = 2, 102 SST_HSW_STAGE_ID_BOOST = 3, 103 SST_HSW_STAGE_ID_MAX_FX_ID 104 }; 105 106 /* DX State Type */ 107 enum sst_hsw_dx_type { 108 SST_HSW_DX_TYPE_FW_IMAGE = 0, 109 SST_HSW_DX_TYPE_MEMORY_DUMP = 1 110 }; 111 112 /* Volume Curve Type*/ 113 enum sst_hsw_volume_curve { 114 SST_HSW_VOLUME_CURVE_NONE = 0, 115 SST_HSW_VOLUME_CURVE_FADE = 1 116 }; 117 118 /* Sample ordering */ 119 enum sst_hsw_interleaving { 120 SST_HSW_INTERLEAVING_PER_CHANNEL = 0, 121 SST_HSW_INTERLEAVING_PER_SAMPLE = 1, 122 }; 123 124 /* Channel indices */ 125 enum sst_hsw_channel_index { 126 SST_HSW_CHANNEL_LEFT = 0, 127 SST_HSW_CHANNEL_CENTER = 1, 128 SST_HSW_CHANNEL_RIGHT = 2, 129 SST_HSW_CHANNEL_LEFT_SURROUND = 3, 130 SST_HSW_CHANNEL_CENTER_SURROUND = 3, 131 SST_HSW_CHANNEL_RIGHT_SURROUND = 4, 132 SST_HSW_CHANNEL_LFE = 7, 133 SST_HSW_CHANNEL_INVALID = 0xF, 134 }; 135 136 /* List of supported channel maps. */ 137 enum sst_hsw_channel_config { 138 SST_HSW_CHANNEL_CONFIG_MONO = 0, /* mono only. */ 139 SST_HSW_CHANNEL_CONFIG_STEREO = 1, /* L & R. */ 140 SST_HSW_CHANNEL_CONFIG_2_POINT_1 = 2, /* L, R & LFE; PCM only. */ 141 SST_HSW_CHANNEL_CONFIG_3_POINT_0 = 3, /* L, C & R; MP3 & AAC only. */ 142 SST_HSW_CHANNEL_CONFIG_3_POINT_1 = 4, /* L, C, R & LFE; PCM only. */ 143 SST_HSW_CHANNEL_CONFIG_QUATRO = 5, /* L, R, Ls & Rs; PCM only. */ 144 SST_HSW_CHANNEL_CONFIG_4_POINT_0 = 6, /* L, C, R & Cs; MP3 & AAC only. */ 145 SST_HSW_CHANNEL_CONFIG_5_POINT_0 = 7, /* L, C, R, Ls & Rs. */ 146 SST_HSW_CHANNEL_CONFIG_5_POINT_1 = 8, /* L, C, R, Ls, Rs & LFE. */ 147 SST_HSW_CHANNEL_CONFIG_DUAL_MONO = 9, /* One channel replicated in two. */ 148 SST_HSW_CHANNEL_CONFIG_INVALID, 149 }; 150 151 /* List of supported bit depths. */ 152 enum sst_hsw_bitdepth { 153 SST_HSW_DEPTH_8BIT = 8, 154 SST_HSW_DEPTH_16BIT = 16, 155 SST_HSW_DEPTH_24BIT = 24, /* Default. */ 156 SST_HSW_DEPTH_32BIT = 32, 157 SST_HSW_DEPTH_INVALID = 33, 158 }; 159 160 enum sst_hsw_module_id { 161 SST_HSW_MODULE_BASE_FW = 0x0, 162 SST_HSW_MODULE_MP3 = 0x1, 163 SST_HSW_MODULE_AAC_5_1 = 0x2, 164 SST_HSW_MODULE_AAC_2_0 = 0x3, 165 SST_HSW_MODULE_SRC = 0x4, 166 SST_HSW_MODULE_WAVES = 0x5, 167 SST_HSW_MODULE_DOLBY = 0x6, 168 SST_HSW_MODULE_BOOST = 0x7, 169 SST_HSW_MODULE_LPAL = 0x8, 170 SST_HSW_MODULE_DTS = 0x9, 171 SST_HSW_MODULE_PCM_CAPTURE = 0xA, 172 SST_HSW_MODULE_PCM_SYSTEM = 0xB, 173 SST_HSW_MODULE_PCM_REFERENCE = 0xC, 174 SST_HSW_MODULE_PCM = 0xD, 175 SST_HSW_MODULE_BLUETOOTH_RENDER_MODULE = 0xE, 176 SST_HSW_MODULE_BLUETOOTH_CAPTURE_MODULE = 0xF, 177 SST_HSW_MAX_MODULE_ID, 178 }; 179 180 enum sst_hsw_performance_action { 181 SST_HSW_PERF_START = 0, 182 SST_HSW_PERF_STOP = 1, 183 }; 184 185 /* SST firmware module info */ 186 struct sst_hsw_module_info { 187 u8 name[SST_HSW_MAX_INFO_SIZE]; 188 u8 version[SST_HSW_MAX_INFO_SIZE]; 189 } __attribute__((packed)); 190 191 /* Module entry point */ 192 struct sst_hsw_module_entry { 193 enum sst_hsw_module_id module_id; 194 u32 entry_point; 195 } __attribute__((packed)); 196 197 /* Module map - alignement matches DSP */ 198 struct sst_hsw_module_map { 199 u8 module_entries_count; 200 struct sst_hsw_module_entry module_entries[1]; 201 } __attribute__((packed)); 202 203 struct sst_hsw_memory_info { 204 u32 offset; 205 u32 size; 206 } __attribute__((packed)); 207 208 struct sst_hsw_fx_enable { 209 struct sst_hsw_module_map module_map; 210 struct sst_hsw_memory_info persistent_mem; 211 } __attribute__((packed)); 212 213 struct sst_hsw_get_fx_param { 214 u32 parameter_id; 215 u32 param_size; 216 } __attribute__((packed)); 217 218 struct sst_hsw_perf_action { 219 u32 action; 220 } __attribute__((packed)); 221 222 struct sst_hsw_perf_data { 223 u64 timestamp; 224 u64 cycles; 225 u64 datatime; 226 } __attribute__((packed)); 227 228 /* FW version */ 229 struct sst_hsw_ipc_fw_version { 230 u8 build; 231 u8 minor; 232 u8 major; 233 u8 type; 234 u8 fw_build_hash[SST_HSW_BUILD_HASH_LENGTH]; 235 u32 fw_log_providers_hash; 236 } __attribute__((packed)); 237 238 /* Stream ring info */ 239 struct sst_hsw_ipc_stream_ring { 240 u32 ring_pt_address; 241 u32 num_pages; 242 u32 ring_size; 243 u32 ring_offset; 244 u32 ring_first_pfn; 245 } __attribute__((packed)); 246 247 /* Debug Dump Log Enable Request */ 248 struct sst_hsw_ipc_debug_log_enable_req { 249 struct sst_hsw_ipc_stream_ring ringinfo; 250 u32 config[SST_HSW_FW_LOG_CONFIG_DWORDS]; 251 } __attribute__((packed)); 252 253 /* Debug Dump Log Reply */ 254 struct sst_hsw_ipc_debug_log_reply { 255 u32 log_buffer_begining; 256 u32 log_buffer_size; 257 } __attribute__((packed)); 258 259 /* Stream glitch position */ 260 struct sst_hsw_ipc_stream_glitch_position { 261 u32 glitch_type; 262 u32 present_pos; 263 u32 write_pos; 264 } __attribute__((packed)); 265 266 /* Stream get position */ 267 struct sst_hsw_ipc_stream_get_position { 268 u32 position; 269 u32 fw_cycle_count; 270 } __attribute__((packed)); 271 272 /* Stream set position */ 273 struct sst_hsw_ipc_stream_set_position { 274 u32 position; 275 u32 end_of_buffer; 276 } __attribute__((packed)); 277 278 /* Stream Free Request */ 279 struct sst_hsw_ipc_stream_free_req { 280 u8 stream_id; 281 u8 reserved[3]; 282 } __attribute__((packed)); 283 284 /* Set Volume Request */ 285 struct sst_hsw_ipc_volume_req { 286 u32 channel; 287 u32 target_volume; 288 u64 curve_duration; 289 u32 curve_type; 290 } __attribute__((packed)); 291 292 /* Device Configuration Request */ 293 struct sst_hsw_ipc_device_config_req { 294 u32 ssp_interface; 295 u32 clock_frequency; 296 u32 mode; 297 u16 clock_divider; 298 u16 reserved; 299 } __attribute__((packed)); 300 301 /* Audio Data formats */ 302 struct sst_hsw_audio_data_format_ipc { 303 u32 frequency; 304 u32 bitdepth; 305 u32 map; 306 u32 config; 307 u32 style; 308 u8 ch_num; 309 u8 valid_bit; 310 u8 reserved[2]; 311 } __attribute__((packed)); 312 313 /* Stream Allocate Request */ 314 struct sst_hsw_ipc_stream_alloc_req { 315 u8 path_id; 316 u8 stream_type; 317 u8 format_id; 318 u8 reserved; 319 struct sst_hsw_audio_data_format_ipc format; 320 struct sst_hsw_ipc_stream_ring ringinfo; 321 struct sst_hsw_module_map map; 322 struct sst_hsw_memory_info persistent_mem; 323 struct sst_hsw_memory_info scratch_mem; 324 u32 number_of_notifications; 325 } __attribute__((packed)); 326 327 /* Stream Allocate Reply */ 328 struct sst_hsw_ipc_stream_alloc_reply { 329 u32 stream_hw_id; 330 u32 mixer_hw_id; // returns rate ???? 331 u32 read_position_register_address; 332 u32 presentation_position_register_address; 333 u32 peak_meter_register_address[SST_HSW_NO_CHANNELS]; 334 u32 volume_register_address[SST_HSW_NO_CHANNELS]; 335 } __attribute__((packed)); 336 337 /* Get Mixer Stream Info */ 338 struct sst_hsw_ipc_stream_info_reply { 339 u32 mixer_hw_id; 340 u32 peak_meter_register_address[SST_HSW_NO_CHANNELS]; 341 u32 volume_register_address[SST_HSW_NO_CHANNELS]; 342 } __attribute__((packed)); 343 344 /* DX State Request */ 345 struct sst_hsw_ipc_dx_req { 346 u8 state; 347 u8 reserved[3]; 348 } __attribute__((packed)); 349 350 /* DX State Reply Memory Info Item */ 351 struct sst_hsw_ipc_dx_memory_item { 352 u32 offset; 353 u32 size; 354 u32 source; 355 } __attribute__((packed)); 356 357 /* DX State Reply */ 358 struct sst_hsw_ipc_dx_reply { 359 u32 entries_no; 360 struct sst_hsw_ipc_dx_memory_item mem_info[SST_HSW_MAX_DX_REGIONS]; 361 } __attribute__((packed)); 362 363 struct sst_hsw_ipc_fw_version; 364 365 /* SST Init & Free */ 366 struct sst_hsw *sst_hsw_new(struct device *dev, const u8 *fw, size_t fw_length, 367 u32 fw_offset); 368 void sst_hsw_free(struct sst_hsw *hsw); 369 int sst_hsw_fw_get_version(struct sst_hsw *hsw, 370 struct sst_hsw_ipc_fw_version *version); 371 u32 create_channel_map(enum sst_hsw_channel_config config); 372 373 /* Stream Mixer Controls - */ 374 int sst_hsw_stream_mute(struct sst_hsw *hsw, struct sst_hsw_stream *stream, 375 u32 stage_id, u32 channel); 376 int sst_hsw_stream_unmute(struct sst_hsw *hsw, struct sst_hsw_stream *stream, 377 u32 stage_id, u32 channel); 378 379 int sst_hsw_stream_set_volume(struct sst_hsw *hsw, 380 struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 volume); 381 int sst_hsw_stream_get_volume(struct sst_hsw *hsw, 382 struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 *volume); 383 384 int sst_hsw_stream_set_volume_curve(struct sst_hsw *hsw, 385 struct sst_hsw_stream *stream, u64 curve_duration, 386 enum sst_hsw_volume_curve curve); 387 388 /* Global Mixer Controls - */ 389 int sst_hsw_mixer_mute(struct sst_hsw *hsw, u32 stage_id, u32 channel); 390 int sst_hsw_mixer_unmute(struct sst_hsw *hsw, u32 stage_id, u32 channel); 391 392 int sst_hsw_mixer_set_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel, 393 u32 volume); 394 int sst_hsw_mixer_get_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel, 395 u32 *volume); 396 397 int sst_hsw_mixer_set_volume_curve(struct sst_hsw *hsw, 398 u64 curve_duration, enum sst_hsw_volume_curve curve); 399 400 /* Stream API */ 401 struct sst_hsw_stream *sst_hsw_stream_new(struct sst_hsw *hsw, int id, 402 u32 (*get_write_position)(struct sst_hsw_stream *stream, void *data), 403 void *data); 404 405 int sst_hsw_stream_free(struct sst_hsw *hsw, struct sst_hsw_stream *stream); 406 407 /* Stream Configuration */ 408 int sst_hsw_stream_format(struct sst_hsw *hsw, struct sst_hsw_stream *stream, 409 enum sst_hsw_stream_path_id path_id, 410 enum sst_hsw_stream_type stream_type, 411 enum sst_hsw_stream_format format_id); 412 413 int sst_hsw_stream_buffer(struct sst_hsw *hsw, struct sst_hsw_stream *stream, 414 u32 ring_pt_address, u32 num_pages, 415 u32 ring_size, u32 ring_offset, u32 ring_first_pfn); 416 417 int sst_hsw_stream_commit(struct sst_hsw *hsw, struct sst_hsw_stream *stream); 418 419 int sst_hsw_stream_set_valid(struct sst_hsw *hsw, struct sst_hsw_stream *stream, 420 u32 bits); 421 int sst_hsw_stream_set_rate(struct sst_hsw *hsw, struct sst_hsw_stream *stream, 422 int rate); 423 int sst_hsw_stream_set_bits(struct sst_hsw *hsw, struct sst_hsw_stream *stream, 424 enum sst_hsw_bitdepth bits); 425 int sst_hsw_stream_set_channels(struct sst_hsw *hsw, 426 struct sst_hsw_stream *stream, int channels); 427 int sst_hsw_stream_set_map_config(struct sst_hsw *hsw, 428 struct sst_hsw_stream *stream, u32 map, 429 enum sst_hsw_channel_config config); 430 int sst_hsw_stream_set_style(struct sst_hsw *hsw, struct sst_hsw_stream *stream, 431 enum sst_hsw_interleaving style); 432 int sst_hsw_stream_set_module_info(struct sst_hsw *hsw, 433 struct sst_hsw_stream *stream, enum sst_hsw_module_id module_id, 434 u32 entry_point); 435 int sst_hsw_stream_set_pmemory_info(struct sst_hsw *hsw, 436 struct sst_hsw_stream *stream, u32 offset, u32 size); 437 int sst_hsw_stream_set_smemory_info(struct sst_hsw *hsw, 438 struct sst_hsw_stream *stream, u32 offset, u32 size); 439 int sst_hsw_stream_get_hw_id(struct sst_hsw *hsw, 440 struct sst_hsw_stream *stream); 441 int sst_hsw_stream_get_mixer_id(struct sst_hsw *hsw, 442 struct sst_hsw_stream *stream); 443 u32 sst_hsw_stream_get_read_reg(struct sst_hsw *hsw, 444 struct sst_hsw_stream *stream); 445 u32 sst_hsw_stream_get_pointer_reg(struct sst_hsw *hsw, 446 struct sst_hsw_stream *stream); 447 u32 sst_hsw_stream_get_peak_reg(struct sst_hsw *hsw, 448 struct sst_hsw_stream *stream, u32 channel); 449 u32 sst_hsw_stream_get_vol_reg(struct sst_hsw *hsw, 450 struct sst_hsw_stream *stream, u32 channel); 451 int sst_hsw_mixer_get_info(struct sst_hsw *hsw); 452 453 /* Stream ALSA trigger operations */ 454 int sst_hsw_stream_pause(struct sst_hsw *hsw, struct sst_hsw_stream *stream, 455 int wait); 456 int sst_hsw_stream_resume(struct sst_hsw *hsw, struct sst_hsw_stream *stream, 457 int wait); 458 int sst_hsw_stream_reset(struct sst_hsw *hsw, struct sst_hsw_stream *stream); 459 460 /* Stream pointer positions */ 461 int sst_hsw_stream_get_read_pos(struct sst_hsw *hsw, 462 struct sst_hsw_stream *stream, u32 *position); 463 int sst_hsw_stream_get_write_pos(struct sst_hsw *hsw, 464 struct sst_hsw_stream *stream, u32 *position); 465 int sst_hsw_stream_set_write_position(struct sst_hsw *hsw, 466 struct sst_hsw_stream *stream, u32 stage_id, u32 position); 467 u32 sst_hsw_get_dsp_position(struct sst_hsw *hsw, 468 struct sst_hsw_stream *stream); 469 u64 sst_hsw_get_dsp_presentation_position(struct sst_hsw *hsw, 470 struct sst_hsw_stream *stream); 471 472 /* HW port config */ 473 int sst_hsw_device_set_config(struct sst_hsw *hsw, 474 enum sst_hsw_device_id dev, enum sst_hsw_device_mclk mclk, 475 enum sst_hsw_device_mode mode, u32 clock_divider); 476 477 /* DX Config */ 478 int sst_hsw_dx_set_state(struct sst_hsw *hsw, 479 enum sst_hsw_dx_state state, struct sst_hsw_ipc_dx_reply *dx); 480 int sst_hsw_dx_get_state(struct sst_hsw *hsw, u32 item, 481 u32 *offset, u32 *size, u32 *source); 482 483 /* init */ 484 int sst_hsw_dsp_init(struct device *dev, struct sst_pdata *pdata); 485 void sst_hsw_dsp_free(struct device *dev, struct sst_pdata *pdata); 486 struct sst_dsp *sst_hsw_get_dsp(struct sst_hsw *hsw); 487 void sst_hsw_set_scratch_module(struct sst_hsw *hsw, 488 struct sst_module *scratch); 489 490 #endif 491