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Searched refs:IO_ADDRESS (Results 1 – 25 of 86) sorted by relevance

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/arch/arm/mach-pnx4008/
Dtime.h23 #define MSTIM_INT IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x0))
24 #define MSTIM_CTRL IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x4))
25 #define MSTIM_COUNTER IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x8))
26 #define MSTIM_MCTRL IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x14))
27 #define MSTIM_MATCH0 IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x18))
28 #define MSTIM_MATCH1 IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x1c))
32 #define HSTIM_INT IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x0))
33 #define HSTIM_CTRL IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x4))
34 #define HSTIM_COUNTER IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x8))
35 #define HSTIM_PMATCH IO_ADDRESS((PNX4008_HSTIMER_BASE + 0xC))
[all …]
Dserial.c31 #define UART3_BASE_VA IO_ADDRESS(PNX4008_UART3_BASE)
32 #define UART4_BASE_VA IO_ADDRESS(PNX4008_UART4_BASE)
33 #define UART5_BASE_VA IO_ADDRESS(PNX4008_UART5_BASE)
34 #define UART6_BASE_VA IO_ADDRESS(PNX4008_UART6_BASE)
Dcore.c108 .membase = (void *)__iomem(IO_ADDRESS(PNX4008_UART5_BASE)),
117 .membase = (void *)__iomem(IO_ADDRESS(PNX4008_UART3_BASE)),
149 .start = IO_ADDRESS(PNX4008_USB_CONFIG_BASE),
150 .end = IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0x100),
231 .virtual = IO_ADDRESS(PNX4008_IRAM_BASE),
236 .virtual = IO_ADDRESS(PNX4008_NDF_FLASH_BASE),
241 .virtual = IO_ADDRESS(PNX4008_JPEG_CONFIG_BASE),
246 .virtual = IO_ADDRESS(PNX4008_DMA_CONFIG_BASE),
251 .virtual = IO_ADDRESS(PNX4008_AHB2FAB_BASE),
/arch/arm/mach-pnx4008/include/mach/
Dirq.h18 #define MIC_VA_BASE IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
19 #define SIC1_VA_BASE IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
20 #define SIC2_VA_BASE IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
26 #define INTC_ER(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x0 + (((irq)&(0x3<<5))<<9)))
27 #define INTC_RSR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x4 + (((irq)&(0x3<<5))<<9)))
28 #define INTC_SR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x8 + (((irq)&(0x3<<5))<<9)))
29 #define INTC_APR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0xC + (((irq)&(0x3<<5))<<9)))
30 #define INTC_ATR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x10 + (((irq)&(0x3<<5))<<9)))
31 #define INTC_ITR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x14 + (((irq)&(0x3<<5))<<9)))
35 #define START_INT_ER_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1)))
[all …]
Dclock.h19 #define PWRMAN_VA_BASE IO_ADDRESS(PNX4008_PWRMAN_BASE)
44 #define AUDIOCONFIG_VA_BASE IO_ADDRESS(PNX4008_AUDIOCONFIG_BASE)
50 #define USB_OTG_CLKCTRL_REG IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xff4)
52 #define VFP9CLKCTRL_REG IO_ADDRESS(PNX4008_DEBUG_BASE)
Dentry-macro.S16 #define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE) macro
33 ldr \base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
66 ldreq \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
68 ldrne \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
82 ldrne \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
84 ldreq \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
/arch/arm/mach-gemini/
Dmm.c22 .virtual = IO_ADDRESS(GEMINI_GLOBAL_BASE),
27 .virtual = IO_ADDRESS(GEMINI_UART_BASE),
32 .virtual = IO_ADDRESS(GEMINI_TIMER_BASE),
37 .virtual = IO_ADDRESS(GEMINI_INTERRUPT_BASE),
42 .virtual = IO_ADDRESS(GEMINI_POWER_CTRL_BASE),
47 .virtual = IO_ADDRESS(GEMINI_GPIO_BASE(0)),
52 .virtual = IO_ADDRESS(GEMINI_GPIO_BASE(1)),
57 .virtual = IO_ADDRESS(GEMINI_GPIO_BASE(2)),
62 .virtual = IO_ADDRESS(GEMINI_FLASH_CTRL_BASE),
67 .virtual = IO_ADDRESS(GEMINI_DRAM_CTRL_BASE),
[all …]
Dirq.c37 __raw_writel(1 << d->irq, IRQ_CLEAR(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); in gemini_ack_irq()
44 mask = __raw_readl(IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); in gemini_mask_irq()
46 __raw_writel(mask, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); in gemini_mask_irq()
53 mask = __raw_readl(IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); in gemini_unmask_irq()
55 __raw_writel(mask, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); in gemini_unmask_irq()
67 .start = IO_ADDRESS(GEMINI_INTERRUPT_BASE),
68 .end = IO_ADDRESS(FIQ_STATUS(GEMINI_INTERRUPT_BASE)) + 4,
96 __raw_writel(0, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); in gemini_init_irq()
97 __raw_writel(0, FIQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); in gemini_init_irq()
100 __raw_writel(mode, IRQ_TMODE(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); in gemini_init_irq()
[all …]
Dtime.c59 reg_v = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE + GLOBAL_STATUS)); in gemini_timer_init()
86 __raw_writel(tick_rate / HZ, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE))); in gemini_timer_init()
87 __raw_writel(tick_rate / HZ, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE))); in gemini_timer_init()
88 __raw_writel(TIMER_2_CR_ENABLE | TIMER_2_CR_INT, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); in gemini_timer_init()
Ddevices.c23 .membase = (void *)IO_ADDRESS(GEMINI_UART_BASE),
70 reg = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_STATUS); in platform_register_pflash()
81 reg = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_MISC_CTRL); in platform_register_pflash()
84 __raw_writel(reg, IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_MISC_CTRL); in platform_register_pflash()
/arch/arm/mach-tegra/
Dirq.c52 IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
53 IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
54 IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
55 IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
56 IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE),
120 distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE); in tegra_init_irq()
147 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); in tegra_init_irq()
Dplatsmp.c37 static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
40 (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
42 (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c)
44 (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x340)
46 (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344)
48 (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x34c)
Dreset.c38 void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE); in tegra_cpu_reset_handler_enable()
40 IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100); in tegra_cpu_reset_handler_enable()
41 void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE); in tegra_cpu_reset_handler_enable()
/arch/arm/mach-realview/include/mach/
Dhardware.h36 #define IO_ADDRESS(x) (((x) & 0x03ffffff) + 0xfb000000) macro
38 #define IO_ADDRESS(x) (x) macro
40 #define __io_address(n) IOMEM(IO_ADDRESS(n))
/arch/arm/mach-integrator/include/mach/
Dhardware.h37 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE) macro
39 #define IO_ADDRESS(x) (x) macro
42 #define __io_address(n) ((void __iomem *)IO_ADDRESS(n))
/arch/arm/mach-spear6xx/include/mach/
Dspear.h25 #define VA_SPEAR6XX_ICM1_UART0_BASE IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE)
50 #define VA_SPEAR6XX_CPU_VIC_SEC_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE)
52 #define VA_SPEAR6XX_CPU_VIC_PRI_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE)
66 #define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE)
68 #define VA_SPEAR6XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE)
/arch/arm/mach-nomadik/include/mach/
Dhardware.h33 #define IO_ADDRESS(x) ((x) - NOMADIK_IO_PHYSICAL + NOMADIK_IO_VIRTUAL) macro
86 #define NOMADIK_FSMC_VA IO_ADDRESS(NOMADIK_FSMC_BASE)
87 #define NOMADIK_MTU0_VA IO_ADDRESS(NOMADIK_MTU0_BASE)
88 #define NOMADIK_MTU1_VA IO_ADDRESS(NOMADIK_MTU1_BASE)
/arch/arm/mach-integrator/
Dintegrator_cp.c62 #define INTCP_VA_CTRL_BASE IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
84 .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
89 .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
94 .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
99 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
104 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
109 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
114 .virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
119 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
124 .virtual = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
[all …]
Dintegrator_ap.c90 .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
95 .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
100 .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
105 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
110 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
115 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
120 .virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
125 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
130 .virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
323 #define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE)
[all …]
/arch/arm/mach-spear3xx/include/mach/
Dspear.h29 #define VA_SPEAR3XX_ICM1_UART_BASE IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE)
56 #define VA_SPEAR3XX_ML1_VIC_BASE IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE)
68 #define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE)
70 #define VA_SPEAR3XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE)
/arch/arm/mach-versatile/include/mach/
Dhardware.h34 #define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) macro
36 #define __io_address(n) ((void __iomem __force *)IO_ADDRESS(n))
/arch/arm/mach-picoxcell/include/mach/
Dmap.h20 #define IO_ADDRESS(x) PHYS_TO_IO((x))
22 #define IO_ADDRESS(x) (void __iomem __force *)(PHYS_TO_IO((x))) macro
/arch/arm/mach-lpc32xx/include/mach/
Dhardware.h28 #define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\ macro
31 #define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x))
/arch/arm/mach-realview/
Drealview_pb1176.c54 .virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
59 .virtual = IO_ADDRESS(REALVIEW_PB1176_GIC_CPU_BASE),
64 .virtual = IO_ADDRESS(REALVIEW_PB1176_GIC_DIST_BASE),
69 .virtual = IO_ADDRESS(REALVIEW_DC1176_GIC_CPU_BASE),
74 .virtual = IO_ADDRESS(REALVIEW_DC1176_GIC_DIST_BASE),
79 .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
84 .virtual = IO_ADDRESS(REALVIEW_PB1176_TIMER0_1_BASE),
89 .virtual = IO_ADDRESS(REALVIEW_PB1176_TIMER2_3_BASE),
94 .virtual = IO_ADDRESS(REALVIEW_PB1176_L220_BASE),
101 .virtual = IO_ADDRESS(REALVIEW_PB1176_UART0_BASE),
/arch/arm/mach-ux500/include/mach/
Dhardware.h22 #define IO_ADDRESS(x) \ macro
26 #define __io_address(n) IOMEM(IO_ADDRESS(n))

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