1/* 2 * arch/arm/mach-pnx4008/include/mach/entry-macro.S 3 * 4 * Low-level IRQ helper macros for PNX4008-based platforms 5 * 6 * 2005-2006 (c) MontaVista Software, Inc. 7 * Author: Vitaly Wool <vwool@ru.mvista.com> 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13#include "platform.h" 14 15#define IO_BASE 0xF0000000 16#define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE) 17 18#define INTRC_MASK 0x00 19#define INTRC_RAW_STAT 0x04 20#define INTRC_STAT 0x08 21#define INTRC_POLAR 0x0C 22#define INTRC_ACT_TYPE 0x10 23#define INTRC_TYPE 0x14 24 25#define SIC1_BASE_INT 32 26#define SIC2_BASE_INT 64 27 28 .macro get_irqnr_preamble, base, tmp 29 .endm 30 31 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 32/* decode the MIC interrupt numbers */ 33 ldr \base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE) 34 ldr \irqstat, [\base, #INTRC_STAT] 35 36 cmp \irqstat,#1<<16 37 movhs \irqnr,#16 38 movlo \irqnr,#0 39 movhs \irqstat,\irqstat,lsr#16 40 cmp \irqstat,#1<<8 41 addhs \irqnr,\irqnr,#8 42 movhs \irqstat,\irqstat,lsr#8 43 cmp \irqstat,#1<<4 44 addhs \irqnr,\irqnr,#4 45 movhs \irqstat,\irqstat,lsr#4 46 cmp \irqstat,#1<<2 47 addhs \irqnr,\irqnr,#2 48 movhs \irqstat,\irqstat,lsr#2 49 cmp \irqstat,#1<<1 50 addhs \irqnr,\irqnr,#1 51 52/* was there an interrupt ? if not then drop out with EQ status */ 53 teq \irqstat,#0 54 beq 1003f 55 56/* and now check for extended IRQ reasons */ 57 cmp \irqnr,#1 58 bls 1003f 59 cmp \irqnr,#30 60 blo 1002f 61 62/* IRQ 31,30 : High priority cascade IRQ handle */ 63/* read the correct SIC */ 64/* decoding status after compare : eq is 30 (SIC1) , ne is 31 (SIC2) */ 65/* set the base IRQ number */ 66 ldreq \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE) 67 moveq \irqnr,#SIC1_BASE_INT 68 ldrne \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE) 69 movne \irqnr,#SIC2_BASE_INT 70 ldr \irqstat, [\base, #INTRC_STAT] 71 ldr \tmp, [\base, #INTRC_TYPE] 72/* and with inverted mask : low priority interrupts */ 73 and \irqstat,\irqstat,\tmp 74 b 1004f 75 761003: 77/* IRQ 1,0 : Low priority cascade IRQ handle */ 78/* read the correct SIC */ 79/* decoding status after compare : eq is 1 (SIC2) , ne is 0 (SIC1)*/ 80/* read the correct SIC */ 81/* set the base IRQ number */ 82 ldrne \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE) 83 movne \irqnr,#SIC1_BASE_INT 84 ldreq \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE) 85 moveq \irqnr,#SIC2_BASE_INT 86 ldr \irqstat, [\base, #INTRC_STAT] 87 ldr \tmp, [\base, #INTRC_TYPE] 88/* and with inverted mask : low priority interrupts */ 89 bic \irqstat,\irqstat,\tmp 90 911004: 92 93 cmp \irqstat,#1<<16 94 addhs \irqnr,\irqnr,#16 95 movhs \irqstat,\irqstat,lsr#16 96 cmp \irqstat,#1<<8 97 addhs \irqnr,\irqnr,#8 98 movhs \irqstat,\irqstat,lsr#8 99 cmp \irqstat,#1<<4 100 addhs \irqnr,\irqnr,#4 101 movhs \irqstat,\irqstat,lsr#4 102 cmp \irqstat,#1<<2 103 addhs \irqnr,\irqnr,#2 104 movhs \irqstat,\irqstat,lsr#2 105 cmp \irqstat,#1<<1 106 addhs \irqnr,\irqnr,#1 107 108 109/* is irqstat not zero */ 110 1111002: 112/* we assert that irqstat is not equal to zero and return ne status if true*/ 113 teq \irqstat,#0 1141003: 115 .endm 116 117