Searched refs:L3 (Results 1 – 16 of 16) sorted by relevance
/arch/m68k/lib/ |
D | divsi3.S | 120 jpl L3 123 L3: movel sp@+, d2 label
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D | udivsi3.S | 100 jcc L3 /* then try next algorithm */ 112 L3: movel d1, d2 /* use d2 as divisor backup */ label
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/arch/blackfin/kernel/cplb-mpu/ |
D | Makefile | 8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
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/arch/blackfin/kernel/cplb-nompu/ |
D | Makefile | 8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
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/arch/arm/mach-exynos/include/mach/ |
D | cpufreq.h | 14 L0, L1, L2, L3, L4, enumerator
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/arch/m68k/platform/68328/ |
D | head-pilot.S | 160 L3: label 164 bhi L3
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/arch/alpha/kernel/ |
D | setup.c | 1337 int L1I, L1D, L2, L3; in determine_cpu_caches() local 1348 L3 = -1; in determine_cpu_caches() 1369 L3 = -1; in determine_cpu_caches() 1400 L3 = external_cache_probe(1024*1024, width); in determine_cpu_caches() 1414 L3 = -1; in determine_cpu_caches() 1437 L3 = -1; in determine_cpu_caches() 1444 L3 = -1; in determine_cpu_caches() 1449 L1I = L1D = L2 = L3 = 0; in determine_cpu_caches() 1456 alpha_l3_cacheshape = L3; in determine_cpu_caches()
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/arch/xtensa/lib/ |
D | memset.S | 91 bbci.l a4, 2, .L3 95 .L3: label
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D | memcopy.S | 197 bbsi.l a4, 2, .L3 201 .L3: label
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D | usercopy.S | 187 bbci.l a4, 2, .L3 193 .L3: label
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/arch/hexagon/lib/ |
D | memset.S | 177 if (p0.new) jump:nt .L3 189 .L3: label
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/arch/blackfin/mach-bf561/ |
D | secondary.S | 50 L3 = r6; define
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/arch/arm/mach-omap2/ |
D | sram242x.S | 101 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks 195 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks 311 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
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D | sram243x.S | 101 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks 195 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks 311 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
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D | Kconfig | 376 can be found on path between MPU to EMIF and MPU to L3 interconnect. 384 In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
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/arch/blackfin/mach-common/ |
D | head.S | 59 L3 = r6; define
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