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Searched refs:L3 (Results 1 – 16 of 16) sorted by relevance

/arch/m68k/lib/
Ddivsi3.S120 jpl L3
123 L3: movel sp@+, d2 label
Dudivsi3.S100 jcc L3 /* then try next algorithm */
112 L3: movel d1, d2 /* use d2 as divisor backup */ label
/arch/blackfin/kernel/cplb-mpu/
DMakefile8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
/arch/blackfin/kernel/cplb-nompu/
DMakefile8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
/arch/arm/mach-exynos/include/mach/
Dcpufreq.h14 L0, L1, L2, L3, L4, enumerator
/arch/m68k/platform/68328/
Dhead-pilot.S160 L3: label
164 bhi L3
/arch/alpha/kernel/
Dsetup.c1337 int L1I, L1D, L2, L3; in determine_cpu_caches() local
1348 L3 = -1; in determine_cpu_caches()
1369 L3 = -1; in determine_cpu_caches()
1400 L3 = external_cache_probe(1024*1024, width); in determine_cpu_caches()
1414 L3 = -1; in determine_cpu_caches()
1437 L3 = -1; in determine_cpu_caches()
1444 L3 = -1; in determine_cpu_caches()
1449 L1I = L1D = L2 = L3 = 0; in determine_cpu_caches()
1456 alpha_l3_cacheshape = L3; in determine_cpu_caches()
/arch/xtensa/lib/
Dmemset.S91 bbci.l a4, 2, .L3
95 .L3: label
Dmemcopy.S197 bbsi.l a4, 2, .L3
201 .L3: label
Dusercopy.S187 bbci.l a4, 2, .L3
193 .L3: label
/arch/hexagon/lib/
Dmemset.S177 if (p0.new) jump:nt .L3
189 .L3: label
/arch/blackfin/mach-bf561/
Dsecondary.S50 L3 = r6; define
/arch/arm/mach-omap2/
Dsram242x.S101 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
195 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
311 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
Dsram243x.S101 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
195 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
311 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
DKconfig376 can be found on path between MPU to EMIF and MPU to L3 interconnect.
384 In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
/arch/blackfin/mach-common/
Dhead.S59 L3 = r6; define