Searched refs:PAD_CTL_DSE_HIGH (Results 1 – 7 of 7) sorted by relevance
24 #define MX50_ELCDIF_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH)27 PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH)29 #define MX50_UART_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE)31 #define MX50_I2C_PAD_CTRL (PAD_CTL_ODE | PAD_CTL_DSE_HIGH | \35 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP)39 PAD_CTL_DSE_HIGH)43 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)46 PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH)49 PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_HIGH)53 #define MX50_PAD_KEY_COL0__NANDF_CLE IOMUX_PAD(0x2CC, 0x20, 2, 0x0, 0, PAD_CTL_DSE_HIGH)[all …]
103 #define PAD_CTL_DSE_HIGH (2 << 1) macro
21 #define MX51_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \24 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \27 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \30 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \33 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)34 #define MX51_SDHCI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \37 #define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST)42 #define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)184 PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS))
29 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS)31 PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \
49 PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),68 PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
110 PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
365 PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH); in mx51_babbage_init()