1 /*
2 *
3 * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
4 *
5 * based on board-mx51_babbage.c which is
6 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17 #include <linux/init.h>
18 #include <linux/platform_device.h>
19 #include <linux/i2c.h>
20 #include <linux/i2c/tsc2007.h>
21 #include <linux/gpio.h>
22 #include <linux/delay.h>
23 #include <linux/io.h>
24 #include <linux/interrupt.h>
25 #include <linux/i2c-gpio.h>
26 #include <linux/spi/spi.h>
27 #include <linux/can/platform/mcp251x.h>
28
29 #include <mach/eukrea-baseboards.h>
30 #include <mach/common.h>
31 #include <mach/hardware.h>
32 #include <mach/iomux-mx51.h>
33
34 #include <asm/setup.h>
35 #include <asm/mach-types.h>
36 #include <asm/mach/arch.h>
37 #include <asm/mach/time.h>
38
39 #include "devices-imx51.h"
40 #include "cpu_op-mx51.h"
41
42 #define USBH1_RST IMX_GPIO_NR(2, 28)
43 #define ETH_RST IMX_GPIO_NR(2, 31)
44 #define TSC2007_IRQGPIO IMX_GPIO_NR(3, 12)
45 #define CAN_IRQGPIO IMX_GPIO_NR(1, 1)
46 #define CAN_RST IMX_GPIO_NR(4, 15)
47 #define CAN_NCS IMX_GPIO_NR(4, 24)
48 #define CAN_RXOBF IMX_GPIO_NR(1, 4)
49 #define CAN_RX1BF IMX_GPIO_NR(1, 6)
50 #define CAN_TXORTS IMX_GPIO_NR(1, 7)
51 #define CAN_TX1RTS IMX_GPIO_NR(1, 8)
52 #define CAN_TX2RTS IMX_GPIO_NR(1, 9)
53 #define I2C_SCL IMX_GPIO_NR(4, 16)
54 #define I2C_SDA IMX_GPIO_NR(4, 17)
55
56 /* USB_CTRL_1 */
57 #define MX51_USB_CTRL_1_OFFSET 0x10
58 #define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
59
60 #define MX51_USB_PLLDIV_12_MHZ 0x00
61 #define MX51_USB_PLL_DIV_19_2_MHZ 0x01
62 #define MX51_USB_PLL_DIV_24_MHZ 0x02
63
64 static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
65 /* UART1 */
66 MX51_PAD_UART1_RXD__UART1_RXD,
67 MX51_PAD_UART1_TXD__UART1_TXD,
68 MX51_PAD_UART1_RTS__UART1_RTS,
69 MX51_PAD_UART1_CTS__UART1_CTS,
70
71 /* USB HOST1 */
72 MX51_PAD_USBH1_CLK__USBH1_CLK,
73 MX51_PAD_USBH1_DIR__USBH1_DIR,
74 MX51_PAD_USBH1_NXT__USBH1_NXT,
75 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
76 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
77 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
78 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
79 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
80 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
81 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
82 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
83 MX51_PAD_USBH1_STP__USBH1_STP,
84 MX51_PAD_EIM_CS3__GPIO2_28, /* PHY nRESET */
85
86 /* FEC */
87 MX51_PAD_EIM_DTACK__GPIO2_31, /* PHY nRESET */
88
89 /* HSI2C */
90 MX51_PAD_I2C1_CLK__GPIO4_16,
91 MX51_PAD_I2C1_DAT__GPIO4_17,
92
93 /* CAN */
94 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
95 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
96 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
97 MX51_PAD_CSPI1_SS0__GPIO4_24, /* nCS */
98 MX51_PAD_CSI2_PIXCLK__GPIO4_15, /* nReset */
99 MX51_PAD_GPIO1_1__GPIO1_1, /* IRQ */
100 MX51_PAD_GPIO1_4__GPIO1_4, /* Control signals */
101 MX51_PAD_GPIO1_6__GPIO1_6,
102 MX51_PAD_GPIO1_7__GPIO1_7,
103 MX51_PAD_GPIO1_8__GPIO1_8,
104 MX51_PAD_GPIO1_9__GPIO1_9,
105
106 /* Touchscreen */
107 /* IRQ */
108 NEW_PAD_CTRL(MX51_PAD_GPIO_NAND__GPIO_NAND, PAD_CTL_PUS_22K_UP |
109 PAD_CTL_PKE | PAD_CTL_SRE_FAST |
110 PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
111 };
112
113 static const struct imxuart_platform_data uart_pdata __initconst = {
114 .flags = IMXUART_HAVE_RTSCTS,
115 };
116
117 static struct tsc2007_platform_data tsc2007_info = {
118 .model = 2007,
119 .x_plate_ohms = 180,
120 };
121
122 static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
123 {
124 I2C_BOARD_INFO("pcf8563", 0x51),
125 }, {
126 I2C_BOARD_INFO("tsc2007", 0x49),
127 .type = "tsc2007",
128 .platform_data = &tsc2007_info,
129 .irq = IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO),
130 },
131 };
132
133 static const struct mxc_nand_platform_data
134 eukrea_cpuimx51sd_nand_board_info __initconst = {
135 .width = 1,
136 .hw_ecc = 1,
137 .flash_bbt = 1,
138 };
139
140 /* This function is board specific as the bit mask for the plldiv will also
141 be different for other Freescale SoCs, thus a common bitmask is not
142 possible and cannot get place in /plat-mxc/ehci.c.*/
initialize_otg_port(struct platform_device * pdev)143 static int initialize_otg_port(struct platform_device *pdev)
144 {
145 u32 v;
146 void __iomem *usb_base;
147 void __iomem *usbother_base;
148
149 usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
150 if (!usb_base)
151 return -ENOMEM;
152 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
153
154 /* Set the PHY clock to 19.2MHz */
155 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
156 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
157 v |= MX51_USB_PLL_DIV_19_2_MHZ;
158 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
159 iounmap(usb_base);
160
161 mdelay(10);
162
163 return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
164 }
165
initialize_usbh1_port(struct platform_device * pdev)166 static int initialize_usbh1_port(struct platform_device *pdev)
167 {
168 u32 v;
169 void __iomem *usb_base;
170 void __iomem *usbother_base;
171
172 usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
173 if (!usb_base)
174 return -ENOMEM;
175 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
176
177 /* The clock for the USBH1 ULPI port will come from the PHY. */
178 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
179 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
180 usbother_base + MX51_USB_CTRL_1_OFFSET);
181 iounmap(usb_base);
182
183 mdelay(10);
184
185 return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
186 MXC_EHCI_ITC_NO_THRESHOLD);
187 }
188
189 static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
190 .init = initialize_otg_port,
191 .portsc = MXC_EHCI_UTMI_16BIT,
192 };
193
194 static const struct fsl_usb2_platform_data usb_pdata __initconst = {
195 .operating_mode = FSL_USB2_DR_DEVICE,
196 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
197 };
198
199 static const struct mxc_usbh_platform_data usbh1_config __initconst = {
200 .init = initialize_usbh1_port,
201 .portsc = MXC_EHCI_MODE_ULPI,
202 };
203
204 static int otg_mode_host;
205
eukrea_cpuimx51sd_otg_mode(char * options)206 static int __init eukrea_cpuimx51sd_otg_mode(char *options)
207 {
208 if (!strcmp(options, "host"))
209 otg_mode_host = 1;
210 else if (!strcmp(options, "device"))
211 otg_mode_host = 0;
212 else
213 pr_info("otg_mode neither \"host\" nor \"device\". "
214 "Defaulting to device\n");
215 return 0;
216 }
217 __setup("otg_mode=", eukrea_cpuimx51sd_otg_mode);
218
219 static struct i2c_gpio_platform_data pdata = {
220 .sda_pin = I2C_SDA,
221 .sda_is_open_drain = 0,
222 .scl_pin = I2C_SCL,
223 .scl_is_open_drain = 0,
224 .udelay = 2,
225 };
226
227 static struct platform_device hsi2c_gpio_device = {
228 .name = "i2c-gpio",
229 .id = 0,
230 .dev.platform_data = &pdata,
231 };
232
233 static struct mcp251x_platform_data mcp251x_info = {
234 .oscillator_frequency = 24E6,
235 };
236
237 static struct spi_board_info cpuimx51sd_spi_device[] = {
238 {
239 .modalias = "mcp2515",
240 .max_speed_hz = 10000000,
241 .bus_num = 0,
242 .mode = SPI_MODE_0,
243 .chip_select = 0,
244 .platform_data = &mcp251x_info,
245 .irq = IMX_GPIO_TO_IRQ(CAN_IRQGPIO)
246 },
247 };
248
249 static int cpuimx51sd_spi1_cs[] = {
250 CAN_NCS,
251 };
252
253 static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst = {
254 .chipselect = cpuimx51sd_spi1_cs,
255 .num_chipselect = ARRAY_SIZE(cpuimx51sd_spi1_cs),
256 };
257
258 static struct platform_device *platform_devices[] __initdata = {
259 &hsi2c_gpio_device,
260 };
261
eukrea_cpuimx51sd_init(void)262 static void __init eukrea_cpuimx51sd_init(void)
263 {
264 imx51_soc_init();
265
266 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
267 ARRAY_SIZE(eukrea_cpuimx51sd_pads));
268
269 #if defined(CONFIG_CPU_FREQ_IMX)
270 get_cpu_op = mx51_get_cpu_op;
271 #endif
272
273 imx51_add_imx_uart(0, &uart_pdata);
274 imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
275
276 gpio_request(ETH_RST, "eth_rst");
277 gpio_set_value(ETH_RST, 1);
278 imx51_add_fec(NULL);
279
280 gpio_request(CAN_IRQGPIO, "can_irq");
281 gpio_direction_input(CAN_IRQGPIO);
282 gpio_free(CAN_IRQGPIO);
283 gpio_request(CAN_NCS, "can_ncs");
284 gpio_direction_output(CAN_NCS, 1);
285 gpio_free(CAN_NCS);
286 gpio_request(CAN_RST, "can_rst");
287 gpio_direction_output(CAN_RST, 0);
288 msleep(20);
289 gpio_set_value(CAN_RST, 1);
290 imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
291 spi_register_board_info(cpuimx51sd_spi_device,
292 ARRAY_SIZE(cpuimx51sd_spi_device));
293
294 gpio_request(TSC2007_IRQGPIO, "tsc2007_irq");
295 gpio_direction_input(TSC2007_IRQGPIO);
296 gpio_free(TSC2007_IRQGPIO);
297
298 i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices,
299 ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices));
300 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
301
302 if (otg_mode_host)
303 imx51_add_mxc_ehci_otg(&dr_utmi_config);
304 else {
305 initialize_otg_port(NULL);
306 imx51_add_fsl_usb2_udc(&usb_pdata);
307 }
308
309 gpio_request(USBH1_RST, "usb_rst");
310 gpio_direction_output(USBH1_RST, 0);
311 msleep(20);
312 gpio_set_value(USBH1_RST, 1);
313 imx51_add_mxc_ehci_hs(1, &usbh1_config);
314
315 #ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
316 eukrea_mbimxsd51_baseboard_init();
317 #endif
318 }
319
eukrea_cpuimx51sd_timer_init(void)320 static void __init eukrea_cpuimx51sd_timer_init(void)
321 {
322 mx51_clocks_init(32768, 24000000, 22579200, 0);
323 }
324
325 static struct sys_timer mxc_timer = {
326 .init = eukrea_cpuimx51sd_timer_init,
327 };
328
329 MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
330 /* Maintainer: Eric Bénard <eric@eukrea.com> */
331 .atag_offset = 0x100,
332 .map_io = mx51_map_io,
333 .init_early = imx51_init_early,
334 .init_irq = mx51_init_irq,
335 .handle_irq = imx51_handle_irq,
336 .timer = &mxc_timer,
337 .init_machine = eukrea_cpuimx51sd_init,
338 .restart = mxc_restart,
339 MACHINE_END
340