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/arch/m68k/platform/coldfire/
Dhead.S30 movel #CONFIG_RAMSIZE,%d0 /* hard coded memory size */
44 movel MCFSIM_DMR0,%d0 /* get mask for 1st bank */
45 btst #0,%d0 /* check if region enabled */
47 andl #0xfffc0000,%d0
49 addl #0x00040000,%d0 /* convert mask to size */
57 addl %d1,%d0 /* total mem size in d0 */
63 movel MCF_MBAR+MCFSIM_CSOR7,%d0 /* get SDRAM address mask */
64 andil #0xfffff000,%d0 /* mask out chip select options */
65 negl %d0 /* negate bits */
70 clrl %d0
[all …]
/arch/mn10300/kernel/
Dhead.S68 mov d0,a3
71 mov swapper_pg_dir,d0
72 mov d0,(PTBR)
73 clr d0
74 movbu d0,(PIDR)
77 mov MMUCTR_IIV|MMUCTR_DIV,d0
78 mov d0,(MMUCTR)
80 mov MMUCTR_ITE|MMUCTR_DTE|MMUCTR_CE|MMUCTR_WTE,d0
82 mov MMUCTR_ITE|MMUCTR_DTE|MMUCTR_CE,d0
84 mov d0,(MMUCTR)
[all …]
Dentry.S54 clr d0
55 mov d0,(REG_D0,fp)
66 mov d0,(REG_ORIG_D0,fp)
68 cmp nr_syscalls,d0
73 add d0,d0,a1
75 mov (REG_A0,fp),d0
78 mov d0,(REG_D0,fp)
126 mov fp,d0
133 mov -ENOSYS,d0
134 mov d0,(REG_D0,fp)
[all …]
Dsmp-low.S33 mov d0,(sp)
34 movhu (IAGR),d0
35 and IAGR_GN,d0
36 lsr 0x2,d0
38 cmp FLUSH_CACHE_IPI,d0
41 cmp SMP_BOOT_IRQ,d0
44 mov (sp),d0
59 mov (sp),d0
80 movhu (GxICR(SMP_BOOT_IRQ)),d0
81 and ~GxICR_REQUEST,d0
[all …]
/arch/powerpc/math-emu/
Dudivmodti4.c11 _FP_W_TYPE d1, _FP_W_TYPE d0) in _fp_udivmodti4() argument
19 if (d0 > n1) in _fp_udivmodti4()
23 udiv_qrnnd (q0, n0, n1, n0, d0); in _fp_udivmodti4()
32 if (d0 == 0) in _fp_udivmodti4()
33 d0 = 1 / d0; /* Divide intentionally by zero. */ in _fp_udivmodti4()
35 udiv_qrnnd (q1, n1, 0, n1, d0); in _fp_udivmodti4()
36 udiv_qrnnd (q0, n0, n1, n0, d0); in _fp_udivmodti4()
46 if (d0 > n1) in _fp_udivmodti4()
50 count_leading_zeros (bm, d0); in _fp_udivmodti4()
57 d0 = d0 << bm; in _fp_udivmodti4()
[all …]
/arch/m68k/include/asm/
Dm5249sim.h202 moveb #MCFINTC2_VECBASE,%d0
203 moveb %d0,0x16b(%a1) /* interrupt base register */
208 movel #0x001F0021,%d0 /* disable C/I bit */
209 movel %d0,0x84(%a0) /* set CSMR0 */
215 movel 0x180(%a1),%d0 /* get current PLL value */
216 andl #0xfffffffe,%d0 /* PLL bypass first */
217 movel %d0,0x180(%a1) /* set PLL register */
226 movel #0x125a40f0,%d0 /* set for 140MHz */
227 movel %d0,0x180(%a1) /* set PLL register */
228 orl #0x1,%d0
[all …]
/arch/m68k/math-emu/
Dfp_cond.S62 move.l %d2,%d0
63 swap %d0
64 fp_get_instr_word %d0,fp_err_ua1
65 lea (-2,%a0,%d0.l),%a0
67 move.l %d2,%d0
68 swap %d0
70 tst.l %d0
79 fp_get_instr_word %d0,fp_err_ua1
80 add.w %d0,%a1
82 printf PDECODE,"d%d,%x\n",2,%d0,%a1
[all …]
Dfp_entry.S50 GET_CURRENT(%d0)
73 tst.l %d0
115 jmp ([0f:w,%pc,%d0.w*4])
125 move.l (PT_OFF_D0+8,%sp),%d0
126 printf PREGISTER,"{d0->%08x}",1,%d0
130 move.l (PT_OFF_D1+8,%sp),%d0
131 printf PREGISTER,"{d1->%08x}",1,%d0
135 move.l (PT_OFF_D2+8,%sp),%d0
136 printf PREGISTER,"{d2->%08x}",1,%d0
140 move.l %d3,%d0
[all …]
Dfp_util.S70 2: clr.l %d0
94 | args: %d0 = source (32-bit long)
98 printf PCONV,"l2e: %p -> %p(",2,%d0,%a0
100 tst.l %d0
104 neg.l %d0
108 move.l %d0,(%a0)+ | set mantissa
125 | args: %d0 = source (single-precision fp value)
129 printf PCONV,"s2e: %p -> %p(",2,%d0,%a0
130 move.l %d0,%d1
131 lsl.l #8,%d0 | shift mantissa
[all …]
Dfp_move.S48 move.w %d0,%d1 | store data size twice in %d1
50 move.w %d0,%d1
53 clr.l %d0
54 move.b (%a0,%d1.w),%d0
55 printf PDECODE,"fmove.%c ",1,%d0
57 printf PDECODE,"fp%d,",1,%d0
75 move.w %d0,%d1
98 move.l %d0,%d1
100 move.w %d2,%d0
102 move.b %d1,%d0
[all …]
Dfp_scan.S67 getuser.b (%a0),%d0,fp_err_ua1,%a0
69 cmp.b #0xf2,%d0 | cpid = 1
71 cmp.b #0xfc,%d0 | cpid = 6
95 printf PDECODE,"f<op>.x fp%d",1,%d0
108 cmp.w #7,%d0
110 move.w %d0,%d1 | store data size twice in %d1
112 move.w %d0,%d1
115 clr.l %d0
116 move.b (%a0,%d1.w),%d0
117 printf PDECODE,"f<op>.%c ",1,%d0
[all …]
/arch/x86/lib/
Dstring_32.c19 int d0, d1, d2; in strcpy() local
24 : "=&S" (d0), "=&D" (d1), "=&a" (d2) in strcpy()
34 int d0, d1, d2, d3; in strncpy() local
44 : "=&S" (d0), "=&D" (d1), "=&c" (d2), "=&a" (d3) in strncpy()
54 int d0, d1, d2, d3; in strcat() local
62 : "=&S" (d0), "=&D" (d1), "=&a" (d2), "=&c" (d3) in strcat()
72 int d0, d1, d2, d3; in strncat() local
85 : "=&S" (d0), "=&D" (d1), "=&a" (d2), "=&c" (d3) in strncat()
96 int d0, d1; in strcmp() local
108 : "=a" (res), "=&S" (d0), "=&D" (d1) in strcmp()
[all …]
/arch/mn10300/lib/
Ddo_csum.S26 mov d0,a0 # buff
39 movbu (a0),d0
41 asl +8,d0
42 add d0,d1
50 movhu (a0+),d0
51 add d0,d1
65 mov (a0+),d0
69 add d0,d1
73 mov (a0+),d0
77 addc d0,d1
[all …]
Dmemmove.S26 cmp d1,d0
31 mov d0,(12,sp)
34 add d0,d2,a0 # dst end
36 mov d0,e3 # the return value
42 or d0,d1,d3
56 mov (a1),d0
58 mov d0,(a0)
63 mov (a1),d0
65 mov d0,(a0)
70 mov (a1),d0
[all …]
/arch/m68k/kernel/
Dhead.S668 movel %a0@,%d0
669 subql #1,%d0
672 dbra %d0,loopx2
686 movel %pc@(m68k_cputype),%d0
695 btst #CPUB_68060,%d0
704 btst #CPUB_68040,%d0
713 btst #CPUB_68020,%d0
739 clrl %d0
759 movel #_PAGE_CACHE040W,%d0
763 movew #_PAGE_CACHE040,%d0
[all …]
/arch/mn10300/mm/
Dcache.inc36 and ~CHCTR_ICEN,d0
37 movhu d0,(a0)
41 movhu (a0),d0
42 btst CHCTR_ICBUSY,d0
46 or CHCTR_ICINV,d0
47 movhu d0,(a0)
51 movhu (a0),d0
52 btst CHCTR_ICBUSY,d0
56 or CHCTR_ICEN,d0
57 movhu d0,(a0)
[all …]
Dcache-inv-by-tag.S70 movhu (a0),d0
71 btst CHCTR_ICEN,d0
92 movhu (a0),d0
93 btst CHCTR_DCEN,d0
118 and ~(PAGE_SIZE-1),d0
121 add d0,d1
157 mov a1,d0
158 and L1_CACHE_TAG_ENTRY,d0
159 add d0,a0 # starting dcache tag RAM
172 movhu (a2),d0
[all …]
Dcache-dbg-flush-by-reg.S35 movhu (CHCTR),d0
36 btst CHCTR_DCEN|CHCTR_ICEN,d0
46 btst CHCTR_DCEN,d0
51 mov (a0),d0
52 btst DCPGCR_DCPGBSY,d0
56 clr d0
57 mov d0,(DCPGMR)
63 mov DCPGCR_DCP,d0
64 mov d0,(a0)
68 mov (a0),d0
[all …]
/arch/m68k/fpsp040/
Dx_store.S41 movel CMDREG3B(%a6),%d0
42 bfextu %d0{#6:#3},%d0 |isolate dest. reg from cmdreg3b
45 moveb (%a1,%d0.w),%d0 |convert reg# to dynamic register mask
50 fmovemx (%a0),%d0 |move to correct register
56 cmpb #0x80,%d0
61 cmpb #0x40,%d0
66 cmpb #0x20,%d0
71 cmpb #0x10,%d0
79 bsrl g_opcls |returns opclass in d0
80 cmpib #3,%d0
[all …]
Dsto_res.S34 bfextu CMDREG1B(%a6){#13:#3},%d0 |extract cos destination
35 cmpib #3,%d0 |check for fp0/fp1 cases
39 subl %d0,%d1 |d1 = 7- (dest. reg. no.)
40 clrl %d0
41 bsetl %d1,%d0 |d0 is dynamic register mask
42 fmovemx (%a7)+,%d0
45 cmpib #0,%d0
47 cmpib #1,%d0
49 cmpib #2,%d0
67 bfextu CMDREG1B(%a6){#6:#3},%d0 |extract destination register
[all …]
Dstanh.S87 movel (%a0),%d0
88 movew 4(%a0),%d0
89 movel %d0,X(%a6)
90 andl #0x7FFFFFFF,%d0
91 cmp2l BOUNDS1(%pc),%d0 | ...2**(-40) < |X| < (5/2)LOG2 ?
97 movel X(%a6),%d0
98 movel %d0,SGN(%a6)
99 andl #0x7FFF0000,%d0
100 addl #0x00010000,%d0 | ...EXPONENT OF 2|X|
101 movel %d0,X(%a6)
[all …]
Dx_operr.S142 cmpl #0x7FFF0000,%d0
157 moveb STAG(%a6),%d0 |test stag for nan
158 andib #0xe0,%d0 |clr all but tag
159 cmpib #0x60,%d0 |check for nan
164 tstl %d0
165 bnes chkwerr |if d0 is true, check for incorrect operr
166 movel #0x80000000,%d0 |store special case result
173 movew FPTEMP_EX(%a6),%d0
174 andw #0x7FFF,%d0 |ignore sign bit
175 cmpw #0x3FFE,%d0 |this is the only possible exponent value
[all …]
/arch/m68k/platform/68360/
Dhead-ram.S114 move.l #_dprbase, %d0
115 andi.l #MCU_SIM_MBAR_BA_MASK, %d0
116 ori.l #MCU_SIM_MBAR_AS_MASK, %d0
117 moves.l %d0, %a0@
140 move.w #16384, %d0
142 subi.w #1, %d0
163 move.l #MCU_SIM_GMR, %d0
164 move.l %d0, GMR
167 move.l #RAMEND, %d0
168 subi.l #__ramstart, %d0
[all …]
/arch/m68k/platform/68328/
Dhead-pilot.S63 moveq #0, %d0
64 movew %d0, 0xfffff618 /* Watchdog off */
101 moveq #0,%d0
102 movew #16384, %d0 /* PLL settle wait loop */
104 subw #1, %d0
120 movel %a0@+, %d0
121 movel %d0, %a1@+
134 movel %a0@+, %d0
135 movel %d0, %a1@+
161 movel %a0@+, %d0
[all …]
Dentry.S52 movel #-ENOSYS,%d0
59 1: movel %d0,%sp@(PT_OFF_D0) /* save the return value */
77 movel %sp@(PT_OFF_ORIG_D0),%d0
84 cmpl #NR_syscalls,%d0
86 lsl #2,%d0
88 movel %a0@(%d0), %a0
90 movel %d0,%sp@(PT_OFF_D0) /* save the return value*/
133 movew %sp@(PT_OFF_FORMATVEC), %d0
134 and #0x3ff, %d0
144 movew %sp@(PT_OFF_FORMATVEC), %d0
[all …]

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