Searched refs:erratum (Results 1 – 7 of 7) sorted by relevance
| /arch/arm/mach-iop33x/include/mach/ |
| D | entry-macro.S | 24 mrceq p6, 0, \irqstat, c14, c0, 0 @ erratum 63 workaround
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| /arch/x86/kernel/cpu/ |
| D | amd.c | 788 bool cpu_has_amd_erratum(const int *erratum) in cpu_has_amd_erratum() argument
791 int osvw_id = *erratum++; in cpu_has_amd_erratum()
821 while ((range = *erratum++)) in cpu_has_amd_erratum()
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| /arch/arm/ |
| D | Kconfig | 1225 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1234 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1250 erratum. For very specific sequences of memory operations, it is
1263 erratum. Any asynchronous access to the L2 cache may encounter a
1275 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1287 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1314 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1316 As a consequence of this erratum, some TLB entries which should be
1328 rare circumstances, due to this erratum, write data can be lost when
1337 (r2p*) erratum. Under very rare conditions, a faulty
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| /arch/powerpc/platforms/8xx/ |
| D | Kconfig | 141 This enables a workaround for erratum CPU15 on MPC8xx chips.
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| /arch/m68k/ifpsp060/ |
| D | CHANGES | 46 4) Beta B.2 version had the following erratum:
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| /arch/powerpc/boot/dts/fsl/ |
| D | mpc8536si-post.dtsi | 173 /* mark compat w/8572 to get some erratum treatment */
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| /arch/powerpc/ |
| D | Kconfig | 754 bool "Enable workaround for MPC826x erratum PCI 9"
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