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Searched refs:reg_src (Results 1 – 14 of 14) sorted by relevance

/arch/arm/plat-samsung/
Dclock-clksrc.c78 u32 clksrc = __raw_readl(sclk->reg_src.reg); in s3c_setparent_clksrc()
79 u32 mask = bit_mask(sclk->reg_src.shift, sclk->reg_src.size); in s3c_setparent_clksrc()
93 clksrc |= src_nr << sclk->reg_src.shift; in s3c_setparent_clksrc()
95 __raw_writel(clksrc, sclk->reg_src.reg); in s3c_setparent_clksrc()
133 u32 mask = bit_mask(clk->reg_src.shift, clk->reg_src.size); in s3c_set_clksrc()
136 if (!clk->reg_src.reg) { in s3c_set_clksrc()
143 clksrc = __raw_readl(clk->reg_src.reg); in s3c_set_clksrc()
145 clksrc >>= clk->reg_src.shift; in s3c_set_clksrc()
183 if (!clksrc->reg_div.reg && !clksrc->reg_src.reg) in s3c_register_clksrc()
192 else if (!clksrc->reg_src.reg) in s3c_register_clksrc()
/arch/arm/mach-s5pv210/
Dclock.c42 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
50 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
58 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
76 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
119 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
136 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
239 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 },
257 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
277 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
625 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
[all …]
/arch/arm/mach-exynos/
Dclock-exynos4210.c64 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
74 .reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
127 exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU; in exynos4210_register_clocks()
128 exynos4_clk_mout_mpll.reg_src.shift = 8; in exynos4210_register_clocks()
129 exynos4_clk_mout_mpll.reg_src.size = 1; in exynos4210_register_clocks()
Dclock-exynos4212.c57 .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
106 exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC; in exynos4212_register_clocks()
107 exynos4_clk_mout_mpll.reg_src.shift = 12; in exynos4212_register_clocks()
108 exynos4_clk_mout_mpll.reg_src.size = 1; in exynos4212_register_clocks()
Dclock-exynos4.c218 .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
234 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
261 .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
328 .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
388 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
397 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
406 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
415 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
436 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
454 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
[all …]
Dclock-exynos5.c137 .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
153 .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
171 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
179 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
187 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
195 .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
215 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
233 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
261 .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
284 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
[all …]
/arch/arm/mach-s5p64x0/
Dclock-s5p6450.c42 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 },
109 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 },
127 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 },
159 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 },
410 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 10, .size = 3 },
422 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
431 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
440 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 30, .size = 2 },
449 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 10, .size = 2 },
458 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 28, .size = 2 },
[all …]
Dclock-s5p6440.c116 .reg_src = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 },
388 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
397 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
406 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
415 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 0, .size = 3 },
428 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
440 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
452 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
463 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
475 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
[all …]
Dclock.c42 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 0, .size = 1 },
51 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 1, .size = 1 },
60 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 2, .size = 1 },
/arch/arm/mach-s5pc100/
Dclock.c57 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
75 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 },
83 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
92 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
100 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
117 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
183 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
225 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
796 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 },
822 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 },
[all …]
/arch/arm/mach-s3c24xx/
Dclock-s3c2416.c70 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 18 },
106 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
123 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
Dcommon-s3c2443.c84 .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 7 },
106 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 6 },
144 .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 3 },
324 .reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 },
417 .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },
/arch/arm/mach-s3c64xx/
Dclock.c447 .reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 },
465 .reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 },
483 .reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 },
700 .reg_src = { .reg = S3C_CLK_SRC, .shift = 5, .size = 2 },
710 .reg_src = { .reg = S3C_CLK_SRC, .shift = 7, .size = 3 },
720 .reg_src = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3 },
730 .reg_src = { .reg = S3C6410_CLK_SRC2, .shift = 0, .size = 3 },
739 .reg_src = { .reg = S3C_CLK_SRC, .shift = 24, .size = 2 },
749 .reg_src = { .reg = NULL, .shift = 0, .size = 0 },
761 .reg_src = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1 },
[all …]
/arch/arm/plat-samsung/include/plat/
Dclock-clksrc.h62 struct clksrc_reg reg_src; member