1 /*
2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * EXYNOS4210 - Clock support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/err.h>
14 #include <linux/clk.h>
15 #include <linux/io.h>
16 #include <linux/syscore_ops.h>
17
18 #include <plat/cpu-freq.h>
19 #include <plat/clock.h>
20 #include <plat/cpu.h>
21 #include <plat/pll.h>
22 #include <plat/s5p-clock.h>
23 #include <plat/clock-clksrc.h>
24 #include <plat/pm.h>
25
26 #include <mach/hardware.h>
27 #include <mach/map.h>
28 #include <mach/regs-clock.h>
29
30 #include "common.h"
31 #include "clock-exynos4.h"
32
33 #ifdef CONFIG_PM_SLEEP
34 static struct sleep_save exynos4210_clock_save[] = {
35 SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
36 SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
37 SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
38 SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
39 SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
40 SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
41 SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
42 SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
43 };
44 #endif
45
46 static struct clksrc_clk *sysclks[] = {
47 /* nothing here yet */
48 };
49
exynos4_clksrc_mask_lcd1_ctrl(struct clk * clk,int enable)50 static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
51 {
52 return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
53 }
54
55 static struct clksrc_clk clksrcs[] = {
56 {
57 .clk = {
58 .name = "sclk_sata",
59 .id = -1,
60 .enable = exynos4_clksrc_mask_fsys_ctrl,
61 .ctrlbit = (1 << 24),
62 },
63 .sources = &exynos4_clkset_mout_corebus,
64 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
65 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
66 }, {
67 .clk = {
68 .name = "sclk_fimd",
69 .devname = "exynos4-fb.1",
70 .enable = exynos4_clksrc_mask_lcd1_ctrl,
71 .ctrlbit = (1 << 0),
72 },
73 .sources = &exynos4_clkset_group,
74 .reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
75 .reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
76 },
77 };
78
79 static struct clk init_clocks_off[] = {
80 {
81 .name = "sataphy",
82 .id = -1,
83 .parent = &exynos4_clk_aclk_133.clk,
84 .enable = exynos4_clk_ip_fsys_ctrl,
85 .ctrlbit = (1 << 3),
86 }, {
87 .name = "sata",
88 .id = -1,
89 .parent = &exynos4_clk_aclk_133.clk,
90 .enable = exynos4_clk_ip_fsys_ctrl,
91 .ctrlbit = (1 << 10),
92 }, {
93 .name = "fimd",
94 .devname = "exynos4-fb.1",
95 .enable = exynos4_clk_ip_lcd1_ctrl,
96 .ctrlbit = (1 << 0),
97 },
98 };
99
100 #ifdef CONFIG_PM_SLEEP
exynos4210_clock_suspend(void)101 static int exynos4210_clock_suspend(void)
102 {
103 s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
104
105 return 0;
106 }
107
exynos4210_clock_resume(void)108 static void exynos4210_clock_resume(void)
109 {
110 s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
111 }
112
113 #else
114 #define exynos4210_clock_suspend NULL
115 #define exynos4210_clock_resume NULL
116 #endif
117
118 static struct syscore_ops exynos4210_clock_syscore_ops = {
119 .suspend = exynos4210_clock_suspend,
120 .resume = exynos4210_clock_resume,
121 };
122
exynos4210_register_clocks(void)123 void __init exynos4210_register_clocks(void)
124 {
125 int ptr;
126
127 exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
128 exynos4_clk_mout_mpll.reg_src.shift = 8;
129 exynos4_clk_mout_mpll.reg_src.size = 1;
130
131 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
132 s3c_register_clksrc(sysclks[ptr], 1);
133
134 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
135
136 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
137 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
138
139 register_syscore_ops(&exynos4210_clock_syscore_ops);
140 }
141