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Searched refs:I915_WRITE (Results 1 – 22 of 22) sorted by relevance

/drivers/gpu/drm/i915/
Di915_suspend.c91 I915_WRITE(reg + (i << 2), array[i]); in i915_restore_palette()
427 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]); in i915_restore_modeset_reg()
429 I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]); in i915_restore_modeset_reg()
451 I915_WRITE(PCH_DREF_CONTROL, dev_priv->savePCH_DREF_CONTROL); in i915_restore_modeset_reg()
452 I915_WRITE(DISP_ARB_CTL, dev_priv->saveDISP_ARB_CTL); in i915_restore_modeset_reg()
458 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A & in i915_restore_modeset_reg()
463 I915_WRITE(fpa0_reg, dev_priv->saveFPA0); in i915_restore_modeset_reg()
464 I915_WRITE(fpa1_reg, dev_priv->saveFPA1); in i915_restore_modeset_reg()
466 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A); in i915_restore_modeset_reg()
470 I915_WRITE(_DPLL_A_MD, dev_priv->saveDPLL_A_MD); in i915_restore_modeset_reg()
[all …]
Dintel_display.c753 I915_WRITE(pipestat_reg, in intel_wait_for_vblank()
1180 I915_WRITE(reg, val); in intel_enable_pll()
1183 I915_WRITE(reg, val); in intel_enable_pll()
1186 I915_WRITE(reg, val); in intel_enable_pll()
1215 I915_WRITE(reg, val); in intel_disable_pll()
1245 I915_WRITE(reg, val); in intel_enable_pch_pll()
1278 I915_WRITE(reg, val); in intel_disable_pch_pll()
1323 I915_WRITE(reg, val | TRANS_ENABLE); in intel_enable_transcoder()
1344 I915_WRITE(reg, val); in intel_disable_transcoder()
1391 I915_WRITE(reg, val | PIPECONF_ENABLE); in intel_enable_pipe()
[all …]
Di915_irq.c73 I915_WRITE(DEIMR, dev_priv->irq_mask); in ironlake_enable_display_irq()
83 I915_WRITE(DEIMR, dev_priv->irq_mask); in ironlake_disable_display_irq()
96 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); in i915_enable_pipestat()
108 I915_WRITE(reg, dev_priv->pipestat[pipe]); in i915_disable_pipestat()
386 I915_WRITE(GEN6_PMIMR, 0); in gen6_pm_rps_work()
404 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, in gen6_pm_rps_work()
410 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, in gen6_pm_rps_work()
444 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir); in gen6_queue_rps_work()
503 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); in ivybridge_irq_handler()
560 I915_WRITE(SDEIIR, pch_iir); in ivybridge_irq_handler()
[all …]
Dintel_sprite.c123 I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); in ivb_update_plane()
124 I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); in ivb_update_plane()
126 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); in ivb_update_plane()
131 I915_WRITE(SPRLINOFF(pipe), offset); in ivb_update_plane()
133 I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); in ivb_update_plane()
134 I915_WRITE(SPRSCALE(pipe), sprscale); in ivb_update_plane()
135 I915_WRITE(SPRCTL(pipe), sprctl); in ivb_update_plane()
136 I915_WRITE(SPRSURF(pipe), obj->gtt_offset); in ivb_update_plane()
148 I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE); in ivb_disable_plane()
150 I915_WRITE(SPRSCALE(pipe), 0); in ivb_disable_plane()
[all …]
Dintel_tv.c847 I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE); in intel_tv_dpms()
852 I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE); in intel_tv_dpms()
1040 I915_WRITE(TV_H_CTL_1, hctl1); in intel_tv_mode_set()
1041 I915_WRITE(TV_H_CTL_2, hctl2); in intel_tv_mode_set()
1042 I915_WRITE(TV_H_CTL_3, hctl3); in intel_tv_mode_set()
1043 I915_WRITE(TV_V_CTL_1, vctl1); in intel_tv_mode_set()
1044 I915_WRITE(TV_V_CTL_2, vctl2); in intel_tv_mode_set()
1045 I915_WRITE(TV_V_CTL_3, vctl3); in intel_tv_mode_set()
1046 I915_WRITE(TV_V_CTL_4, vctl4); in intel_tv_mode_set()
1047 I915_WRITE(TV_V_CTL_5, vctl5); in intel_tv_mode_set()
[all …]
Dintel_crt.c88 I915_WRITE(reg, temp); in intel_crt_dpms()
146 I915_WRITE(dpll_md_reg, in intel_crt_mode_set()
165 I915_WRITE(BCLRPAT(intel_crtc->pipe), 0); in intel_crt_mode_set()
167 I915_WRITE(adpa_reg, adpa); in intel_crt_mode_set()
192 I915_WRITE(PCH_ADPA, adpa); in intel_ironlake_crt_detect_hotplug()
199 I915_WRITE(PCH_ADPA, save_adpa); in intel_ironlake_crt_detect_hotplug()
248 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); in intel_crt_detect_hotplug()
261 I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); in intel_crt_detect_hotplug()
264 I915_WRITE(PORT_HOTPLUG_EN, orig); in intel_crt_detect_hotplug()
379 I915_WRITE(bclrpat_reg, 0x500050); in intel_crt_load_detect()
[all …]
Dintel_i2c.c53 I915_WRITE(PCH_GMBUS0, 0); in intel_i2c_reset()
55 I915_WRITE(GMBUS0, 0); in intel_i2c_reset()
71 I915_WRITE(DSPCLK_GATE_D, val); in intel_i2c_quirk_set()
224 I915_WRITE(GMBUS0 + reg_offset, bus->reg0); in gmbus_xfer()
231 I915_WRITE(GMBUS1 + reg_offset, in gmbus_xfer()
260 I915_WRITE(GMBUS3 + reg_offset, val); in gmbus_xfer()
261 I915_WRITE(GMBUS1 + reg_offset, in gmbus_xfer()
280 I915_WRITE(GMBUS3 + reg_offset, val); in gmbus_xfer()
298 I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT); in gmbus_xfer()
299 I915_WRITE(GMBUS1 + reg_offset, 0); in gmbus_xfer()
[all …]
Dintel_hdmi.c139 I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | val | port | flags); in i9xx_write_infoframe()
143 I915_WRITE(VIDEO_DIP_DATA, *data); in i9xx_write_infoframe()
150 I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | val | port | flags); in i9xx_write_infoframe()
172 I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags); in ironlake_write_infoframe()
176 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); in ironlake_write_infoframe()
183 I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags); in ironlake_write_infoframe()
265 I915_WRITE(intel_hdmi->sdvox_reg, sdvox); in intel_hdmi_mode_set()
289 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); in intel_hdmi_dpms()
299 I915_WRITE(intel_hdmi->sdvox_reg, temp); in intel_hdmi_dpms()
306 I915_WRITE(intel_hdmi->sdvox_reg, temp); in intel_hdmi_dpms()
[all …]
Dintel_dp.c414 I915_WRITE(ch_data + i, in intel_dp_aux_ch()
418 I915_WRITE(ch_ctl, in intel_dp_aux_ch()
435 I915_WRITE(ch_ctl, in intel_dp_aux_ch()
820 I915_WRITE(TRANSDATA_M1(pipe), in intel_dp_set_m_n()
823 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); in intel_dp_set_m_n()
824 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m); in intel_dp_set_m_n()
825 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n); in intel_dp_set_m_n()
827 I915_WRITE(PIPE_GMCH_DATA_M(pipe), in intel_dp_set_m_n()
830 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); in intel_dp_set_m_n()
831 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); in intel_dp_set_m_n()
[all …]
Dintel_ringbuffer.h11 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
14 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
17 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
20 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
23 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
Dintel_lvds.c87 I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN); in intel_lvds_enable()
100 I915_WRITE(PFIT_PGM_RATIOS, intel_lvds->pfit_pgm_ratios); in intel_lvds_enable()
101 I915_WRITE(PFIT_CONTROL, intel_lvds->pfit_control); in intel_lvds_enable()
105 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); in intel_lvds_enable()
131 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); in intel_lvds_disable()
136 I915_WRITE(PFIT_CONTROL, 0); in intel_lvds_disable()
140 I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN); in intel_lvds_disable()
288 I915_WRITE(BCLRPAT(pipe), 0); in intel_lvds_mode_fixup()
1103 I915_WRITE(BLC_PWM_CPU_CTL2, pwm & ~PWM_ENABLE); in intel_lvds_init()
1108 I915_WRITE(BLC_PWM_CPU_CTL2, pwm | PWM_ENABLE); in intel_lvds_init()
[all …]
Dintel_panel.c141 I915_WRITE(BLC_PWM_PCH_CTL2, in i915_read_blc_pwm_ctl()
151 I915_WRITE(BLC_PWM_CTL, in i915_read_blc_pwm_ctl()
153 I915_WRITE(BLC_PWM_CTL2, in i915_read_blc_pwm_ctl()
220 I915_WRITE(BLC_PWM_CPU_CTL, val | level); in intel_pch_panel_set_backlight()
246 I915_WRITE(BLC_PWM_CTL, tmp | level); in intel_panel_actually_set_backlight()
Dintel_dvo.c108 I915_WRITE(dvo_reg, temp | DVO_ENABLE); in intel_dvo_dpms()
113 I915_WRITE(dvo_reg, temp & ~DVO_ENABLE); in intel_dvo_dpms()
211 I915_WRITE(dpll_reg, I915_READ(dpll_reg) | DPLL_DVO_HIGH_SPEED); in intel_dvo_mode_set()
216 I915_WRITE(dvo_srcdim_reg, in intel_dvo_mode_set()
220 I915_WRITE(dvo_reg, dvo_val); in intel_dvo_mode_set()
Dintel_ringbuffer.c399 I915_WRITE(MI_MODE, mode); in init_render_ring()
401 I915_WRITE(GFX_MODE_GEN7, in init_render_ring()
419 I915_WRITE(CACHE_MODE_0, in init_render_ring()
424 I915_WRITE(INSTPM, in init_render_ring()
673 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); in ironlake_enable_irq()
681 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); in ironlake_disable_irq()
689 I915_WRITE(IMR, dev_priv->irq_mask); in i915_enable_irq()
697 I915_WRITE(IMR, dev_priv->irq_mask); in i915_disable_irq()
768 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); in intel_ring_setup_status_page()
774 I915_WRITE(reg, in intel_ring_setup_status_page()
[all …]
Di915_drv.c590 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830); in i8xx_do_reset()
594 I915_WRITE(DEBUG_RESET_I830, in i8xx_do_reset()
601 I915_WRITE(DEBUG_RESET_I830, 0); in i8xx_do_reset()
607 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830); in i8xx_do_reset()
639 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1); in ironlake_do_reset()
Dintel_overlay.c1385 I915_WRITE(OGAMC0, attrs->gamma0); in intel_overlay_attrs()
1386 I915_WRITE(OGAMC1, attrs->gamma1); in intel_overlay_attrs()
1387 I915_WRITE(OGAMC2, attrs->gamma2); in intel_overlay_attrs()
1388 I915_WRITE(OGAMC3, attrs->gamma3); in intel_overlay_attrs()
1389 I915_WRITE(OGAMC4, attrs->gamma4); in intel_overlay_attrs()
1390 I915_WRITE(OGAMC5, attrs->gamma5); in intel_overlay_attrs()
Di915_gem.c2308 I915_WRITE(fence_reg, val); in i915_write_fence_reg()
2351 I915_WRITE(FENCE_REG_830_0 + regnum * 4, val); in i830_write_fence_reg()
2639 I915_WRITE(fence_reg, 0); in i915_gem_clear_fence_reg()
3749 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | in i915_gem_init_swizzling()
3755 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); in i915_gem_init_swizzling()
3757 I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_SNB)); in i915_gem_init_swizzling()
3759 I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_IVB)); in i915_gem_init_swizzling()
3798 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | in i915_gem_init_ppgtt()
3800 I915_WRITE(GFX_MODE, GFX_MODE_ENABLE(GFX_PPGTT_ENABLE)); in i915_gem_init_ppgtt()
3802 I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B); in i915_gem_init_ppgtt()
[all …]
Di915_dma.c55 I915_WRITE(HWS_PGA, addr); in i915_write_hws_pga()
104 I915_WRITE(HWS_PGA, 0x1ffff000); in i915_free_hws()
881 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr); in i915_set_status_page()
1112 I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start); in i915_setup_compression()
1114 I915_WRITE(DPFC_CB_BASE, compressed_fb->start); in i915_setup_compression()
1116 I915_WRITE(FBC_CFB_BASE, cfb_base); in i915_setup_compression()
1117 I915_WRITE(FBC_LL_BASE, ll_base); in i915_setup_compression()
Dintel_bios.c756 I915_WRITE(PP_ON_DELAYS, 0x019007d0); in intel_setup_bios()
759 I915_WRITE(PP_OFF_DELAYS, 0x015e07d0); in intel_setup_bios()
Di915_debugfs.c1268 I915_WRITE(GEN6_PCODE_DATA, gpu_freq); in i915_ring_freq_table()
1269 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | in i915_ring_freq_table()
1684 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); in i915_cache_sharing_write()
Dintel_sdvo.c238 I915_WRITE(intel_sdvo->sdvo_reg, val); in intel_sdvo_write_sdvox()
255 I915_WRITE(SDVOB, bval); in intel_sdvo_write_sdvox()
257 I915_WRITE(SDVOC, cval); in intel_sdvo_write_sdvox()
Di915_drv.h1486 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) macro