1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #include <linux/sysrq.h>
30 #include <linux/slab.h>
31 #include "drmP.h"
32 #include "drm.h"
33 #include "i915_drm.h"
34 #include "i915_drv.h"
35 #include "i915_trace.h"
36 #include "intel_drv.h"
37
38 #define MAX_NOPID ((u32)~0)
39
40 /**
41 * Interrupts that are always left unmasked.
42 *
43 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
44 * we leave them always unmasked in IMR and then control enabling them through
45 * PIPESTAT alone.
46 */
47 #define I915_INTERRUPT_ENABLE_FIX \
48 (I915_ASLE_INTERRUPT | \
49 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
50 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
51 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \
52 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \
53 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
54
55 /** Interrupts that we mask and unmask at runtime. */
56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
57
58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
59 PIPE_VBLANK_INTERRUPT_STATUS)
60
61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
62 PIPE_VBLANK_INTERRUPT_ENABLE)
63
64 #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
65 DRM_I915_VBLANK_PIPE_B)
66
67 /* For display hotplug interrupt */
68 static void
ironlake_enable_display_irq(drm_i915_private_t * dev_priv,u32 mask)69 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
70 {
71 if ((dev_priv->irq_mask & mask) != 0) {
72 dev_priv->irq_mask &= ~mask;
73 I915_WRITE(DEIMR, dev_priv->irq_mask);
74 POSTING_READ(DEIMR);
75 }
76 }
77
78 static inline void
ironlake_disable_display_irq(drm_i915_private_t * dev_priv,u32 mask)79 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
80 {
81 if ((dev_priv->irq_mask & mask) != mask) {
82 dev_priv->irq_mask |= mask;
83 I915_WRITE(DEIMR, dev_priv->irq_mask);
84 POSTING_READ(DEIMR);
85 }
86 }
87
88 void
i915_enable_pipestat(drm_i915_private_t * dev_priv,int pipe,u32 mask)89 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
90 {
91 if ((dev_priv->pipestat[pipe] & mask) != mask) {
92 u32 reg = PIPESTAT(pipe);
93
94 dev_priv->pipestat[pipe] |= mask;
95 /* Enable the interrupt, clear any pending status */
96 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
97 POSTING_READ(reg);
98 }
99 }
100
101 void
i915_disable_pipestat(drm_i915_private_t * dev_priv,int pipe,u32 mask)102 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
103 {
104 if ((dev_priv->pipestat[pipe] & mask) != 0) {
105 u32 reg = PIPESTAT(pipe);
106
107 dev_priv->pipestat[pipe] &= ~mask;
108 I915_WRITE(reg, dev_priv->pipestat[pipe]);
109 POSTING_READ(reg);
110 }
111 }
112
113 /**
114 * intel_enable_asle - enable ASLE interrupt for OpRegion
115 */
intel_enable_asle(struct drm_device * dev)116 void intel_enable_asle(struct drm_device *dev)
117 {
118 drm_i915_private_t *dev_priv = dev->dev_private;
119 unsigned long irqflags;
120
121 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
122
123 if (HAS_PCH_SPLIT(dev))
124 ironlake_enable_display_irq(dev_priv, DE_GSE);
125 else {
126 i915_enable_pipestat(dev_priv, 1,
127 PIPE_LEGACY_BLC_EVENT_ENABLE);
128 if (INTEL_INFO(dev)->gen >= 4)
129 i915_enable_pipestat(dev_priv, 0,
130 PIPE_LEGACY_BLC_EVENT_ENABLE);
131 }
132
133 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
134 }
135
136 /**
137 * i915_pipe_enabled - check if a pipe is enabled
138 * @dev: DRM device
139 * @pipe: pipe to check
140 *
141 * Reading certain registers when the pipe is disabled can hang the chip.
142 * Use this routine to make sure the PLL is running and the pipe is active
143 * before reading such registers if unsure.
144 */
145 static int
i915_pipe_enabled(struct drm_device * dev,int pipe)146 i915_pipe_enabled(struct drm_device *dev, int pipe)
147 {
148 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
149 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
150 }
151
152 /* Called from drm generic code, passed a 'crtc', which
153 * we use as a pipe index
154 */
i915_get_vblank_counter(struct drm_device * dev,int pipe)155 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
156 {
157 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
158 unsigned long high_frame;
159 unsigned long low_frame;
160 u32 high1, high2, low;
161
162 if (!i915_pipe_enabled(dev, pipe)) {
163 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
164 "pipe %c\n", pipe_name(pipe));
165 return 0;
166 }
167
168 high_frame = PIPEFRAME(pipe);
169 low_frame = PIPEFRAMEPIXEL(pipe);
170
171 /*
172 * High & low register fields aren't synchronized, so make sure
173 * we get a low value that's stable across two reads of the high
174 * register.
175 */
176 do {
177 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
178 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
179 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
180 } while (high1 != high2);
181
182 high1 >>= PIPE_FRAME_HIGH_SHIFT;
183 low >>= PIPE_FRAME_LOW_SHIFT;
184 return (high1 << 8) | low;
185 }
186
gm45_get_vblank_counter(struct drm_device * dev,int pipe)187 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
188 {
189 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
190 int reg = PIPE_FRMCOUNT_GM45(pipe);
191
192 if (!i915_pipe_enabled(dev, pipe)) {
193 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
194 "pipe %c\n", pipe_name(pipe));
195 return 0;
196 }
197
198 return I915_READ(reg);
199 }
200
i915_get_crtc_scanoutpos(struct drm_device * dev,int pipe,int * vpos,int * hpos)201 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
202 int *vpos, int *hpos)
203 {
204 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
205 u32 vbl = 0, position = 0;
206 int vbl_start, vbl_end, htotal, vtotal;
207 bool in_vbl = true;
208 int ret = 0;
209
210 if (!i915_pipe_enabled(dev, pipe)) {
211 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
212 "pipe %c\n", pipe_name(pipe));
213 return 0;
214 }
215
216 /* Get vtotal. */
217 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
218
219 if (INTEL_INFO(dev)->gen >= 4) {
220 /* No obvious pixelcount register. Only query vertical
221 * scanout position from Display scan line register.
222 */
223 position = I915_READ(PIPEDSL(pipe));
224
225 /* Decode into vertical scanout position. Don't have
226 * horizontal scanout position.
227 */
228 *vpos = position & 0x1fff;
229 *hpos = 0;
230 } else {
231 /* Have access to pixelcount since start of frame.
232 * We can split this into vertical and horizontal
233 * scanout position.
234 */
235 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
236
237 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
238 *vpos = position / htotal;
239 *hpos = position - (*vpos * htotal);
240 }
241
242 /* Query vblank area. */
243 vbl = I915_READ(VBLANK(pipe));
244
245 /* Test position against vblank region. */
246 vbl_start = vbl & 0x1fff;
247 vbl_end = (vbl >> 16) & 0x1fff;
248
249 if ((*vpos < vbl_start) || (*vpos > vbl_end))
250 in_vbl = false;
251
252 /* Inside "upper part" of vblank area? Apply corrective offset: */
253 if (in_vbl && (*vpos >= vbl_start))
254 *vpos = *vpos - vtotal;
255
256 /* Readouts valid? */
257 if (vbl > 0)
258 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
259
260 /* In vblank? */
261 if (in_vbl)
262 ret |= DRM_SCANOUTPOS_INVBL;
263
264 return ret;
265 }
266
i915_get_vblank_timestamp(struct drm_device * dev,int pipe,int * max_error,struct timeval * vblank_time,unsigned flags)267 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
268 int *max_error,
269 struct timeval *vblank_time,
270 unsigned flags)
271 {
272 struct drm_i915_private *dev_priv = dev->dev_private;
273 struct drm_crtc *crtc;
274
275 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
276 DRM_ERROR("Invalid crtc %d\n", pipe);
277 return -EINVAL;
278 }
279
280 /* Get drm_crtc to timestamp: */
281 crtc = intel_get_crtc_for_pipe(dev, pipe);
282 if (crtc == NULL) {
283 DRM_ERROR("Invalid crtc %d\n", pipe);
284 return -EINVAL;
285 }
286
287 if (!crtc->enabled) {
288 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
289 return -EBUSY;
290 }
291
292 /* Helper routine in DRM core does all the work: */
293 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
294 vblank_time, flags,
295 crtc);
296 }
297
298 /*
299 * Handle hotplug events outside the interrupt handler proper.
300 */
i915_hotplug_work_func(struct work_struct * work)301 static void i915_hotplug_work_func(struct work_struct *work)
302 {
303 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
304 hotplug_work);
305 struct drm_device *dev = dev_priv->dev;
306 struct drm_mode_config *mode_config = &dev->mode_config;
307 struct intel_encoder *encoder;
308
309 mutex_lock(&mode_config->mutex);
310 DRM_DEBUG_KMS("running encoder hotplug functions\n");
311
312 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
313 if (encoder->hot_plug)
314 encoder->hot_plug(encoder);
315
316 mutex_unlock(&mode_config->mutex);
317
318 /* Just fire off a uevent and let userspace tell us what to do */
319 drm_helper_hpd_irq_event(dev);
320 }
321
i915_handle_rps_change(struct drm_device * dev)322 static void i915_handle_rps_change(struct drm_device *dev)
323 {
324 drm_i915_private_t *dev_priv = dev->dev_private;
325 u32 busy_up, busy_down, max_avg, min_avg;
326 u8 new_delay = dev_priv->cur_delay;
327
328 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
329 busy_up = I915_READ(RCPREVBSYTUPAVG);
330 busy_down = I915_READ(RCPREVBSYTDNAVG);
331 max_avg = I915_READ(RCBMAXAVG);
332 min_avg = I915_READ(RCBMINAVG);
333
334 /* Handle RCS change request from hw */
335 if (busy_up > max_avg) {
336 if (dev_priv->cur_delay != dev_priv->max_delay)
337 new_delay = dev_priv->cur_delay - 1;
338 if (new_delay < dev_priv->max_delay)
339 new_delay = dev_priv->max_delay;
340 } else if (busy_down < min_avg) {
341 if (dev_priv->cur_delay != dev_priv->min_delay)
342 new_delay = dev_priv->cur_delay + 1;
343 if (new_delay > dev_priv->min_delay)
344 new_delay = dev_priv->min_delay;
345 }
346
347 if (ironlake_set_drps(dev, new_delay))
348 dev_priv->cur_delay = new_delay;
349
350 return;
351 }
352
notify_ring(struct drm_device * dev,struct intel_ring_buffer * ring)353 static void notify_ring(struct drm_device *dev,
354 struct intel_ring_buffer *ring)
355 {
356 struct drm_i915_private *dev_priv = dev->dev_private;
357 u32 seqno;
358
359 if (ring->obj == NULL)
360 return;
361
362 seqno = ring->get_seqno(ring);
363 trace_i915_gem_request_complete(ring, seqno);
364
365 ring->irq_seqno = seqno;
366 wake_up_all(&ring->irq_queue);
367 if (i915_enable_hangcheck) {
368 dev_priv->hangcheck_count = 0;
369 mod_timer(&dev_priv->hangcheck_timer,
370 jiffies +
371 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
372 }
373 }
374
gen6_pm_rps_work(struct work_struct * work)375 static void gen6_pm_rps_work(struct work_struct *work)
376 {
377 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
378 rps_work);
379 u8 new_delay = dev_priv->cur_delay;
380 u32 pm_iir, pm_imr;
381
382 spin_lock_irq(&dev_priv->rps_lock);
383 pm_iir = dev_priv->pm_iir;
384 dev_priv->pm_iir = 0;
385 pm_imr = I915_READ(GEN6_PMIMR);
386 I915_WRITE(GEN6_PMIMR, 0);
387 spin_unlock_irq(&dev_priv->rps_lock);
388
389 if (!pm_iir)
390 return;
391
392 mutex_lock(&dev_priv->dev->struct_mutex);
393 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
394 if (dev_priv->cur_delay != dev_priv->max_delay)
395 new_delay = dev_priv->cur_delay + 1;
396 if (new_delay > dev_priv->max_delay)
397 new_delay = dev_priv->max_delay;
398 } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
399 gen6_gt_force_wake_get(dev_priv);
400 if (dev_priv->cur_delay != dev_priv->min_delay)
401 new_delay = dev_priv->cur_delay - 1;
402 if (new_delay < dev_priv->min_delay) {
403 new_delay = dev_priv->min_delay;
404 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
405 I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
406 ((new_delay << 16) & 0x3f0000));
407 } else {
408 /* Make sure we continue to get down interrupts
409 * until we hit the minimum frequency */
410 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
411 I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
412 }
413 gen6_gt_force_wake_put(dev_priv);
414 }
415
416 gen6_set_rps(dev_priv->dev, new_delay);
417 dev_priv->cur_delay = new_delay;
418
419 /*
420 * rps_lock not held here because clearing is non-destructive. There is
421 * an *extremely* unlikely race with gen6_rps_enable() that is prevented
422 * by holding struct_mutex for the duration of the write.
423 */
424 mutex_unlock(&dev_priv->dev->struct_mutex);
425 }
426
gen6_queue_rps_work(struct drm_i915_private * dev_priv,u32 pm_iir)427 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
428 u32 pm_iir)
429 {
430 unsigned long flags;
431
432 /*
433 * IIR bits should never already be set because IMR should
434 * prevent an interrupt from being shown in IIR. The warning
435 * displays a case where we've unsafely cleared
436 * dev_priv->pm_iir. Although missing an interrupt of the same
437 * type is not a problem, it displays a problem in the logic.
438 *
439 * The mask bit in IMR is cleared by rps_work.
440 */
441
442 spin_lock_irqsave(&dev_priv->rps_lock, flags);
443 dev_priv->pm_iir |= pm_iir;
444 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
445 POSTING_READ(GEN6_PMIMR);
446 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
447
448 queue_work(dev_priv->wq, &dev_priv->rps_work);
449 }
450
pch_irq_handler(struct drm_device * dev,u32 pch_iir)451 static void pch_irq_handler(struct drm_device *dev, u32 pch_iir)
452 {
453 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
454 int pipe;
455
456 if (pch_iir & SDE_AUDIO_POWER_MASK)
457 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
458 (pch_iir & SDE_AUDIO_POWER_MASK) >>
459 SDE_AUDIO_POWER_SHIFT);
460
461 if (pch_iir & SDE_GMBUS)
462 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
463
464 if (pch_iir & SDE_AUDIO_HDCP_MASK)
465 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
466
467 if (pch_iir & SDE_AUDIO_TRANS_MASK)
468 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
469
470 if (pch_iir & SDE_POISON)
471 DRM_ERROR("PCH poison interrupt\n");
472
473 if (pch_iir & SDE_FDI_MASK)
474 for_each_pipe(pipe)
475 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
476 pipe_name(pipe),
477 I915_READ(FDI_RX_IIR(pipe)));
478
479 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
480 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
481
482 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
483 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
484
485 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
486 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
487 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
488 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
489 }
490
ivybridge_irq_handler(DRM_IRQ_ARGS)491 static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
492 {
493 struct drm_device *dev = (struct drm_device *) arg;
494 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
495 int ret = IRQ_NONE;
496 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
497 struct drm_i915_master_private *master_priv;
498
499 atomic_inc(&dev_priv->irq_received);
500
501 /* disable master interrupt before clearing iir */
502 de_ier = I915_READ(DEIER);
503 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
504 POSTING_READ(DEIER);
505
506 de_iir = I915_READ(DEIIR);
507 gt_iir = I915_READ(GTIIR);
508 pch_iir = I915_READ(SDEIIR);
509 pm_iir = I915_READ(GEN6_PMIIR);
510
511 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0)
512 goto done;
513
514 ret = IRQ_HANDLED;
515
516 if (dev->primary->master) {
517 master_priv = dev->primary->master->driver_priv;
518 if (master_priv->sarea_priv)
519 master_priv->sarea_priv->last_dispatch =
520 READ_BREADCRUMB(dev_priv);
521 }
522
523 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
524 notify_ring(dev, &dev_priv->ring[RCS]);
525 if (gt_iir & GT_GEN6_BSD_USER_INTERRUPT)
526 notify_ring(dev, &dev_priv->ring[VCS]);
527 if (gt_iir & GT_BLT_USER_INTERRUPT)
528 notify_ring(dev, &dev_priv->ring[BCS]);
529
530 if (de_iir & DE_GSE_IVB)
531 intel_opregion_gse_intr(dev);
532
533 if (de_iir & DE_PIPEA_VBLANK_IVB)
534 drm_handle_vblank(dev, 0);
535
536 if (de_iir & DE_PIPEB_VBLANK_IVB)
537 drm_handle_vblank(dev, 1);
538
539 if (de_iir & DE_PLANEA_FLIP_DONE_IVB) {
540 intel_prepare_page_flip(dev, 0);
541 intel_finish_page_flip_plane(dev, 0);
542 }
543
544 if (de_iir & DE_PLANEB_FLIP_DONE_IVB) {
545 intel_prepare_page_flip(dev, 1);
546 intel_finish_page_flip_plane(dev, 1);
547 }
548
549 /* check event from PCH */
550 if (de_iir & DE_PCH_EVENT_IVB) {
551 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
552 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
553 pch_irq_handler(dev, pch_iir);
554 }
555
556 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
557 gen6_queue_rps_work(dev_priv, pm_iir);
558
559 /* should clear PCH hotplug event before clear CPU irq */
560 I915_WRITE(SDEIIR, pch_iir);
561 I915_WRITE(GTIIR, gt_iir);
562 I915_WRITE(DEIIR, de_iir);
563 I915_WRITE(GEN6_PMIIR, pm_iir);
564
565 done:
566 I915_WRITE(DEIER, de_ier);
567 POSTING_READ(DEIER);
568
569 return ret;
570 }
571
ironlake_irq_handler(DRM_IRQ_ARGS)572 static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
573 {
574 struct drm_device *dev = (struct drm_device *) arg;
575 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
576 int ret = IRQ_NONE;
577 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
578 u32 hotplug_mask;
579 struct drm_i915_master_private *master_priv;
580 u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
581
582 atomic_inc(&dev_priv->irq_received);
583
584 if (IS_GEN6(dev))
585 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
586
587 /* disable master interrupt before clearing iir */
588 de_ier = I915_READ(DEIER);
589 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
590 POSTING_READ(DEIER);
591
592 de_iir = I915_READ(DEIIR);
593 gt_iir = I915_READ(GTIIR);
594 pch_iir = I915_READ(SDEIIR);
595 pm_iir = I915_READ(GEN6_PMIIR);
596
597 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
598 (!IS_GEN6(dev) || pm_iir == 0))
599 goto done;
600
601 if (HAS_PCH_CPT(dev))
602 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
603 else
604 hotplug_mask = SDE_HOTPLUG_MASK;
605
606 ret = IRQ_HANDLED;
607
608 if (dev->primary->master) {
609 master_priv = dev->primary->master->driver_priv;
610 if (master_priv->sarea_priv)
611 master_priv->sarea_priv->last_dispatch =
612 READ_BREADCRUMB(dev_priv);
613 }
614
615 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
616 notify_ring(dev, &dev_priv->ring[RCS]);
617 if (gt_iir & bsd_usr_interrupt)
618 notify_ring(dev, &dev_priv->ring[VCS]);
619 if (gt_iir & GT_BLT_USER_INTERRUPT)
620 notify_ring(dev, &dev_priv->ring[BCS]);
621
622 if (de_iir & DE_GSE)
623 intel_opregion_gse_intr(dev);
624
625 if (de_iir & DE_PIPEA_VBLANK)
626 drm_handle_vblank(dev, 0);
627
628 if (de_iir & DE_PIPEB_VBLANK)
629 drm_handle_vblank(dev, 1);
630
631 if (de_iir & DE_PLANEA_FLIP_DONE) {
632 intel_prepare_page_flip(dev, 0);
633 intel_finish_page_flip_plane(dev, 0);
634 }
635
636 if (de_iir & DE_PLANEB_FLIP_DONE) {
637 intel_prepare_page_flip(dev, 1);
638 intel_finish_page_flip_plane(dev, 1);
639 }
640
641 /* check event from PCH */
642 if (de_iir & DE_PCH_EVENT) {
643 if (pch_iir & hotplug_mask)
644 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
645 pch_irq_handler(dev, pch_iir);
646 }
647
648 if (de_iir & DE_PCU_EVENT) {
649 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
650 i915_handle_rps_change(dev);
651 }
652
653 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
654 gen6_queue_rps_work(dev_priv, pm_iir);
655
656 /* should clear PCH hotplug event before clear CPU irq */
657 I915_WRITE(SDEIIR, pch_iir);
658 I915_WRITE(GTIIR, gt_iir);
659 I915_WRITE(DEIIR, de_iir);
660 I915_WRITE(GEN6_PMIIR, pm_iir);
661
662 done:
663 I915_WRITE(DEIER, de_ier);
664 POSTING_READ(DEIER);
665
666 return ret;
667 }
668
669 /**
670 * i915_error_work_func - do process context error handling work
671 * @work: work struct
672 *
673 * Fire an error uevent so userspace can see that a hang or error
674 * was detected.
675 */
i915_error_work_func(struct work_struct * work)676 static void i915_error_work_func(struct work_struct *work)
677 {
678 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
679 error_work);
680 struct drm_device *dev = dev_priv->dev;
681 char *error_event[] = { "ERROR=1", NULL };
682 char *reset_event[] = { "RESET=1", NULL };
683 char *reset_done_event[] = { "ERROR=0", NULL };
684
685 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
686
687 if (atomic_read(&dev_priv->mm.wedged)) {
688 DRM_DEBUG_DRIVER("resetting chip\n");
689 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
690 if (!i915_reset(dev, GRDOM_RENDER)) {
691 atomic_set(&dev_priv->mm.wedged, 0);
692 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
693 }
694 complete_all(&dev_priv->error_completion);
695 }
696 }
697
698 #ifdef CONFIG_DEBUG_FS
699 static struct drm_i915_error_object *
i915_error_object_create(struct drm_i915_private * dev_priv,struct drm_i915_gem_object * src)700 i915_error_object_create(struct drm_i915_private *dev_priv,
701 struct drm_i915_gem_object *src)
702 {
703 struct drm_i915_error_object *dst;
704 int page, page_count;
705 u32 reloc_offset;
706
707 if (src == NULL || src->pages == NULL)
708 return NULL;
709
710 page_count = src->base.size / PAGE_SIZE;
711
712 dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
713 if (dst == NULL)
714 return NULL;
715
716 reloc_offset = src->gtt_offset;
717 for (page = 0; page < page_count; page++) {
718 unsigned long flags;
719 void *d;
720
721 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
722 if (d == NULL)
723 goto unwind;
724
725 local_irq_save(flags);
726 if (reloc_offset < dev_priv->mm.gtt_mappable_end) {
727 void __iomem *s;
728
729 /* Simply ignore tiling or any overlapping fence.
730 * It's part of the error state, and this hopefully
731 * captures what the GPU read.
732 */
733
734 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
735 reloc_offset);
736 memcpy_fromio(d, s, PAGE_SIZE);
737 io_mapping_unmap_atomic(s);
738 } else {
739 void *s;
740
741 drm_clflush_pages(&src->pages[page], 1);
742
743 s = kmap_atomic(src->pages[page]);
744 memcpy(d, s, PAGE_SIZE);
745 kunmap_atomic(s);
746
747 drm_clflush_pages(&src->pages[page], 1);
748 }
749 local_irq_restore(flags);
750
751 dst->pages[page] = d;
752
753 reloc_offset += PAGE_SIZE;
754 }
755 dst->page_count = page_count;
756 dst->gtt_offset = src->gtt_offset;
757
758 return dst;
759
760 unwind:
761 while (page--)
762 kfree(dst->pages[page]);
763 kfree(dst);
764 return NULL;
765 }
766
767 static void
i915_error_object_free(struct drm_i915_error_object * obj)768 i915_error_object_free(struct drm_i915_error_object *obj)
769 {
770 int page;
771
772 if (obj == NULL)
773 return;
774
775 for (page = 0; page < obj->page_count; page++)
776 kfree(obj->pages[page]);
777
778 kfree(obj);
779 }
780
781 static void
i915_error_state_free(struct drm_device * dev,struct drm_i915_error_state * error)782 i915_error_state_free(struct drm_device *dev,
783 struct drm_i915_error_state *error)
784 {
785 int i;
786
787 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
788 i915_error_object_free(error->ring[i].batchbuffer);
789 i915_error_object_free(error->ring[i].ringbuffer);
790 kfree(error->ring[i].requests);
791 }
792
793 kfree(error->active_bo);
794 kfree(error->overlay);
795 kfree(error);
796 }
797
capture_bo_list(struct drm_i915_error_buffer * err,int count,struct list_head * head)798 static u32 capture_bo_list(struct drm_i915_error_buffer *err,
799 int count,
800 struct list_head *head)
801 {
802 struct drm_i915_gem_object *obj;
803 int i = 0;
804
805 list_for_each_entry(obj, head, mm_list) {
806 err->size = obj->base.size;
807 err->name = obj->base.name;
808 err->seqno = obj->last_rendering_seqno;
809 err->gtt_offset = obj->gtt_offset;
810 err->read_domains = obj->base.read_domains;
811 err->write_domain = obj->base.write_domain;
812 err->fence_reg = obj->fence_reg;
813 err->pinned = 0;
814 if (obj->pin_count > 0)
815 err->pinned = 1;
816 if (obj->user_pin_count > 0)
817 err->pinned = -1;
818 err->tiling = obj->tiling_mode;
819 err->dirty = obj->dirty;
820 err->purgeable = obj->madv != I915_MADV_WILLNEED;
821 err->ring = obj->ring ? obj->ring->id : -1;
822 err->cache_level = obj->cache_level;
823
824 if (++i == count)
825 break;
826
827 err++;
828 }
829
830 return i;
831 }
832
i915_gem_record_fences(struct drm_device * dev,struct drm_i915_error_state * error)833 static void i915_gem_record_fences(struct drm_device *dev,
834 struct drm_i915_error_state *error)
835 {
836 struct drm_i915_private *dev_priv = dev->dev_private;
837 int i;
838
839 /* Fences */
840 switch (INTEL_INFO(dev)->gen) {
841 case 7:
842 case 6:
843 for (i = 0; i < 16; i++)
844 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
845 break;
846 case 5:
847 case 4:
848 for (i = 0; i < 16; i++)
849 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
850 break;
851 case 3:
852 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
853 for (i = 0; i < 8; i++)
854 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
855 case 2:
856 for (i = 0; i < 8; i++)
857 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
858 break;
859
860 }
861 }
862
863 static struct drm_i915_error_object *
i915_error_first_batchbuffer(struct drm_i915_private * dev_priv,struct intel_ring_buffer * ring)864 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
865 struct intel_ring_buffer *ring)
866 {
867 struct drm_i915_gem_object *obj;
868 u32 seqno;
869
870 if (!ring->get_seqno)
871 return NULL;
872
873 seqno = ring->get_seqno(ring);
874 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
875 if (obj->ring != ring)
876 continue;
877
878 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
879 continue;
880
881 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
882 continue;
883
884 /* We need to copy these to an anonymous buffer as the simplest
885 * method to avoid being overwritten by userspace.
886 */
887 return i915_error_object_create(dev_priv, obj);
888 }
889
890 return NULL;
891 }
892
i915_record_ring_state(struct drm_device * dev,struct drm_i915_error_state * error,struct intel_ring_buffer * ring)893 static void i915_record_ring_state(struct drm_device *dev,
894 struct drm_i915_error_state *error,
895 struct intel_ring_buffer *ring)
896 {
897 struct drm_i915_private *dev_priv = dev->dev_private;
898
899 if (INTEL_INFO(dev)->gen >= 6) {
900 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
901 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
902 error->semaphore_mboxes[ring->id][0]
903 = I915_READ(RING_SYNC_0(ring->mmio_base));
904 error->semaphore_mboxes[ring->id][1]
905 = I915_READ(RING_SYNC_1(ring->mmio_base));
906 }
907
908 if (INTEL_INFO(dev)->gen >= 4) {
909 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
910 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
911 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
912 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
913 if (ring->id == RCS) {
914 error->instdone1 = I915_READ(INSTDONE1);
915 error->bbaddr = I915_READ64(BB_ADDR);
916 }
917 } else {
918 error->ipeir[ring->id] = I915_READ(IPEIR);
919 error->ipehr[ring->id] = I915_READ(IPEHR);
920 error->instdone[ring->id] = I915_READ(INSTDONE);
921 }
922
923 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
924 error->seqno[ring->id] = ring->get_seqno(ring);
925 error->acthd[ring->id] = intel_ring_get_active_head(ring);
926 error->head[ring->id] = I915_READ_HEAD(ring);
927 error->tail[ring->id] = I915_READ_TAIL(ring);
928
929 error->cpu_ring_head[ring->id] = ring->head;
930 error->cpu_ring_tail[ring->id] = ring->tail;
931 }
932
i915_gem_record_rings(struct drm_device * dev,struct drm_i915_error_state * error)933 static void i915_gem_record_rings(struct drm_device *dev,
934 struct drm_i915_error_state *error)
935 {
936 struct drm_i915_private *dev_priv = dev->dev_private;
937 struct drm_i915_gem_request *request;
938 int i, count;
939
940 for (i = 0; i < I915_NUM_RINGS; i++) {
941 struct intel_ring_buffer *ring = &dev_priv->ring[i];
942
943 if (ring->obj == NULL)
944 continue;
945
946 i915_record_ring_state(dev, error, ring);
947
948 error->ring[i].batchbuffer =
949 i915_error_first_batchbuffer(dev_priv, ring);
950
951 error->ring[i].ringbuffer =
952 i915_error_object_create(dev_priv, ring->obj);
953
954 count = 0;
955 list_for_each_entry(request, &ring->request_list, list)
956 count++;
957
958 error->ring[i].num_requests = count;
959 error->ring[i].requests =
960 kmalloc(count*sizeof(struct drm_i915_error_request),
961 GFP_ATOMIC);
962 if (error->ring[i].requests == NULL) {
963 error->ring[i].num_requests = 0;
964 continue;
965 }
966
967 count = 0;
968 list_for_each_entry(request, &ring->request_list, list) {
969 struct drm_i915_error_request *erq;
970
971 erq = &error->ring[i].requests[count++];
972 erq->seqno = request->seqno;
973 erq->jiffies = request->emitted_jiffies;
974 erq->tail = request->tail;
975 }
976 }
977 }
978
979 /**
980 * i915_capture_error_state - capture an error record for later analysis
981 * @dev: drm device
982 *
983 * Should be called when an error is detected (either a hang or an error
984 * interrupt) to capture error state from the time of the error. Fills
985 * out a structure which becomes available in debugfs for user level tools
986 * to pick up.
987 */
i915_capture_error_state(struct drm_device * dev)988 static void i915_capture_error_state(struct drm_device *dev)
989 {
990 struct drm_i915_private *dev_priv = dev->dev_private;
991 struct drm_i915_gem_object *obj;
992 struct drm_i915_error_state *error;
993 unsigned long flags;
994 int i, pipe;
995
996 spin_lock_irqsave(&dev_priv->error_lock, flags);
997 error = dev_priv->first_error;
998 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
999 if (error)
1000 return;
1001
1002 /* Account for pipe specific data like PIPE*STAT */
1003 error = kzalloc(sizeof(*error), GFP_ATOMIC);
1004 if (!error) {
1005 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1006 return;
1007 }
1008
1009 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1010 dev->primary->index);
1011
1012 error->eir = I915_READ(EIR);
1013 error->pgtbl_er = I915_READ(PGTBL_ER);
1014 for_each_pipe(pipe)
1015 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1016
1017 if (INTEL_INFO(dev)->gen >= 6) {
1018 error->error = I915_READ(ERROR_GEN6);
1019 error->done_reg = I915_READ(DONE_REG);
1020 }
1021
1022 i915_gem_record_fences(dev, error);
1023 i915_gem_record_rings(dev, error);
1024
1025 /* Record buffers on the active and pinned lists. */
1026 error->active_bo = NULL;
1027 error->pinned_bo = NULL;
1028
1029 i = 0;
1030 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1031 i++;
1032 error->active_bo_count = i;
1033 list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
1034 i++;
1035 error->pinned_bo_count = i - error->active_bo_count;
1036
1037 error->active_bo = NULL;
1038 error->pinned_bo = NULL;
1039 if (i) {
1040 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1041 GFP_ATOMIC);
1042 if (error->active_bo)
1043 error->pinned_bo =
1044 error->active_bo + error->active_bo_count;
1045 }
1046
1047 if (error->active_bo)
1048 error->active_bo_count =
1049 capture_bo_list(error->active_bo,
1050 error->active_bo_count,
1051 &dev_priv->mm.active_list);
1052
1053 if (error->pinned_bo)
1054 error->pinned_bo_count =
1055 capture_bo_list(error->pinned_bo,
1056 error->pinned_bo_count,
1057 &dev_priv->mm.pinned_list);
1058
1059 do_gettimeofday(&error->time);
1060
1061 error->overlay = intel_overlay_capture_error_state(dev);
1062 error->display = intel_display_capture_error_state(dev);
1063
1064 spin_lock_irqsave(&dev_priv->error_lock, flags);
1065 if (dev_priv->first_error == NULL) {
1066 dev_priv->first_error = error;
1067 error = NULL;
1068 }
1069 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1070
1071 if (error)
1072 i915_error_state_free(dev, error);
1073 }
1074
i915_destroy_error_state(struct drm_device * dev)1075 void i915_destroy_error_state(struct drm_device *dev)
1076 {
1077 struct drm_i915_private *dev_priv = dev->dev_private;
1078 struct drm_i915_error_state *error;
1079 unsigned long flags;
1080
1081 spin_lock_irqsave(&dev_priv->error_lock, flags);
1082 error = dev_priv->first_error;
1083 dev_priv->first_error = NULL;
1084 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1085
1086 if (error)
1087 i915_error_state_free(dev, error);
1088 }
1089 #else
1090 #define i915_capture_error_state(x)
1091 #endif
1092
i915_report_and_clear_eir(struct drm_device * dev)1093 static void i915_report_and_clear_eir(struct drm_device *dev)
1094 {
1095 struct drm_i915_private *dev_priv = dev->dev_private;
1096 u32 eir = I915_READ(EIR);
1097 int pipe;
1098
1099 if (!eir)
1100 return;
1101
1102 printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
1103 eir);
1104
1105 if (IS_G4X(dev)) {
1106 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1107 u32 ipeir = I915_READ(IPEIR_I965);
1108
1109 printk(KERN_ERR " IPEIR: 0x%08x\n",
1110 I915_READ(IPEIR_I965));
1111 printk(KERN_ERR " IPEHR: 0x%08x\n",
1112 I915_READ(IPEHR_I965));
1113 printk(KERN_ERR " INSTDONE: 0x%08x\n",
1114 I915_READ(INSTDONE_I965));
1115 printk(KERN_ERR " INSTPS: 0x%08x\n",
1116 I915_READ(INSTPS));
1117 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
1118 I915_READ(INSTDONE1));
1119 printk(KERN_ERR " ACTHD: 0x%08x\n",
1120 I915_READ(ACTHD_I965));
1121 I915_WRITE(IPEIR_I965, ipeir);
1122 POSTING_READ(IPEIR_I965);
1123 }
1124 if (eir & GM45_ERROR_PAGE_TABLE) {
1125 u32 pgtbl_err = I915_READ(PGTBL_ER);
1126 printk(KERN_ERR "page table error\n");
1127 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
1128 pgtbl_err);
1129 I915_WRITE(PGTBL_ER, pgtbl_err);
1130 POSTING_READ(PGTBL_ER);
1131 }
1132 }
1133
1134 if (!IS_GEN2(dev)) {
1135 if (eir & I915_ERROR_PAGE_TABLE) {
1136 u32 pgtbl_err = I915_READ(PGTBL_ER);
1137 printk(KERN_ERR "page table error\n");
1138 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
1139 pgtbl_err);
1140 I915_WRITE(PGTBL_ER, pgtbl_err);
1141 POSTING_READ(PGTBL_ER);
1142 }
1143 }
1144
1145 if (eir & I915_ERROR_MEMORY_REFRESH) {
1146 printk(KERN_ERR "memory refresh error:\n");
1147 for_each_pipe(pipe)
1148 printk(KERN_ERR "pipe %c stat: 0x%08x\n",
1149 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1150 /* pipestat has already been acked */
1151 }
1152 if (eir & I915_ERROR_INSTRUCTION) {
1153 printk(KERN_ERR "instruction error\n");
1154 printk(KERN_ERR " INSTPM: 0x%08x\n",
1155 I915_READ(INSTPM));
1156 if (INTEL_INFO(dev)->gen < 4) {
1157 u32 ipeir = I915_READ(IPEIR);
1158
1159 printk(KERN_ERR " IPEIR: 0x%08x\n",
1160 I915_READ(IPEIR));
1161 printk(KERN_ERR " IPEHR: 0x%08x\n",
1162 I915_READ(IPEHR));
1163 printk(KERN_ERR " INSTDONE: 0x%08x\n",
1164 I915_READ(INSTDONE));
1165 printk(KERN_ERR " ACTHD: 0x%08x\n",
1166 I915_READ(ACTHD));
1167 I915_WRITE(IPEIR, ipeir);
1168 POSTING_READ(IPEIR);
1169 } else {
1170 u32 ipeir = I915_READ(IPEIR_I965);
1171
1172 printk(KERN_ERR " IPEIR: 0x%08x\n",
1173 I915_READ(IPEIR_I965));
1174 printk(KERN_ERR " IPEHR: 0x%08x\n",
1175 I915_READ(IPEHR_I965));
1176 printk(KERN_ERR " INSTDONE: 0x%08x\n",
1177 I915_READ(INSTDONE_I965));
1178 printk(KERN_ERR " INSTPS: 0x%08x\n",
1179 I915_READ(INSTPS));
1180 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
1181 I915_READ(INSTDONE1));
1182 printk(KERN_ERR " ACTHD: 0x%08x\n",
1183 I915_READ(ACTHD_I965));
1184 I915_WRITE(IPEIR_I965, ipeir);
1185 POSTING_READ(IPEIR_I965);
1186 }
1187 }
1188
1189 I915_WRITE(EIR, eir);
1190 POSTING_READ(EIR);
1191 eir = I915_READ(EIR);
1192 if (eir) {
1193 /*
1194 * some errors might have become stuck,
1195 * mask them.
1196 */
1197 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1198 I915_WRITE(EMR, I915_READ(EMR) | eir);
1199 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1200 }
1201 }
1202
1203 /**
1204 * i915_handle_error - handle an error interrupt
1205 * @dev: drm device
1206 *
1207 * Do some basic checking of regsiter state at error interrupt time and
1208 * dump it to the syslog. Also call i915_capture_error_state() to make
1209 * sure we get a record and make it available in debugfs. Fire a uevent
1210 * so userspace knows something bad happened (should trigger collection
1211 * of a ring dump etc.).
1212 */
i915_handle_error(struct drm_device * dev,bool wedged)1213 void i915_handle_error(struct drm_device *dev, bool wedged)
1214 {
1215 struct drm_i915_private *dev_priv = dev->dev_private;
1216
1217 i915_capture_error_state(dev);
1218 i915_report_and_clear_eir(dev);
1219
1220 if (wedged) {
1221 INIT_COMPLETION(dev_priv->error_completion);
1222 atomic_set(&dev_priv->mm.wedged, 1);
1223
1224 /*
1225 * Wakeup waiting processes so they don't hang
1226 */
1227 wake_up_all(&dev_priv->ring[RCS].irq_queue);
1228 if (HAS_BSD(dev))
1229 wake_up_all(&dev_priv->ring[VCS].irq_queue);
1230 if (HAS_BLT(dev))
1231 wake_up_all(&dev_priv->ring[BCS].irq_queue);
1232 }
1233
1234 queue_work(dev_priv->wq, &dev_priv->error_work);
1235 }
1236
i915_pageflip_stall_check(struct drm_device * dev,int pipe)1237 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1238 {
1239 drm_i915_private_t *dev_priv = dev->dev_private;
1240 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1242 struct drm_i915_gem_object *obj;
1243 struct intel_unpin_work *work;
1244 unsigned long flags;
1245 bool stall_detected;
1246
1247 /* Ignore early vblank irqs */
1248 if (intel_crtc == NULL)
1249 return;
1250
1251 spin_lock_irqsave(&dev->event_lock, flags);
1252 work = intel_crtc->unpin_work;
1253
1254 if (work == NULL || work->pending || !work->enable_stall_check) {
1255 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1256 spin_unlock_irqrestore(&dev->event_lock, flags);
1257 return;
1258 }
1259
1260 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1261 obj = work->pending_flip_obj;
1262 if (INTEL_INFO(dev)->gen >= 4) {
1263 int dspsurf = DSPSURF(intel_crtc->plane);
1264 stall_detected = I915_READ(dspsurf) == obj->gtt_offset;
1265 } else {
1266 int dspaddr = DSPADDR(intel_crtc->plane);
1267 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1268 crtc->y * crtc->fb->pitches[0] +
1269 crtc->x * crtc->fb->bits_per_pixel/8);
1270 }
1271
1272 spin_unlock_irqrestore(&dev->event_lock, flags);
1273
1274 if (stall_detected) {
1275 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1276 intel_prepare_page_flip(dev, intel_crtc->plane);
1277 }
1278 }
1279
i915_driver_irq_handler(DRM_IRQ_ARGS)1280 static irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1281 {
1282 struct drm_device *dev = (struct drm_device *) arg;
1283 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1284 struct drm_i915_master_private *master_priv;
1285 u32 iir, new_iir;
1286 u32 pipe_stats[I915_MAX_PIPES];
1287 u32 vblank_status;
1288 int vblank = 0;
1289 unsigned long irqflags;
1290 int irq_received;
1291 int ret = IRQ_NONE, pipe;
1292 bool blc_event = false;
1293
1294 atomic_inc(&dev_priv->irq_received);
1295
1296 iir = I915_READ(IIR);
1297
1298 if (INTEL_INFO(dev)->gen >= 4)
1299 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
1300 else
1301 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
1302
1303 for (;;) {
1304 irq_received = iir != 0;
1305
1306 /* Can't rely on pipestat interrupt bit in iir as it might
1307 * have been cleared after the pipestat interrupt was received.
1308 * It doesn't set the bit in iir again, but it still produces
1309 * interrupts (for non-MSI).
1310 */
1311 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1312 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
1313 i915_handle_error(dev, false);
1314
1315 for_each_pipe(pipe) {
1316 int reg = PIPESTAT(pipe);
1317 pipe_stats[pipe] = I915_READ(reg);
1318
1319 /*
1320 * Clear the PIPE*STAT regs before the IIR
1321 */
1322 if (pipe_stats[pipe] & 0x8000ffff) {
1323 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1324 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1325 pipe_name(pipe));
1326 I915_WRITE(reg, pipe_stats[pipe]);
1327 irq_received = 1;
1328 }
1329 }
1330 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1331
1332 if (!irq_received)
1333 break;
1334
1335 ret = IRQ_HANDLED;
1336
1337 /* Consume port. Then clear IIR or we'll miss events */
1338 if ((I915_HAS_HOTPLUG(dev)) &&
1339 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
1340 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1341
1342 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1343 hotplug_status);
1344 if (hotplug_status & dev_priv->hotplug_supported_mask)
1345 queue_work(dev_priv->wq,
1346 &dev_priv->hotplug_work);
1347
1348 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1349 I915_READ(PORT_HOTPLUG_STAT);
1350 }
1351
1352 I915_WRITE(IIR, iir);
1353 new_iir = I915_READ(IIR); /* Flush posted writes */
1354
1355 if (dev->primary->master) {
1356 master_priv = dev->primary->master->driver_priv;
1357 if (master_priv->sarea_priv)
1358 master_priv->sarea_priv->last_dispatch =
1359 READ_BREADCRUMB(dev_priv);
1360 }
1361
1362 if (iir & I915_USER_INTERRUPT)
1363 notify_ring(dev, &dev_priv->ring[RCS]);
1364 if (iir & I915_BSD_USER_INTERRUPT)
1365 notify_ring(dev, &dev_priv->ring[VCS]);
1366
1367 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1368 intel_prepare_page_flip(dev, 0);
1369 if (dev_priv->flip_pending_is_done)
1370 intel_finish_page_flip_plane(dev, 0);
1371 }
1372
1373 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1374 intel_prepare_page_flip(dev, 1);
1375 if (dev_priv->flip_pending_is_done)
1376 intel_finish_page_flip_plane(dev, 1);
1377 }
1378
1379 for_each_pipe(pipe) {
1380 if (pipe_stats[pipe] & vblank_status &&
1381 drm_handle_vblank(dev, pipe)) {
1382 vblank++;
1383 if (!dev_priv->flip_pending_is_done) {
1384 i915_pageflip_stall_check(dev, pipe);
1385 intel_finish_page_flip(dev, pipe);
1386 }
1387 }
1388
1389 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1390 blc_event = true;
1391 }
1392
1393
1394 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1395 intel_opregion_asle_intr(dev);
1396
1397 /* With MSI, interrupts are only generated when iir
1398 * transitions from zero to nonzero. If another bit got
1399 * set while we were handling the existing iir bits, then
1400 * we would never get another interrupt.
1401 *
1402 * This is fine on non-MSI as well, as if we hit this path
1403 * we avoid exiting the interrupt handler only to generate
1404 * another one.
1405 *
1406 * Note that for MSI this could cause a stray interrupt report
1407 * if an interrupt landed in the time between writing IIR and
1408 * the posting read. This should be rare enough to never
1409 * trigger the 99% of 100,000 interrupts test for disabling
1410 * stray interrupts.
1411 */
1412 iir = new_iir;
1413 }
1414
1415 return ret;
1416 }
1417
i915_emit_irq(struct drm_device * dev)1418 static int i915_emit_irq(struct drm_device * dev)
1419 {
1420 drm_i915_private_t *dev_priv = dev->dev_private;
1421 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1422
1423 i915_kernel_lost_context(dev);
1424
1425 DRM_DEBUG_DRIVER("\n");
1426
1427 dev_priv->counter++;
1428 if (dev_priv->counter > 0x7FFFFFFFUL)
1429 dev_priv->counter = 1;
1430 if (master_priv->sarea_priv)
1431 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1432
1433 if (BEGIN_LP_RING(4) == 0) {
1434 OUT_RING(MI_STORE_DWORD_INDEX);
1435 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1436 OUT_RING(dev_priv->counter);
1437 OUT_RING(MI_USER_INTERRUPT);
1438 ADVANCE_LP_RING();
1439 }
1440
1441 return dev_priv->counter;
1442 }
1443
i915_wait_irq(struct drm_device * dev,int irq_nr)1444 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1445 {
1446 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1447 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1448 int ret = 0;
1449 struct intel_ring_buffer *ring = LP_RING(dev_priv);
1450
1451 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1452 READ_BREADCRUMB(dev_priv));
1453
1454 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1455 if (master_priv->sarea_priv)
1456 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1457 return 0;
1458 }
1459
1460 if (master_priv->sarea_priv)
1461 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1462
1463 if (ring->irq_get(ring)) {
1464 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
1465 READ_BREADCRUMB(dev_priv) >= irq_nr);
1466 ring->irq_put(ring);
1467 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
1468 ret = -EBUSY;
1469
1470 if (ret == -EBUSY) {
1471 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1472 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1473 }
1474
1475 return ret;
1476 }
1477
1478 /* Needs the lock as it touches the ring.
1479 */
i915_irq_emit(struct drm_device * dev,void * data,struct drm_file * file_priv)1480 int i915_irq_emit(struct drm_device *dev, void *data,
1481 struct drm_file *file_priv)
1482 {
1483 drm_i915_private_t *dev_priv = dev->dev_private;
1484 drm_i915_irq_emit_t *emit = data;
1485 int result;
1486
1487 if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
1488 DRM_ERROR("called with no initialization\n");
1489 return -EINVAL;
1490 }
1491
1492 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1493
1494 mutex_lock(&dev->struct_mutex);
1495 result = i915_emit_irq(dev);
1496 mutex_unlock(&dev->struct_mutex);
1497
1498 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1499 DRM_ERROR("copy_to_user\n");
1500 return -EFAULT;
1501 }
1502
1503 return 0;
1504 }
1505
1506 /* Doesn't need the hardware lock.
1507 */
i915_irq_wait(struct drm_device * dev,void * data,struct drm_file * file_priv)1508 int i915_irq_wait(struct drm_device *dev, void *data,
1509 struct drm_file *file_priv)
1510 {
1511 drm_i915_private_t *dev_priv = dev->dev_private;
1512 drm_i915_irq_wait_t *irqwait = data;
1513
1514 if (!dev_priv) {
1515 DRM_ERROR("called with no initialization\n");
1516 return -EINVAL;
1517 }
1518
1519 return i915_wait_irq(dev, irqwait->irq_seq);
1520 }
1521
1522 /* Called from drm generic code, passed 'crtc' which
1523 * we use as a pipe index
1524 */
i915_enable_vblank(struct drm_device * dev,int pipe)1525 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1526 {
1527 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1528 unsigned long irqflags;
1529
1530 if (!i915_pipe_enabled(dev, pipe))
1531 return -EINVAL;
1532
1533 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1534 if (INTEL_INFO(dev)->gen >= 4)
1535 i915_enable_pipestat(dev_priv, pipe,
1536 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1537 else
1538 i915_enable_pipestat(dev_priv, pipe,
1539 PIPE_VBLANK_INTERRUPT_ENABLE);
1540
1541 /* maintain vblank delivery even in deep C-states */
1542 if (dev_priv->info->gen == 3)
1543 I915_WRITE(INSTPM, INSTPM_AGPBUSY_DIS << 16);
1544 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1545
1546 return 0;
1547 }
1548
ironlake_enable_vblank(struct drm_device * dev,int pipe)1549 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1550 {
1551 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1552 unsigned long irqflags;
1553
1554 if (!i915_pipe_enabled(dev, pipe))
1555 return -EINVAL;
1556
1557 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1558 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1559 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1560 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1561
1562 return 0;
1563 }
1564
ivybridge_enable_vblank(struct drm_device * dev,int pipe)1565 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1566 {
1567 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1568 unsigned long irqflags;
1569
1570 if (!i915_pipe_enabled(dev, pipe))
1571 return -EINVAL;
1572
1573 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1574 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1575 DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1576 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1577
1578 return 0;
1579 }
1580
1581 /* Called from drm generic code, passed 'crtc' which
1582 * we use as a pipe index
1583 */
i915_disable_vblank(struct drm_device * dev,int pipe)1584 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1585 {
1586 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1587 unsigned long irqflags;
1588
1589 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1590 if (dev_priv->info->gen == 3)
1591 I915_WRITE(INSTPM,
1592 INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS);
1593
1594 i915_disable_pipestat(dev_priv, pipe,
1595 PIPE_VBLANK_INTERRUPT_ENABLE |
1596 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1597 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1598 }
1599
ironlake_disable_vblank(struct drm_device * dev,int pipe)1600 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1601 {
1602 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1603 unsigned long irqflags;
1604
1605 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1606 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1607 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1608 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1609 }
1610
ivybridge_disable_vblank(struct drm_device * dev,int pipe)1611 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1612 {
1613 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1614 unsigned long irqflags;
1615
1616 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1617 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1618 DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1619 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1620 }
1621
1622 /* Set the vblank monitor pipe
1623 */
i915_vblank_pipe_set(struct drm_device * dev,void * data,struct drm_file * file_priv)1624 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1625 struct drm_file *file_priv)
1626 {
1627 drm_i915_private_t *dev_priv = dev->dev_private;
1628
1629 if (!dev_priv) {
1630 DRM_ERROR("called with no initialization\n");
1631 return -EINVAL;
1632 }
1633
1634 return 0;
1635 }
1636
i915_vblank_pipe_get(struct drm_device * dev,void * data,struct drm_file * file_priv)1637 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1638 struct drm_file *file_priv)
1639 {
1640 drm_i915_private_t *dev_priv = dev->dev_private;
1641 drm_i915_vblank_pipe_t *pipe = data;
1642
1643 if (!dev_priv) {
1644 DRM_ERROR("called with no initialization\n");
1645 return -EINVAL;
1646 }
1647
1648 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1649
1650 return 0;
1651 }
1652
1653 /**
1654 * Schedule buffer swap at given vertical blank.
1655 */
i915_vblank_swap(struct drm_device * dev,void * data,struct drm_file * file_priv)1656 int i915_vblank_swap(struct drm_device *dev, void *data,
1657 struct drm_file *file_priv)
1658 {
1659 /* The delayed swap mechanism was fundamentally racy, and has been
1660 * removed. The model was that the client requested a delayed flip/swap
1661 * from the kernel, then waited for vblank before continuing to perform
1662 * rendering. The problem was that the kernel might wake the client
1663 * up before it dispatched the vblank swap (since the lock has to be
1664 * held while touching the ringbuffer), in which case the client would
1665 * clear and start the next frame before the swap occurred, and
1666 * flicker would occur in addition to likely missing the vblank.
1667 *
1668 * In the absence of this ioctl, userland falls back to a correct path
1669 * of waiting for a vblank, then dispatching the swap on its own.
1670 * Context switching to userland and back is plenty fast enough for
1671 * meeting the requirements of vblank swapping.
1672 */
1673 return -EINVAL;
1674 }
1675
1676 static u32
ring_last_seqno(struct intel_ring_buffer * ring)1677 ring_last_seqno(struct intel_ring_buffer *ring)
1678 {
1679 return list_entry(ring->request_list.prev,
1680 struct drm_i915_gem_request, list)->seqno;
1681 }
1682
i915_hangcheck_ring_idle(struct intel_ring_buffer * ring,bool * err)1683 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1684 {
1685 if (list_empty(&ring->request_list) ||
1686 i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1687 /* Issue a wake-up to catch stuck h/w. */
1688 if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) {
1689 DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1690 ring->name,
1691 ring->waiting_seqno,
1692 ring->get_seqno(ring));
1693 wake_up_all(&ring->irq_queue);
1694 *err = true;
1695 }
1696 return true;
1697 }
1698 return false;
1699 }
1700
kick_ring(struct intel_ring_buffer * ring)1701 static bool kick_ring(struct intel_ring_buffer *ring)
1702 {
1703 struct drm_device *dev = ring->dev;
1704 struct drm_i915_private *dev_priv = dev->dev_private;
1705 u32 tmp = I915_READ_CTL(ring);
1706 if (tmp & RING_WAIT) {
1707 DRM_ERROR("Kicking stuck wait on %s\n",
1708 ring->name);
1709 I915_WRITE_CTL(ring, tmp);
1710 return true;
1711 }
1712 return false;
1713 }
1714
1715 /**
1716 * This is called when the chip hasn't reported back with completed
1717 * batchbuffers in a long time. The first time this is called we simply record
1718 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1719 * again, we assume the chip is wedged and try to fix it.
1720 */
i915_hangcheck_elapsed(unsigned long data)1721 void i915_hangcheck_elapsed(unsigned long data)
1722 {
1723 struct drm_device *dev = (struct drm_device *)data;
1724 drm_i915_private_t *dev_priv = dev->dev_private;
1725 uint32_t acthd, instdone, instdone1, acthd_bsd, acthd_blt;
1726 bool err = false;
1727
1728 if (!i915_enable_hangcheck)
1729 return;
1730
1731 /* If all work is done then ACTHD clearly hasn't advanced. */
1732 if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
1733 i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
1734 i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) {
1735 dev_priv->hangcheck_count = 0;
1736 if (err)
1737 goto repeat;
1738 return;
1739 }
1740
1741 if (INTEL_INFO(dev)->gen < 4) {
1742 instdone = I915_READ(INSTDONE);
1743 instdone1 = 0;
1744 } else {
1745 instdone = I915_READ(INSTDONE_I965);
1746 instdone1 = I915_READ(INSTDONE1);
1747 }
1748 acthd = intel_ring_get_active_head(&dev_priv->ring[RCS]);
1749 acthd_bsd = HAS_BSD(dev) ?
1750 intel_ring_get_active_head(&dev_priv->ring[VCS]) : 0;
1751 acthd_blt = HAS_BLT(dev) ?
1752 intel_ring_get_active_head(&dev_priv->ring[BCS]) : 0;
1753
1754 if (dev_priv->last_acthd == acthd &&
1755 dev_priv->last_acthd_bsd == acthd_bsd &&
1756 dev_priv->last_acthd_blt == acthd_blt &&
1757 dev_priv->last_instdone == instdone &&
1758 dev_priv->last_instdone1 == instdone1) {
1759 if (dev_priv->hangcheck_count++ > 1) {
1760 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1761 i915_handle_error(dev, true);
1762
1763 if (!IS_GEN2(dev)) {
1764 /* Is the chip hanging on a WAIT_FOR_EVENT?
1765 * If so we can simply poke the RB_WAIT bit
1766 * and break the hang. This should work on
1767 * all but the second generation chipsets.
1768 */
1769 if (kick_ring(&dev_priv->ring[RCS]))
1770 goto repeat;
1771
1772 if (HAS_BSD(dev) &&
1773 kick_ring(&dev_priv->ring[VCS]))
1774 goto repeat;
1775
1776 if (HAS_BLT(dev) &&
1777 kick_ring(&dev_priv->ring[BCS]))
1778 goto repeat;
1779 }
1780
1781 return;
1782 }
1783 } else {
1784 dev_priv->hangcheck_count = 0;
1785
1786 dev_priv->last_acthd = acthd;
1787 dev_priv->last_acthd_bsd = acthd_bsd;
1788 dev_priv->last_acthd_blt = acthd_blt;
1789 dev_priv->last_instdone = instdone;
1790 dev_priv->last_instdone1 = instdone1;
1791 }
1792
1793 repeat:
1794 /* Reset timer case chip hangs without another request being added */
1795 mod_timer(&dev_priv->hangcheck_timer,
1796 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1797 }
1798
1799 /* drm_dma.h hooks
1800 */
ironlake_irq_preinstall(struct drm_device * dev)1801 static void ironlake_irq_preinstall(struct drm_device *dev)
1802 {
1803 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1804
1805 atomic_set(&dev_priv->irq_received, 0);
1806
1807 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1808 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1809 if (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
1810 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
1811
1812 I915_WRITE(HWSTAM, 0xeffe);
1813
1814 /* XXX hotplug from PCH */
1815
1816 I915_WRITE(DEIMR, 0xffffffff);
1817 I915_WRITE(DEIER, 0x0);
1818 POSTING_READ(DEIER);
1819
1820 /* and GT */
1821 I915_WRITE(GTIMR, 0xffffffff);
1822 I915_WRITE(GTIER, 0x0);
1823 POSTING_READ(GTIER);
1824
1825 /* south display irq */
1826 I915_WRITE(SDEIMR, 0xffffffff);
1827 I915_WRITE(SDEIER, 0x0);
1828 POSTING_READ(SDEIER);
1829 }
1830
1831 /*
1832 * Enable digital hotplug on the PCH, and configure the DP short pulse
1833 * duration to 2ms (which is the minimum in the Display Port spec)
1834 *
1835 * This register is the same on all known PCH chips.
1836 */
1837
ironlake_enable_pch_hotplug(struct drm_device * dev)1838 static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1839 {
1840 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1841 u32 hotplug;
1842
1843 hotplug = I915_READ(PCH_PORT_HOTPLUG);
1844 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1845 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1846 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1847 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1848 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1849 }
1850
ironlake_irq_postinstall(struct drm_device * dev)1851 static int ironlake_irq_postinstall(struct drm_device *dev)
1852 {
1853 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1854 /* enable kind of interrupts always enabled */
1855 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1856 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1857 u32 render_irqs;
1858 u32 hotplug_mask;
1859
1860 DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
1861 if (HAS_BSD(dev))
1862 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
1863 if (HAS_BLT(dev))
1864 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
1865
1866 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1867 dev_priv->irq_mask = ~display_mask;
1868
1869 /* should always can generate irq */
1870 I915_WRITE(DEIIR, I915_READ(DEIIR));
1871 I915_WRITE(DEIMR, dev_priv->irq_mask);
1872 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1873 POSTING_READ(DEIER);
1874
1875 dev_priv->gt_irq_mask = ~0;
1876
1877 I915_WRITE(GTIIR, I915_READ(GTIIR));
1878 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1879
1880 if (IS_GEN6(dev))
1881 render_irqs =
1882 GT_USER_INTERRUPT |
1883 GT_GEN6_BSD_USER_INTERRUPT |
1884 GT_BLT_USER_INTERRUPT;
1885 else
1886 render_irqs =
1887 GT_USER_INTERRUPT |
1888 GT_PIPE_NOTIFY |
1889 GT_BSD_USER_INTERRUPT;
1890 I915_WRITE(GTIER, render_irqs);
1891 POSTING_READ(GTIER);
1892
1893 if (HAS_PCH_CPT(dev)) {
1894 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1895 SDE_PORTB_HOTPLUG_CPT |
1896 SDE_PORTC_HOTPLUG_CPT |
1897 SDE_PORTD_HOTPLUG_CPT);
1898 } else {
1899 hotplug_mask = (SDE_CRT_HOTPLUG |
1900 SDE_PORTB_HOTPLUG |
1901 SDE_PORTC_HOTPLUG |
1902 SDE_PORTD_HOTPLUG |
1903 SDE_AUX_MASK);
1904 }
1905
1906 dev_priv->pch_irq_mask = ~hotplug_mask;
1907
1908 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1909 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1910 I915_WRITE(SDEIER, hotplug_mask);
1911 POSTING_READ(SDEIER);
1912
1913 ironlake_enable_pch_hotplug(dev);
1914
1915 if (IS_IRONLAKE_M(dev)) {
1916 /* Clear & enable PCU event interrupts */
1917 I915_WRITE(DEIIR, DE_PCU_EVENT);
1918 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1919 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1920 }
1921
1922 return 0;
1923 }
1924
ivybridge_irq_postinstall(struct drm_device * dev)1925 static int ivybridge_irq_postinstall(struct drm_device *dev)
1926 {
1927 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1928 /* enable kind of interrupts always enabled */
1929 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
1930 DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB |
1931 DE_PLANEB_FLIP_DONE_IVB;
1932 u32 render_irqs;
1933 u32 hotplug_mask;
1934
1935 DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
1936 if (HAS_BSD(dev))
1937 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
1938 if (HAS_BLT(dev))
1939 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
1940
1941 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1942 dev_priv->irq_mask = ~display_mask;
1943
1944 /* should always can generate irq */
1945 I915_WRITE(DEIIR, I915_READ(DEIIR));
1946 I915_WRITE(DEIMR, dev_priv->irq_mask);
1947 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB |
1948 DE_PIPEB_VBLANK_IVB);
1949 POSTING_READ(DEIER);
1950
1951 dev_priv->gt_irq_mask = ~0;
1952
1953 I915_WRITE(GTIIR, I915_READ(GTIIR));
1954 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1955
1956 render_irqs = GT_USER_INTERRUPT | GT_GEN6_BSD_USER_INTERRUPT |
1957 GT_BLT_USER_INTERRUPT;
1958 I915_WRITE(GTIER, render_irqs);
1959 POSTING_READ(GTIER);
1960
1961 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1962 SDE_PORTB_HOTPLUG_CPT |
1963 SDE_PORTC_HOTPLUG_CPT |
1964 SDE_PORTD_HOTPLUG_CPT);
1965 dev_priv->pch_irq_mask = ~hotplug_mask;
1966
1967 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1968 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1969 I915_WRITE(SDEIER, hotplug_mask);
1970 POSTING_READ(SDEIER);
1971
1972 ironlake_enable_pch_hotplug(dev);
1973
1974 return 0;
1975 }
1976
i915_driver_irq_preinstall(struct drm_device * dev)1977 static void i915_driver_irq_preinstall(struct drm_device * dev)
1978 {
1979 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1980 int pipe;
1981
1982 atomic_set(&dev_priv->irq_received, 0);
1983
1984 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1985 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1986
1987 if (I915_HAS_HOTPLUG(dev)) {
1988 I915_WRITE(PORT_HOTPLUG_EN, 0);
1989 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1990 }
1991
1992 I915_WRITE(HWSTAM, 0xeffe);
1993 for_each_pipe(pipe)
1994 I915_WRITE(PIPESTAT(pipe), 0);
1995 I915_WRITE(IMR, 0xffffffff);
1996 I915_WRITE(IER, 0x0);
1997 POSTING_READ(IER);
1998 }
1999
2000 /*
2001 * Must be called after intel_modeset_init or hotplug interrupts won't be
2002 * enabled correctly.
2003 */
i915_driver_irq_postinstall(struct drm_device * dev)2004 static int i915_driver_irq_postinstall(struct drm_device *dev)
2005 {
2006 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2007 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
2008 u32 error_mask;
2009
2010 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
2011
2012 /* Unmask the interrupts that we always want on. */
2013 dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
2014
2015 dev_priv->pipestat[0] = 0;
2016 dev_priv->pipestat[1] = 0;
2017
2018 if (I915_HAS_HOTPLUG(dev)) {
2019 /* Enable in IER... */
2020 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2021 /* and unmask in IMR */
2022 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2023 }
2024
2025 /*
2026 * Enable some error detection, note the instruction error mask
2027 * bit is reserved, so we leave it masked.
2028 */
2029 if (IS_G4X(dev)) {
2030 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2031 GM45_ERROR_MEM_PRIV |
2032 GM45_ERROR_CP_PRIV |
2033 I915_ERROR_MEMORY_REFRESH);
2034 } else {
2035 error_mask = ~(I915_ERROR_PAGE_TABLE |
2036 I915_ERROR_MEMORY_REFRESH);
2037 }
2038 I915_WRITE(EMR, error_mask);
2039
2040 I915_WRITE(IMR, dev_priv->irq_mask);
2041 I915_WRITE(IER, enable_mask);
2042 POSTING_READ(IER);
2043
2044 if (I915_HAS_HOTPLUG(dev)) {
2045 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2046
2047 /* Note HDMI and DP share bits */
2048 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2049 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2050 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2051 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2052 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2053 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2054 if (IS_G4X(dev)) {
2055 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2056 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2057 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2058 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2059 } else if (IS_GEN4(dev)) {
2060 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2061 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2062 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2063 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2064 } else {
2065 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
2066 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2067 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
2068 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2069 }
2070 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2071 hotplug_en |= CRT_HOTPLUG_INT_EN;
2072
2073 /* Programming the CRT detection parameters tends
2074 to generate a spurious hotplug event about three
2075 seconds later. So just do it once.
2076 */
2077 if (IS_G4X(dev))
2078 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2079 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2080 }
2081
2082 /* Ignore TV since it's buggy */
2083
2084 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2085 }
2086
2087 intel_opregion_enable_asle(dev);
2088
2089 return 0;
2090 }
2091
ironlake_irq_uninstall(struct drm_device * dev)2092 static void ironlake_irq_uninstall(struct drm_device *dev)
2093 {
2094 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2095
2096 if (!dev_priv)
2097 return;
2098
2099 dev_priv->vblank_pipe = 0;
2100
2101 I915_WRITE(HWSTAM, 0xffffffff);
2102
2103 I915_WRITE(DEIMR, 0xffffffff);
2104 I915_WRITE(DEIER, 0x0);
2105 I915_WRITE(DEIIR, I915_READ(DEIIR));
2106
2107 I915_WRITE(GTIMR, 0xffffffff);
2108 I915_WRITE(GTIER, 0x0);
2109 I915_WRITE(GTIIR, I915_READ(GTIIR));
2110
2111 I915_WRITE(SDEIMR, 0xffffffff);
2112 I915_WRITE(SDEIER, 0x0);
2113 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2114 }
2115
i915_driver_irq_uninstall(struct drm_device * dev)2116 static void i915_driver_irq_uninstall(struct drm_device * dev)
2117 {
2118 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2119 int pipe;
2120
2121 if (!dev_priv)
2122 return;
2123
2124 dev_priv->vblank_pipe = 0;
2125
2126 if (I915_HAS_HOTPLUG(dev)) {
2127 I915_WRITE(PORT_HOTPLUG_EN, 0);
2128 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2129 }
2130
2131 I915_WRITE(HWSTAM, 0xffffffff);
2132 for_each_pipe(pipe)
2133 I915_WRITE(PIPESTAT(pipe), 0);
2134 I915_WRITE(IMR, 0xffffffff);
2135 I915_WRITE(IER, 0x0);
2136
2137 for_each_pipe(pipe)
2138 I915_WRITE(PIPESTAT(pipe),
2139 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2140 I915_WRITE(IIR, I915_READ(IIR));
2141 }
2142
intel_irq_init(struct drm_device * dev)2143 void intel_irq_init(struct drm_device *dev)
2144 {
2145 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2146 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2147 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
2148 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2149 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2150 }
2151
2152 if (drm_core_check_feature(dev, DRIVER_MODESET))
2153 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2154 else
2155 dev->driver->get_vblank_timestamp = NULL;
2156 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2157
2158 if (IS_IVYBRIDGE(dev)) {
2159 /* Share pre & uninstall handlers with ILK/SNB */
2160 dev->driver->irq_handler = ivybridge_irq_handler;
2161 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2162 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2163 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2164 dev->driver->enable_vblank = ivybridge_enable_vblank;
2165 dev->driver->disable_vblank = ivybridge_disable_vblank;
2166 } else if (HAS_PCH_SPLIT(dev)) {
2167 dev->driver->irq_handler = ironlake_irq_handler;
2168 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2169 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2170 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2171 dev->driver->enable_vblank = ironlake_enable_vblank;
2172 dev->driver->disable_vblank = ironlake_disable_vblank;
2173 } else {
2174 dev->driver->irq_preinstall = i915_driver_irq_preinstall;
2175 dev->driver->irq_postinstall = i915_driver_irq_postinstall;
2176 dev->driver->irq_uninstall = i915_driver_irq_uninstall;
2177 dev->driver->irq_handler = i915_driver_irq_handler;
2178 dev->driver->enable_vblank = i915_enable_vblank;
2179 dev->driver->disable_vblank = i915_disable_vblank;
2180 }
2181 }
2182