| /drivers/watchdog/ |
| D | ar7_wdt.c | 59 #define READ_REG(x) readl((void __iomem *)&(x)) macro
90 if ((READ_REG(ar7_wdt->kick_lock) & 3) == 1) { in ar7_wdt_kick()
92 if ((READ_REG(ar7_wdt->kick_lock) & 3) == 3) { in ar7_wdt_kick()
103 if ((READ_REG(ar7_wdt->prescale_lock) & 3) == 1) { in ar7_wdt_prescale()
105 if ((READ_REG(ar7_wdt->prescale_lock) & 3) == 3) { in ar7_wdt_prescale()
116 if ((READ_REG(ar7_wdt->change_lock) & 3) == 1) { in ar7_wdt_change()
118 if ((READ_REG(ar7_wdt->change_lock) & 3) == 3) { in ar7_wdt_change()
129 if ((READ_REG(ar7_wdt->disable_lock) & 3) == 1) { in ar7_wdt_disable()
131 if ((READ_REG(ar7_wdt->disable_lock) & 3) == 2) { in ar7_wdt_disable()
133 if ((READ_REG(ar7_wdt->disable_lock) & 3) == 3) { in ar7_wdt_disable()
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| /drivers/net/ethernet/tehuti/ |
| D | tehuti.c | 201 u32 link = READ_REG(priv, regMAC_LNK_STAT) & MAC_LINK_STAT; in bdx_link_changed()
257 isr = (READ_REG(priv, regISR) & IR_RUN); in bdx_isr_napi()
279 READ_REG(priv, regTXF_WPTR_0); in bdx_isr_napi()
280 READ_REG(priv, regRXD_WPTR_0); in bdx_isr_napi()
325 master = READ_REG(priv, regINIT_SEMAPHORE); in bdx_fw_load()
326 if (!READ_REG(priv, regINIT_STATUS) && master) { in bdx_fw_load()
334 if (READ_REG(priv, regINIT_STATUS)) { in bdx_fw_load()
351 READ_REG(priv, regVPC), in bdx_fw_load()
352 READ_REG(priv, regVIC), in bdx_fw_load()
353 READ_REG(priv, regINIT_STATUS), i); in bdx_fw_load()
[all …]
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| D | tehuti.h | 98 #define READ_REG(pp, reg) readl(pp->pBdxRegs + reg) macro
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| /drivers/parisc/ |
| D | sba_iommu.c | 135 #define READ_REG(addr) READ_REG64(addr) macro
138 #define READ_REG(addr) READ_REG32(addr) macro
835 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */ in sba_unmap_single()
844 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */ in sba_unmap_single()
1268 ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE); in sba_ioc_init_pluto()
1269 iova_space_size = ~(READ_REG(ioc->ioc_hpa + IOC_IMASK) & 0xFFFFFFFFUL) + 1; in sba_ioc_init_pluto()
1554 ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL); in sba_hw_init()
1626 cfg_val = READ_REG(rope_cfg); in sba_hw_init()
1638 READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL); in sba_hw_init()
1642 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40), in sba_hw_init()
[all …]
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| D | lba_pci.c | 808 t = READ_REG##size(astro_iop_base + addr); \
891 t = READ_REG##size(PIOP_TO_GMMIO(LBA_DEV(l), addr)); \
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| /drivers/ata/ |
| D | pata_opti.c | 39 READ_REG = 0, /* index of Read cycle timing register */ enumerator
143 opti_write_reg(ap, data_rec_timing[clock][pio], READ_REG); in opti_set_piomode()
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| D | pata_optidma.c | 38 READ_REG = 0, /* index of Read cycle timing register */ enumerator
169 iowrite8(data_rec_timing[pci_clock][pio], regio + READ_REG); in optidma_mode_setup()
172 iowrite8(dma_data_rec_timing[pci_clock][dma], regio + READ_REG); in optidma_mode_setup()
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| /drivers/ide/ |
| D | opti621.c | 23 #define READ_REG 0 /* index of Read cycle timing register */ macro
115 write_reg(tim, READ_REG); in opti621_set_pio_mode()
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| /drivers/staging/rts_pstor/ |
| D | ms.h | 49 #define READ_REG 0x04 macro
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| D | ms.c | 561 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, READ_REG, 6, NO_WAIT_INT); in ms_identify_media_type()
1192 retval = ms_read_bytes(chip, READ_REG, 2, NO_WAIT_INT, val, 2); in ms_read_status_reg()
1273 retval = ms_read_bytes(chip, READ_REG, MS_EXTRA_SIZE, NO_WAIT_INT, data, MS_EXTRA_SIZE); in ms_read_extra_data()
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| /drivers/staging/rts5139/ |
| D | ms.h | 52 #define READ_REG 0x04 macro
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| D | ms.c | 659 ms_transfer_tpc(chip, MS_TM_READ_BYTES, READ_REG, 6, in ms_identify_media_type()
1259 retval = ms_read_bytes(chip, READ_REG, 2, NO_WAIT_INT, val, 2);
1315 ms_read_bytes(chip, READ_REG, MS_EXTRA_SIZE, NO_WAIT_INT, extra,
1379 ms_read_bytes(chip, READ_REG, MS_EXTRA_SIZE, NO_WAIT_INT, data,
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| /drivers/staging/bcm/ |
| D | Debug.h | 73 #define READ_REG (MP<<3) macro
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| /drivers/staging/rtl8712/ |
| D | rtl871x_mp_ioctl.h | 359 GEN_MP_IOCTL_SUBCODE(READ_REG), /*2*/
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| /drivers/atm/ |
| D | iphase.h | 152 #define READ_REG 0x5 macro
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| D | iphase.c | 2811 case READ_REG:
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