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Searched refs:reg_shift (Results 1 – 8 of 8) sorted by relevance

/arch/powerpc/boot/
Dvirtex.c31 u32 reg_shift, reg_offset, clk, spd; in virtex_ns16550_console_init() local
42 n = getprop(devp, "reg-shift", &reg_shift, sizeof(reg_shift)); in virtex_ns16550_console_init()
43 if (n != sizeof(reg_shift)) in virtex_ns16550_console_init()
44 reg_shift = 0; in virtex_ns16550_console_init()
58 out_8(reg_base + (UART_LCR << reg_shift), UART_LCR_DLAB); in virtex_ns16550_console_init()
61 out_8(reg_base + (UART_DLL << reg_shift), divisor & 0xFF); in virtex_ns16550_console_init()
62 out_8(reg_base + (UART_DLM << reg_shift), divisor >> 8); in virtex_ns16550_console_init()
65 out_8(reg_base + (UART_LCR << reg_shift), UART_LCR_WLEN8); in virtex_ns16550_console_init()
68 out_8(reg_base + (UART_MCR << reg_shift), UART_MCR_RTS | UART_MCR_DTR); in virtex_ns16550_console_init()
71 out_8(reg_base + (UART_FCR << reg_shift), in virtex_ns16550_console_init()
Dns16550.c30 static u32 reg_shift; variable
34 out_8(reg_base + (UART_FCR << reg_shift), 0x06); in ns16550_open()
40 while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_THRE) == 0); in ns16550_putc()
46 while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) == 0); in ns16550_getc()
52 return ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) != 0); in ns16550_tstc()
67 n = getprop(devp, "reg-shift", &reg_shift, sizeof(reg_shift)); in ns16550_console_init()
68 if (n != sizeof(reg_shift)) in ns16550_console_init()
69 reg_shift = 0; in ns16550_console_init()
/arch/arm/mach-pxa/include/mach/
Dpata_pxa.h28 uint32_t reg_shift; member
/arch/mips/bcm47xx/
Dserial.c42 p->regshift = ssb_port->reg_shift; in uart8250_init_ssb()
67 p->regshift = bcma_port->reg_shift; in uart8250_init_bcma()
/arch/arm/mach-tegra/
Dtegra2_clocks.c457 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON; in tegra2_bus_clk_init()
458 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1; in tegra2_bus_clk_init()
470 val &= ~(BUS_CLK_DISABLE << c->reg_shift); in tegra2_bus_clk_enable()
486 val |= BUS_CLK_DISABLE << c->reg_shift; in tegra2_bus_clk_disable()
505 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift); in tegra2_bus_clk_set_rate()
506 val |= (i - 1) << c->reg_shift; in tegra2_bus_clk_set_rate()
764 val >>= c->reg_shift; in tegra2_pll_div_clk_init()
792 new_val = val >> c->reg_shift; in tegra2_pll_div_clk_enable()
797 val &= ~(0xFFFF << c->reg_shift); in tegra2_pll_div_clk_enable()
798 val |= new_val << c->reg_shift; in tegra2_pll_div_clk_enable()
[all …]
Dtegra30_clocks.c142 #define AUDIO_SYNC_TAP_NIBBLE_SHIFT(c) ((c->reg_shift - 24) * 4)
1273 val >>= c->reg_shift; in tegra30_pll_div_clk_init()
1303 new_val = val >> c->reg_shift; in tegra30_pll_div_clk_enable()
1308 val &= ~(0xFFFF << c->reg_shift); in tegra30_pll_div_clk_enable()
1309 val |= new_val << c->reg_shift; in tegra30_pll_div_clk_enable()
1326 new_val = val >> c->reg_shift; in tegra30_pll_div_clk_disable()
1331 val &= ~(0xFFFF << c->reg_shift); in tegra30_pll_div_clk_disable()
1332 val |= new_val << c->reg_shift; in tegra30_pll_div_clk_disable()
1350 new_val = val >> c->reg_shift; in tegra30_pll_div_clk_set_rate()
1357 val &= ~(0xFFFF << c->reg_shift); in tegra30_pll_div_clk_set_rate()
[all …]
Dclock.h113 u32 reg_shift; member
/arch/arm/mach-pxa/
Dvpac270.c591 .reg_shift = 1,