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Searched refs:sel (Results 1 – 21 of 21) sorted by relevance

/arch/arm/mach-dove/
Dmpp.c70 static void dove_mpp_cfg_nfc(int sel) in dove_mpp_cfg_nfc() argument
75 mpp_gen_cfg |= sel; in dove_mpp_cfg_nfc()
81 static void dove_mpp_cfg_au1(int sel) in dove_mpp_cfg_au1() argument
93 if (!sel || sel == 0x2) in dove_mpp_cfg_au1()
98 if (sel & 0x1) { in dove_mpp_cfg_au1()
102 if (sel & 0x2) { in dove_mpp_cfg_au1()
106 if (sel & 0x4) { in dove_mpp_cfg_au1()
110 if (sel & 0x8) in dove_mpp_cfg_au1()
128 unsigned int sel = MPP_SEL(*mpp_grp_list); in dove_mpp_conf_grp() local
136 mpp_ctrl4 |= sel << num; in dove_mpp_conf_grp()
[all …]
/arch/powerpc/perf/
Dmpc7450-pmu.c83 int pmc, sel; in mpc7450_threshold_use() local
86 sel = event & PM_PMCSEL_MSK; in mpc7450_threshold_use()
89 if (sel == 0x1e || sel == 0x1f) in mpc7450_threshold_use()
91 if (sel == 0x28 || sel == 0x2b) in mpc7450_threshold_use()
95 if (sel == 0x20) in mpc7450_threshold_use()
99 if (sel == 0xc || sel == 0xd) in mpc7450_threshold_use()
101 if (sel == 0x11) in mpc7450_threshold_use()
105 if (sel == 0x10) in mpc7450_threshold_use()
/arch/mips/include/asm/
Dmipsmtregs.h260 #define mftc0(rt,sel) \ argument
268 " # mftc0 $1, $" #rt ", " #sel " \n" \
269 " .word 0x41000800 | (" #rt " << 16) | " #sel " \n" \
294 #define mftr(rt, u, sel) \ argument
299 " mftr %0, " #rt ", " #u ", " #sel " \n" \
318 #define mttc0(rd, sel, v) \ argument
325 " # mttc0 %0," #rd ", " #sel " \n" \
326 " .word 0x41810000 | (" #rd " << 11) | " #sel " \n" \
333 #define mttr(rd, u, sel, v) \ argument
336 "mttr %0," #rd ", " #u ", " #sel \
Dasmmacro.h84 .macro MFTR rt=0, rd=0, u=0, sel=0
85 .word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
88 .macro MTTR rt=0, rd=0, u=0, sel=0
89 .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
Dmipsregs.h667 #define __read_32bit_c0_register(source, sel) \ argument
669 if (sel == 0) \
676 "mfc0\t%0, " #source ", " #sel "\n\t" \
682 #define __read_64bit_c0_register(source, sel) \ argument
685 __res = __read_64bit_c0_split(source, sel); \
686 else if (sel == 0) \
695 "dmfc0\t%0, " #source ", " #sel "\n\t" \
701 #define __write_32bit_c0_register(register, sel, value) \ argument
703 if (sel == 0) \
710 "mtc0\t%z0, " #register ", " #sel "\n\t" \
[all …]
/arch/arm/mach-tegra/
Dtegra30_clocks.c589 const struct clk_mux_sel *sel; in tegra30_super_clk_init() local
599 for (sel = c->inputs; sel->input != NULL; sel++) { in tegra30_super_clk_init()
600 if (sel->value == source) in tegra30_super_clk_init()
603 BUG_ON(sel->input == NULL); in tegra30_super_clk_init()
604 c->parent = sel->input; in tegra30_super_clk_init()
633 const struct clk_mux_sel *sel; in tegra30_super_clk_set_parent() local
641 for (sel = c->inputs; sel->input != NULL; sel++) { in tegra30_super_clk_set_parent()
642 if (sel->input == p) { in tegra30_super_clk_set_parent()
647 ((sel->value ^ val) & SUPER_LP_DIV2_BYPASS)) { in tegra30_super_clk_set_parent()
654 val |= (sel->value & SUPER_SOURCE_MASK) << shift; in tegra30_super_clk_set_parent()
[all …]
Dtegra2_clocks.c292 const struct clk_mux_sel *sel; in tegra2_super_clk_init() local
300 for (sel = c->inputs; sel->input != NULL; sel++) { in tegra2_super_clk_init()
301 if (sel->value == source) in tegra2_super_clk_init()
304 BUG_ON(sel->input == NULL); in tegra2_super_clk_init()
305 c->parent = sel->input; in tegra2_super_clk_init()
325 const struct clk_mux_sel *sel; in tegra2_super_clk_set_parent() local
333 for (sel = c->inputs; sel->input != NULL; sel++) { in tegra2_super_clk_set_parent()
334 if (sel->input == p) { in tegra2_super_clk_set_parent()
336 val |= sel->value << shift; in tegra2_super_clk_set_parent()
669 const struct clk_pll_freq_table *sel; in tegra2_pll_clk_set_rate() local
[all …]
Dclock.h133 u32 sel; member
/arch/arm/mach-imx/
Dclock-imx35.c111 unsigned char arm, ahb, sel; member
115 { .arm = 1, .ahb = 4, .sel = 0},
116 { .arm = 1, .ahb = 3, .sel = 1},
117 { .arm = 2, .ahb = 2, .sel = 0},
118 { .arm = 0, .ahb = 0, .sel = 0},
119 { .arm = 0, .ahb = 0, .sel = 0},
120 { .arm = 0, .ahb = 0, .sel = 0},
121 { .arm = 4, .ahb = 1, .sel = 0},
122 { .arm = 1, .ahb = 5, .sel = 0},
123 { .arm = 1, .ahb = 8, .sel = 0},
[all …]
/arch/arm/plat-orion/
Dmpp.c43 unsigned int sel = MPP_SEL(*mpp_list); in orion_mpp_conf() local
60 mpp_ctrl[num / 8] |= sel << shift; in orion_mpp_conf()
/arch/x86/boot/
Dvideo.c201 unsigned int sel; in mode_menu() local
222 sel = get_entry(); in mode_menu()
223 if (sel != SCAN) in mode_menu()
224 return sel; in mode_menu()
/arch/arm/plat-samsung/include/plat/
Ddma-s3c24xx.h47 extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
/arch/arm/mach-msm/
Dacpuclock-arm11.c439 uint32_t div, sel; in acpuclk_init() local
448 sel = (readl(A11S_CLK_CNTL_ADDR) >> 12) & 0x7; in acpuclk_init()
453 sel = (readl(A11S_CLK_CNTL_ADDR) >> 4) & 0x07; in acpuclk_init()
459 if (speed->a11clk_src_sel == sel in acpuclk_init()
/arch/x86/oprofile/
Dop_model_p4.c353 #define ESCR_SET_EVENT_SELECT(escr, sel) ((escr) |= (((sel) & 0x3f) << 25)) argument
359 #define CCCR_SET_ESCR_SELECT(cccr, sel) ((cccr) |= (((sel) & 0x07) << 13)) argument
/arch/arm/plat-s3c24xx/
Ddma.c1433 int __init s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel) in s3c24xx_dma_init_map() argument
1436 size_t map_sz = sizeof(*nmap) * sel->map_size; in s3c24xx_dma_init_map()
1439 nmap = kmemdup(sel->map, map_sz, GFP_KERNEL); in s3c24xx_dma_init_map()
1443 memcpy(&dma_sel, sel, sizeof(*sel)); in s3c24xx_dma_init_map()
1447 for (ptr = 0; ptr < sel->map_size; ptr++) in s3c24xx_dma_init_map()
/arch/cris/include/arch-v32/arch/hwregs/
Data_defs.h121 unsigned int sel : 2; member
/arch/x86/include/asm/
Dperf_event_p4.h296 #define P4_OPCODE_PACK(event, sel) (((event) << 8) | sel) argument
Dkvm_host.h859 static inline void kvm_load_ldt(u16 sel) in kvm_load_ldt() argument
861 asm("lldt %0" : : "rm"(sel)); in kvm_load_ldt()
/arch/x86/kvm/
Demulate.c569 u16 sel; in __linearize() local
581 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL, in __linearize()
605 rpl = sel & 3; in __linearize()
1178 u16 sel; in get_descriptor_table_ptr() local
1181 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR)) in get_descriptor_table_ptr()
1684 unsigned short sel; in em_jmp_far() local
1686 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); in em_jmp_far()
1688 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS); in em_jmp_far()
1870 unsigned short sel; in em_lseg() local
1873 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); in em_lseg()
[all …]
/arch/powerpc/boot/dts/
Dmpc832x_mds.dts235 * port pin dir drain sel irq
/arch/mips/include/asm/octeon/
Dcvmx-ciu-defs.h1672 uint64_t sel:3; member