1/* 2 * Copyright (C) 2011 Picochip, Jamie Iles 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13/include/ "skeleton.dtsi" 14/ { 15 model = "Picochip picoXcell PC3X3"; 16 compatible = "picochip,pc3x3"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu@0 { 25 compatible = "arm,1176jz-s"; 26 cpu-clock = <&arm_clk>, "cpu"; 27 reg = <0>; 28 d-cache-line-size = <32>; 29 d-cache-size = <32768>; 30 i-cache-line-size = <32>; 31 i-cache-size = <32768>; 32 }; 33 }; 34 35 clocks { 36 #address-cells = <1>; 37 #size-cells = <1>; 38 ranges; 39 40 clkgate: clkgate@800a0048 { 41 #address-cells = <1>; 42 #size-cells = <0>; 43 reg = <0x800a0048 4>; 44 compatible = "picochip,pc3x3-clk-gate"; 45 46 tzprot_clk: clock@0 { 47 compatible = "picochip,pc3x3-gated-clk"; 48 clock-outputs = "bus"; 49 picochip,clk-disable-bit = <0>; 50 clock-frequency = <200000000>; 51 ref-clock = <&ref_clk>, "ref"; 52 }; 53 54 spi_clk: clock@1 { 55 compatible = "picochip,pc3x3-gated-clk"; 56 clock-outputs = "bus"; 57 picochip,clk-disable-bit = <1>; 58 clock-frequency = <200000000>; 59 ref-clock = <&ref_clk>, "ref"; 60 }; 61 62 dmac0_clk: clock@2 { 63 compatible = "picochip,pc3x3-gated-clk"; 64 clock-outputs = "bus"; 65 picochip,clk-disable-bit = <2>; 66 clock-frequency = <200000000>; 67 ref-clock = <&ref_clk>, "ref"; 68 }; 69 70 dmac1_clk: clock@3 { 71 compatible = "picochip,pc3x3-gated-clk"; 72 clock-outputs = "bus"; 73 picochip,clk-disable-bit = <3>; 74 clock-frequency = <200000000>; 75 ref-clock = <&ref_clk>, "ref"; 76 }; 77 78 ebi_clk: clock@4 { 79 compatible = "picochip,pc3x3-gated-clk"; 80 clock-outputs = "bus"; 81 picochip,clk-disable-bit = <4>; 82 clock-frequency = <200000000>; 83 ref-clock = <&ref_clk>, "ref"; 84 }; 85 86 ipsec_clk: clock@5 { 87 compatible = "picochip,pc3x3-gated-clk"; 88 clock-outputs = "bus"; 89 picochip,clk-disable-bit = <5>; 90 clock-frequency = <200000000>; 91 ref-clock = <&ref_clk>, "ref"; 92 }; 93 94 l2_clk: clock@6 { 95 compatible = "picochip,pc3x3-gated-clk"; 96 clock-outputs = "bus"; 97 picochip,clk-disable-bit = <6>; 98 clock-frequency = <200000000>; 99 ref-clock = <&ref_clk>, "ref"; 100 }; 101 102 trng_clk: clock@7 { 103 compatible = "picochip,pc3x3-gated-clk"; 104 clock-outputs = "bus"; 105 picochip,clk-disable-bit = <7>; 106 clock-frequency = <200000000>; 107 ref-clock = <&ref_clk>, "ref"; 108 }; 109 110 fuse_clk: clock@8 { 111 compatible = "picochip,pc3x3-gated-clk"; 112 clock-outputs = "bus"; 113 picochip,clk-disable-bit = <8>; 114 clock-frequency = <200000000>; 115 ref-clock = <&ref_clk>, "ref"; 116 }; 117 118 otp_clk: clock@9 { 119 compatible = "picochip,pc3x3-gated-clk"; 120 clock-outputs = "bus"; 121 picochip,clk-disable-bit = <9>; 122 clock-frequency = <200000000>; 123 ref-clock = <&ref_clk>, "ref"; 124 }; 125 }; 126 127 arm_clk: clock@11 { 128 compatible = "picochip,pc3x3-pll"; 129 reg = <0x800a0050 0x8>; 130 picochip,min-freq = <140000000>; 131 picochip,max-freq = <700000000>; 132 ref-clock = <&ref_clk>, "ref"; 133 clock-outputs = "cpu"; 134 }; 135 136 pclk: clock@12 { 137 compatible = "fixed-clock"; 138 clock-outputs = "bus", "pclk"; 139 clock-frequency = <200000000>; 140 ref-clock = <&ref_clk>, "ref"; 141 }; 142 }; 143 144 paxi { 145 compatible = "simple-bus"; 146 #address-cells = <1>; 147 #size-cells = <1>; 148 ranges = <0 0x80000000 0x400000>; 149 150 emac: gem@30000 { 151 compatible = "cadence,gem"; 152 reg = <0x30000 0x10000>; 153 interrupt-parent = <&vic0>; 154 interrupts = <31>; 155 }; 156 157 dmac1: dmac@40000 { 158 compatible = "snps,dw-dmac"; 159 reg = <0x40000 0x10000>; 160 interrupt-parent = <&vic0>; 161 interrupts = <25>; 162 }; 163 164 dmac2: dmac@50000 { 165 compatible = "snps,dw-dmac"; 166 reg = <0x50000 0x10000>; 167 interrupt-parent = <&vic0>; 168 interrupts = <26>; 169 }; 170 171 vic0: interrupt-controller@60000 { 172 compatible = "arm,pl192-vic"; 173 interrupt-controller; 174 reg = <0x60000 0x1000>; 175 #interrupt-cells = <1>; 176 }; 177 178 vic1: interrupt-controller@64000 { 179 compatible = "arm,pl192-vic"; 180 interrupt-controller; 181 reg = <0x64000 0x1000>; 182 #interrupt-cells = <1>; 183 }; 184 185 fuse: picoxcell-fuse@80000 { 186 compatible = "picoxcell,fuse-pc3x3"; 187 reg = <0x80000 0x10000>; 188 }; 189 190 ssi: picoxcell-spi@90000 { 191 compatible = "picoxcell,spi"; 192 reg = <0x90000 0x10000>; 193 interrupt-parent = <&vic0>; 194 interrupts = <10>; 195 }; 196 197 ipsec: spacc@100000 { 198 compatible = "picochip,spacc-ipsec"; 199 reg = <0x100000 0x10000>; 200 interrupt-parent = <&vic0>; 201 interrupts = <24>; 202 ref-clock = <&ipsec_clk>, "ref"; 203 }; 204 205 srtp: spacc@140000 { 206 compatible = "picochip,spacc-srtp"; 207 reg = <0x140000 0x10000>; 208 interrupt-parent = <&vic0>; 209 interrupts = <23>; 210 }; 211 212 l2_engine: spacc@180000 { 213 compatible = "picochip,spacc-l2"; 214 reg = <0x180000 0x10000>; 215 interrupt-parent = <&vic0>; 216 interrupts = <22>; 217 ref-clock = <&l2_clk>, "ref"; 218 }; 219 220 apb { 221 compatible = "simple-bus"; 222 #address-cells = <1>; 223 #size-cells = <1>; 224 ranges = <0 0x200000 0x80000>; 225 226 rtc0: rtc@00000 { 227 compatible = "picochip,pc3x2-rtc"; 228 clock-freq = <200000000>; 229 reg = <0x00000 0xf>; 230 interrupt-parent = <&vic0>; 231 interrupts = <8>; 232 }; 233 234 timer0: timer@10000 { 235 compatible = "picochip,pc3x2-timer"; 236 interrupt-parent = <&vic0>; 237 interrupts = <4>; 238 clock-freq = <200000000>; 239 reg = <0x10000 0x14>; 240 }; 241 242 timer1: timer@10014 { 243 compatible = "picochip,pc3x2-timer"; 244 interrupt-parent = <&vic0>; 245 interrupts = <5>; 246 clock-freq = <200000000>; 247 reg = <0x10014 0x14>; 248 }; 249 250 gpio: gpio@20000 { 251 compatible = "snps,dw-apb-gpio"; 252 reg = <0x20000 0x1000>; 253 #address-cells = <1>; 254 #size-cells = <0>; 255 reg-io-width = <4>; 256 257 banka: gpio-controller@0 { 258 compatible = "snps,dw-apb-gpio-bank"; 259 gpio-controller; 260 #gpio-cells = <2>; 261 gpio-generic,nr-gpio = <8>; 262 263 regoffset-dat = <0x50>; 264 regoffset-set = <0x00>; 265 regoffset-dirout = <0x04>; 266 }; 267 268 bankb: gpio-controller@1 { 269 compatible = "snps,dw-apb-gpio-bank"; 270 gpio-controller; 271 #gpio-cells = <2>; 272 gpio-generic,nr-gpio = <16>; 273 274 regoffset-dat = <0x54>; 275 regoffset-set = <0x0c>; 276 regoffset-dirout = <0x10>; 277 }; 278 279 bankd: gpio-controller@2 { 280 compatible = "snps,dw-apb-gpio-bank"; 281 gpio-controller; 282 #gpio-cells = <2>; 283 gpio-generic,nr-gpio = <30>; 284 285 regoffset-dat = <0x5c>; 286 regoffset-set = <0x24>; 287 regoffset-dirout = <0x28>; 288 }; 289 }; 290 291 uart0: uart@30000 { 292 compatible = "snps,dw-apb-uart"; 293 reg = <0x30000 0x1000>; 294 interrupt-parent = <&vic1>; 295 interrupts = <10>; 296 clock-frequency = <3686400>; 297 reg-shift = <2>; 298 reg-io-width = <4>; 299 }; 300 301 uart1: uart@40000 { 302 compatible = "snps,dw-apb-uart"; 303 reg = <0x40000 0x1000>; 304 interrupt-parent = <&vic1>; 305 interrupts = <9>; 306 clock-frequency = <3686400>; 307 reg-shift = <2>; 308 reg-io-width = <4>; 309 }; 310 311 wdog: watchdog@50000 { 312 compatible = "snps,dw-apb-wdg"; 313 reg = <0x50000 0x10000>; 314 interrupt-parent = <&vic0>; 315 interrupts = <11>; 316 bus-clock = <&pclk>, "bus"; 317 }; 318 319 timer2: timer@60000 { 320 compatible = "picochip,pc3x2-timer"; 321 interrupt-parent = <&vic0>; 322 interrupts = <6>; 323 clock-freq = <200000000>; 324 reg = <0x60000 0x14>; 325 }; 326 327 timer3: timer@60014 { 328 compatible = "picochip,pc3x2-timer"; 329 interrupt-parent = <&vic0>; 330 interrupts = <7>; 331 clock-freq = <200000000>; 332 reg = <0x60014 0x14>; 333 }; 334 }; 335 }; 336 337 rwid-axi { 338 #address-cells = <1>; 339 #size-cells = <1>; 340 compatible = "simple-bus"; 341 ranges; 342 343 ebi@50000000 { 344 compatible = "simple-bus"; 345 #address-cells = <2>; 346 #size-cells = <1>; 347 ranges = <0 0 0x40000000 0x08000000 348 1 0 0x48000000 0x08000000 349 2 0 0x50000000 0x08000000 350 3 0 0x58000000 0x08000000>; 351 }; 352 353 axi2pico@c0000000 { 354 compatible = "picochip,axi2pico-pc3x3"; 355 reg = <0xc0000000 0x10000>; 356 interrupt-parent = <&vic0>; 357 interrupts = <13 14 15 16 17 18 19 20 21>; 358 }; 359 360 otp@ffff8000 { 361 compatible = "picochip,otp-pc3x3"; 362 reg = <0xffff8000 0x8000>; 363 }; 364 }; 365}; 366