1 #ifndef __ASM_ARM_CPUTYPE_H
2 #define __ASM_ARM_CPUTYPE_H
3
4 #include <linux/stringify.h>
5 #include <linux/kernel.h>
6
7 #define CPUID_ID 0
8 #define CPUID_CACHETYPE 1
9 #define CPUID_TCM 2
10 #define CPUID_TLBTYPE 3
11 #define CPUID_MPIDR 5
12
13 #define CPUID_EXT_PFR0 "c1, 0"
14 #define CPUID_EXT_PFR1 "c1, 1"
15 #define CPUID_EXT_DFR0 "c1, 2"
16 #define CPUID_EXT_AFR0 "c1, 3"
17 #define CPUID_EXT_MMFR0 "c1, 4"
18 #define CPUID_EXT_MMFR1 "c1, 5"
19 #define CPUID_EXT_MMFR2 "c1, 6"
20 #define CPUID_EXT_MMFR3 "c1, 7"
21 #define CPUID_EXT_ISAR0 "c2, 0"
22 #define CPUID_EXT_ISAR1 "c2, 1"
23 #define CPUID_EXT_ISAR2 "c2, 2"
24 #define CPUID_EXT_ISAR3 "c2, 3"
25 #define CPUID_EXT_ISAR4 "c2, 4"
26 #define CPUID_EXT_ISAR5 "c2, 5"
27
28 extern unsigned int processor_id;
29
30 #ifdef CONFIG_CPU_CP15
31 #define read_cpuid(reg) \
32 ({ \
33 unsigned int __val; \
34 asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \
35 : "=r" (__val) \
36 : \
37 : "cc"); \
38 __val; \
39 })
40 #define read_cpuid_ext(ext_reg) \
41 ({ \
42 unsigned int __val; \
43 asm("mrc p15, 0, %0, c0, " ext_reg \
44 : "=r" (__val) \
45 : \
46 : "cc"); \
47 __val; \
48 })
49 #else
50 #define read_cpuid(reg) (processor_id)
51 #define read_cpuid_ext(reg) 0
52 #endif
53
54 /*
55 * The CPU ID never changes at run time, so we might as well tell the
56 * compiler that it's constant. Use this function to read the CPU ID
57 * rather than directly reading processor_id or read_cpuid() directly.
58 */
read_cpuid_id(void)59 static inline unsigned int __attribute_const__ read_cpuid_id(void)
60 {
61 return read_cpuid(CPUID_ID);
62 }
63
read_cpuid_cachetype(void)64 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
65 {
66 return read_cpuid(CPUID_CACHETYPE);
67 }
68
read_cpuid_tcmstatus(void)69 static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
70 {
71 return read_cpuid(CPUID_TCM);
72 }
73
read_cpuid_mpidr(void)74 static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)
75 {
76 return read_cpuid(CPUID_MPIDR);
77 }
78
79 /*
80 * Intel's XScale3 core supports some v6 features (supersections, L2)
81 * but advertises itself as v5 as it does not support the v6 ISA. For
82 * this reason, we need a way to explicitly test for this type of CPU.
83 */
84 #ifndef CONFIG_CPU_XSC3
85 #define cpu_is_xsc3() 0
86 #else
cpu_is_xsc3(void)87 static inline int cpu_is_xsc3(void)
88 {
89 unsigned int id;
90 id = read_cpuid_id() & 0xffffe000;
91 /* It covers both Intel ID and Marvell ID */
92 if ((id == 0x69056000) || (id == 0x56056000))
93 return 1;
94
95 return 0;
96 }
97 #endif
98
99 #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
100 #define cpu_is_xscale() 0
101 #else
102 #define cpu_is_xscale() 1
103 #endif
104
105 #endif
106